From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B91363998B2; Wed, 3 Jun 2026 19:20:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780514451; cv=none; b=hkG2Z8mP6acHDgJRYDEjQY6ezkMBvSQ5LICQT+YzZC6UqNq1ISE8vvx48qtFcZAwN34Q5iWxthgSiGeVQd/HCrAtT8qFDHgxJhPtXWIWW1NEiclURpnpGvPrPDlWwiMfEbq2OJ+Gi84dwRCf8/tpYldDPhlQBWITk6ZUeAiBVvs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780514451; c=relaxed/simple; bh=fcF2L2qJqR2J21wKlux/XhaLbrXjW+w0lA8W8N2pVNw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=olR8Mdgqpy7vs0M4D1kh/u8+kC0mAimlm59aQ05nCM8eNDJsmOVQ3qE0sEEKABfoNdZM0Pj6HXGM4iHwwjxz6nZlGZj+mq2nuTyq63pyp7J2Sc9Tv8NZcnnNkA/btcJlItscG3ffgfwLN186xWyc3AFR7z7eX8ILxsUZkmRIHwg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=D3vsA/4Z; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="D3vsA/4Z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C82211F00893; Wed, 3 Jun 2026 19:20:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1780514450; bh=MtjugWZzUUxCR/pWyiEIyzLKQZNA0zi91c/pvTORnJM=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=D3vsA/4Z35OrFgCjgF40/eXW5TJAQt/6K5xRMUlikV5XNelSI2ac8CNw3Zvwj7h8m nuYuycK3K2X048XKTLEhV6VNA1rVQFTMZBieZErbsYdVNKnLLiFrTsWjCbd59vdDmh XbnT/cNoDkDJ1LG9GBazWWBBRNBtEbG9MXX898PeRdxQ94hUS1jWJ1BP6c+3Ikjmf8 mwFk9zG6KpacopBieevces+QQWYAsGujLChs329wN5Rn3JoVC17ri9yWm6t7MZZiNn SuZt2DWTNZxP6X6Cy2uX8Jw2iyLUuj0MGtPqHW7vNIqzjJjPL1phaDNN3hhdveJLWV Az2tXqaTNbsuA== Received: from phl-compute-05.internal (phl-compute-05.internal [10.202.2.45]) by mailfauth.phl.internal (Postfix) with ESMTP id E6188F4007A; Wed, 3 Jun 2026 15:20:47 -0400 (EDT) Received: from phl-frontend-04 ([10.202.2.163]) by phl-compute-05.internal (MEProxy); Wed, 03 Jun 2026 15:20:47 -0400 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: dmFkZTEeKZPKaxEW7sI+Y0OjRzaTROUW6RyGxvT1JY5zke8k7MdMeqjg5c3T8fCY/y7cWI j189K4S4lRXCvuW5BKdmiZ9flLa/Fp/BwLhxLdkpITLAAAHtEOChqQHhh39QPW0zEpiW9X qSGozLU6iDQyostAWt5KJUHnZDit/hu8dIn86X3JZQxg6wdJb1GrQzxuTLCyK3oUG6IAr4 pA05MXi4+NjX2ZoyYefPheB+TPrymPSqGDOr+CgAAJddhHa49XUIPsiByV7vq4hOEKWskK Yu1enfoCKCyoPA3E/cV9cQEoN32DMeCrsN4HMNtD5WETRMRYCdN8ifZkJu5o7GJtbGgwQA tzd1q0CuKP6VWNIojSIWR4qkzbondVmNLu9zoDeAf8jlTdEJqku1mjELUs+derQnRNqtRP G78II45sF1gi4xAlp7aBtJ3SVdwV+LorBCq8nvlmWQ/sK9LCoOTIEujTVRB0uRGERSdBC8 vEVKF7o7adHUQwV4aUQBOxDiyzeuua9nvw4uR+EfnO5xqSBuI730Yxy027VJgnvdgGGZ/h 9gm5IpclBU9LqeZmDprL8aXAGLDlT4H1k9mU3F9PdsbfBm1FAFUUDg/Y5dtUWXVnunMtvX 9StD62X568WMdQZLz4Zpldz1ousET1wIueR9kkQrmHyNHEFM68Y+n9mEBM8w X-ME-Proxy: Feedback-ID: i8dbe485b:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 3 Jun 2026 15:20:46 -0400 (EDT) Date: Wed, 3 Jun 2026 12:20:45 -0700 From: Boqun Feng To: Peter Zijlstra Cc: Catalin Marinas , Will Deacon , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Heiko Carstens , Vasily Gorbik , Alexander Gordeev , Christian Borntraeger , Sven Schnelle , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Arnd Bergmann , Juri Lelli , Vincent Guittot , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Waiman Long , Andrew Morton , Andrii Nakryiko , Eduard Zingerman , Alexei Starovoitov , Daniel Borkmann , Martin KaFai Lau , Kumar Kartikeya Dwivedi , Song Liu , Yonghong Song , Jiri Olsa , Shuah Khan , Miguel Ojeda , Gary Guo , =?iso-8859-1?Q?Bj=F6rn?= Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Jinjie Ruan , Lyude Paul , Thomas Huth , Sohil Mehta , "Xin Li (Intel)" , Pawan Gupta , Nikunj A Dadhania , Joel Fernandes , Andy Shevchenko , Randy Dunlap , Yury Norov , Sebastian Andrzej Siewior , linux-kernel@vger.kernel.org, linux-openrisc@vger.kernel.org, linux-s390@vger.kernel.org, linux-arch@vger.kernel.org, bpf@vger.kernel.org, linux-kselftest@vger.kernel.org, rust-for-linux@vger.kernel.org, Onur =?iso-8859-1?Q?=D6zkan?= , Daniel Almeida Subject: Re: [PATCH v2 00/12] Refcounted interrupt disable and SpinLockIrq for rust (Part 1) Message-ID: References: <20260526152148.30514-1-boqun@kernel.org> <20260527161844.GG3102624@noisy.programming.kicks-ass.net> Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, May 27, 2026 at 09:33:53AM -0700, Boqun Feng wrote: > On Wed, May 27, 2026 at 06:18:44PM +0200, Peter Zijlstra wrote: > > On Tue, May 26, 2026 at 08:21:36AM -0700, Boqun Feng wrote: > > > Hi Peter, > > > > > > This is a follow-up for Lyude's work [1]. After learning the current > > > preempt_count() usage and how ARM64 handle this, I came up with this > > > series that could resolve your feedback [2]. The basic idea is based on: > > > > > > 1) preempt_count() previously already masks our NEED_RESCHED bit, so the > > > effective bits is 31bits > > > 2) with a 64bit preempt count implementation (as in your PREEMPT_LONG > > > proposal), the effective bits that record "whether we CAN preempt or > > > not" still fit in 32bit (i.e. an int) > > > > > > as a result, I don't think we need to change the existing > > > preempt_count() API, but rather keep "32bit vs 64bit" as an > > > implementation detail. This saves us the need to change the printk code > > > for preempt_count(). > > > > > > > > v1: https://lore.kernel.org/rust-for-linux/20260508042111.24358-1-boqun@kernel.org/ > > > > > > Changes since v1: > > > > > > * Rename PREEMPT_COUNT_64BIT to HAS_SEPARATE_PREEMPT_RESCHED_BITS per > > > Mark Rutland. > > > > Blergh, so I really don't like that new name. It isn't that > > PREEMPT_RESCHED is separate, it really is a 64bit preempt count. > > > > Shashiko has a few fits, but its mostly being stupid. Although I think > > it might be useful to perhaps put a WARN_ON_ONCE(in_nmi()) in > > local_interrupt_disable(). > > Yes, that's also what I'm thinking of, and also we need to check > local_softirq_pending() in local_interrupt_enable() I think, because now > HARDIRQ_DISABLE bits being non-zero means deferring softirq. (Shashiko > also reported this as well). > After some thoughts on this, I will postpone the idea of checking of local_softirq_pending() in local_interrupt_enable(), because that essientially makes every interrupt enabling a point to trigger softirq, and that's different from the current local_irq_{enable,restore}(). Regards, Boqun > > > > Anyway, I'll re-read things again tomorrow, but I suppose this will do. > > > > Thank you! > > Regards, > Boqun