From: Charlie Jenkins <thecharlesjenkins@gmail.com>
To: Nam Cao <namcao@linutronix.de>
Cc: Charlie Jenkins via B4 Relay
<devnull+thecharlesjenkins.gmail.com@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Conor Dooley <conor@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Andrew Morton <akpm@linux-foundation.org>,
Shuah Khan <shuah@kernel.org>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Subject: Re: [PATCH 01/16] riscv: Introduce instruction table generation
Date: Mon, 15 Jun 2026 22:58:26 -0700 [thread overview]
Message-ID: <ajDmAmq4_hYCDEfp@blinky> (raw)
In-Reply-To: <87se6tejoe.fsf@yellow.woof>
On Thu, Jun 11, 2026 at 07:21:37AM +0200, Nam Cao wrote:
> Charlie Jenkins <thecharlesjenkins@gmail.com> writes:
> > This is a weird one. The Ziclsd extension introduces it for RV32[1]. All
> > of the data is generated from the riscv-unified-db and because it is in
> > the Ziclsd extension, c.ld is included for 32-bit in the c.ld
> > description [2].
>
> Oh :( We probably should amend the base spec to mention that.
>
> >> > + compressed_name=${name##c.*}
> >> ^^^^^^^^^^^^^^^
> >> this name is misleading
> >
> > That's fair, I can rename it to be something like "compressed_inst"?
>
> My issue is that "compressed_name" indicates that it holds the
> compressed variant of the name. But it actually is empty if the
> instruction is compressed, otherwise it is the original instruction name.
>
> I am not sure what is a better name. Perhaps just inline this to the
> usage below.
Oh I see, I'll come up with a name that is more clear on inline it.
>
> Nam
next prev parent reply other threads:[~2026-06-16 5:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-08 4:45 [PATCH 00/16] riscv: Generate riscv instruction functions Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 01/16] riscv: Introduce instruction table generation Charlie Jenkins via B4 Relay
2026-06-10 15:56 ` Nam Cao
2026-06-11 1:06 ` Charlie Jenkins
2026-06-11 5:21 ` Nam Cao
2026-06-16 5:58 ` Charlie Jenkins [this message]
2026-04-08 4:45 ` [PATCH 02/16] riscv: alternatives: Use generated instruction headers for patching code Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 03/16] riscv: kgdb: Use generated instruction headers Charlie Jenkins via B4 Relay
2026-06-11 6:08 ` Nam Cao
2026-06-16 6:02 ` Charlie Jenkins
2026-04-08 4:45 ` [PATCH 04/16] riscv: kprobes: " Charlie Jenkins via B4 Relay
2026-06-11 6:14 ` Nam Cao
2026-06-16 6:06 ` Charlie Jenkins
2026-06-11 6:22 ` Nam Cao
2026-04-08 4:45 ` [PATCH 05/16] riscv: cfi: " Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 06/16] riscv: Use generated instruction headers for misaligned loads/stores Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 07/16] riscv: kvm: Use generated instruction headers for csr code Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 08/16] riscv: kvm: Fix MMIO emulation for sign-extended insns Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 09/16] KVM: device: Add test device Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 10/16] KVM: riscv: selftests: Add mmio test Charlie Jenkins via B4 Relay
2026-04-08 4:45 ` [PATCH 11/16] riscv: kvm: Use generated instruction headers for mmio emulation Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 12/16] riscv: kvm: Add emulated test csr Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 13/16] KVM: riscv: selftests: Add csr emulation test Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 14/16] riscv: kvm: Use generated instruction headers for csr emulation Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 15/16] riscv: kexec: Use generated instruction headers for kexec relocations Charlie Jenkins via B4 Relay
2026-04-08 4:46 ` [PATCH 16/16] riscv: Remove unused instruction headers Charlie Jenkins via B4 Relay
2026-04-08 17:58 ` [PATCH 1/16] riscv: Introduce instruction table generation Charlie Jenkins
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