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From: Reinette Chatre <reinette.chatre@intel.com>
To: Xiaochen Shen <shenxiaochen@open-hieco.net>,
	<tony.luck@intel.com>, <bp@alien8.de>, <fenghuay@nvidia.com>,
	<shuah@kernel.org>, <skhan@linuxfoundation.org>
Cc: <babu.moger@amd.com>, <james.morse@arm.com>,
	<Dave.Martin@arm.com>, <x86@kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-kselftest@vger.kernel.org>
Subject: Re: [PATCH v5 0/4] selftests/resctrl: Add Hygon CPUs support and bug fixes
Date: Thu, 8 Jan 2026 08:02:56 -0800	[thread overview]
Message-ID: <bdecae64-5f6e-42d4-a05b-3334b95e6ec0@intel.com> (raw)
In-Reply-To: <20251217030456.3834956-1-shenxiaochen@open-hieco.net>

Dear Shuah,

Could you please consider this series for inclusion?

Thank you very much.

Reinette

On 12/16/25 7:04 PM, Xiaochen Shen wrote:
> The resctrl selftest currently exhibits several failures on Hygon CPUs
> due to missing vendor detection and edge-case handling specific to
> Hygon's architecture.
> 
> This patch series addresses three distinct issues:
> 1. A division-by-zero crash in SNC detection on some platforms (e.g.,
>    Hygon).
> 2. Missing CPU vendor detection, causing the test to fail with
>    "# Can not get vendor info..." on Hygon CPUs.
> 3. Incorrect handling of non-contiguous CBM support on Hygon CPUs.
> 
> These changes enable resctrl selftest to run successfully on
> Hygon CPUs that support Platform QoS features.
> 
> Maintainer notes:
> -----------------
> Patch 1: selftests/resctrl: Fix a division by zero error on Hygon
>  - This is a candidate for backport with "Fixes:" tag.
> 
> Patch 2: selftests/resctrl: Define CPU vendor IDs as bits to match usage
>  - This is *not* a candidate for backport since it is an enhancement and
>    preparatory patch for patch 3.
> 
> Patch 3: selftests/resctrl: Add CPU vendor detection for Hygon
> Patch 4: selftests/resctrl: Fix non-contiguous CBM check for Hygon
>  - Even though they are fixes they are *not* candidates for backport
>    since they are based on another patch series (x86/resctrl: Fix
>    Platform QoS issues for Hygon) which is in process of being added to
>    resctrl.
> -----------------
> 
> Changelog:
> v5:
> - Patch 2:
>   1. Fix a nit of "reverse fir ordering" of the variable declarations in
>      detect_vendor() in v4 patch series (Reinette).
>   2. Add Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>.
> 
> v4:
> - Cover letter: add maintainer notes outlining how these patches to be
>   handled (Reinette).
> - Re-organize the patch series to move original patch 3 to the beginning
>   of series. The patch order has changed between v3 and v4 (Reinette):
>      v3    ->    v4
>   patch #3 -> patch #1
>   patch #1 -> patch #2
>   patch #2 -> patch #3
>   patch #4 -> patch #4
> - Patch 2:
>   1. Resolve a conflict against latest upstream kernel (Reinette).
>   2. Fix a nit to maintain the reverse fir ordering of variables in
>      detect_vendor() (Reinette).
> - Patch 3: add Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
> - Patch 4: move the maintainer note into the cover letter (Reinette).
> 
> v3:
> - Patch 1:
>   1. Update the return types of detect_vendor() and get_vendor() from
>      'int' to 'unsigned int' to align with their usage as bitmask values
>      and to prevent potentially risky type conversions (Fenghua).
>   2. Split the code changes of "define CPU vendor IDs as bits to match
>      usage" from original patch 1 into a separate patch (this patch,
>      suggested by Fenghua and Reinette).
>   3. Introduce the flag 'initialized' to simplify the get_vendor() ->
>      detect_vendor() logic (Reinette).
> - Patch 2 (original patch 1):
>   1. Move the code changes of "define CPU vendor IDs as bits to match
>      usage" into patch 1.
> - Patch 3 (original patch 2): 
>   1. Fix a nit of code comment for affected platforms (Fenghua).
>   2. Add Reviewed-by: Fenghua Yu <fenghuay@nvidia.com>.
> - Patch 4 (original patch 3): 
>   1. Fix a nit to avoid calling get_vendor() twice (Fenghua).
>   2. Add Reviewed-by: Fenghua Yu <fenghuay@nvidia.com>.
> 
> v2:
> - Patch 1: switch all of the vendor id bitmasks to use BIT() (Reinette)
> - Patch 2: add Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
> - Patch 3: add Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
>            add a maintainer note to highlight it is not a candidate for
> 	   backport (Reinette)
> 
> Xiaochen Shen (4):
>   selftests/resctrl: Fix a division by zero error on Hygon
>   selftests/resctrl: Define CPU vendor IDs as bits to match usage
>   selftests/resctrl: Add CPU vendor detection for Hygon
>   selftests/resctrl: Fix non-contiguous CBM check for Hygon
> 
>  tools/testing/selftests/resctrl/cat_test.c    |  6 ++--
>  tools/testing/selftests/resctrl/resctrl.h     |  8 ++++--
>  .../testing/selftests/resctrl/resctrl_tests.c | 28 +++++++++++++------
>  tools/testing/selftests/resctrl/resctrlfs.c   | 10 +++++++
>  4 files changed, 39 insertions(+), 13 deletions(-)
> 


  parent reply	other threads:[~2026-01-08 16:03 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-17  3:04 [PATCH v5 0/4] selftests/resctrl: Add Hygon CPUs support and bug fixes Xiaochen Shen
2025-12-17  3:04 ` [PATCH v5 1/4] selftests/resctrl: Fix a division by zero error on Hygon Xiaochen Shen
2025-12-17  3:04 ` [PATCH v5 2/4] selftests/resctrl: Define CPU vendor IDs as bits to match usage Xiaochen Shen
2025-12-17  3:04 ` [PATCH v5 3/4] selftests/resctrl: Add CPU vendor detection for Hygon Xiaochen Shen
2025-12-17  3:04 ` [PATCH v5 4/4] selftests/resctrl: Fix non-contiguous CBM check " Xiaochen Shen
2026-01-08 16:02 ` Reinette Chatre [this message]
2026-01-09 23:51   ` [PATCH v5 0/4] selftests/resctrl: Add Hygon CPUs support and bug fixes Shuah
2026-01-10  0:02     ` Reinette Chatre
2026-01-10  7:26       ` Xiaochen Shen

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