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X-CSE-ConnectionGUID: xisnIQS7QG+coeuEwxIDfQ== X-CSE-MsgGUID: /I2CEtdKTLGYW1i8ORBeUg== X-IronPort-AV: E=McAfee;i="6700,10204,11191"; a="24761681" X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="24761681" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2024 00:51:06 -0700 X-CSE-ConnectionGUID: ajRXdtpPQNKqOYG+oecUHg== X-CSE-MsgGUID: cFStQAe4QEW8m1wuEEJ7DQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,219,1719903600"; d="scan'208";a="66915156" Received: from lizhiqua-mobl.ccr.corp.intel.com (HELO [10.124.240.228]) ([10.124.240.228]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Sep 2024 00:51:01 -0700 Message-ID: Date: Wed, 11 Sep 2024 15:50:59 +0800 Precedence: bulk X-Mailing-List: linux-kselftest@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: baolu.lu@linux.intel.com, Jason Gunthorpe , "will@kernel.org" , "joro@8bytes.org" , "suravee.suthikulpanit@amd.com" , "robin.murphy@arm.com" , "dwmw2@infradead.org" , "shuah@kernel.org" , "linux-kernel@vger.kernel.org" , "iommu@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "linux-kselftest@vger.kernel.org" , "eric.auger@redhat.com" , "jean-philippe@linaro.org" , "mdf@kernel.org" , "mshavit@google.com" , "shameerali.kolothum.thodi@huawei.com" , "smostafa@google.com" , "Liu, Yi L" Subject: Re: [PATCH v2 17/19] iommu/arm-smmu-v3: Add arm_smmu_viommu_cache_invalidate To: Nicolin Chen , "Tian, Kevin" References: <4b61aba3bc6c1cce628d9db44d5b18ea567a8be1.1724776335.git.nicolinc@nvidia.com> <20240905162039.GT1358970@nvidia.com> <20240905182148.GA1358970@nvidia.com> Content-Language: en-US From: Baolu Lu In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 2024/9/11 15:20, Nicolin Chen wrote: > On Wed, Sep 11, 2024 at 06:25:16AM +0000, Tian, Kevin wrote: >>> From: Jason Gunthorpe >>> Sent: Friday, September 6, 2024 2:22 AM >>> >>> On Thu, Sep 05, 2024 at 11:00:49AM -0700, Nicolin Chen wrote: >>>> On Thu, Sep 05, 2024 at 01:20:39PM -0300, Jason Gunthorpe wrote: >>>>> On Tue, Aug 27, 2024 at 09:59:54AM -0700, Nicolin Chen wrote: >>>>> >>>>>> +static int arm_smmu_viommu_cache_invalidate(struct >>> iommufd_viommu *viommu, >>>>>> + struct iommu_user_data_array >>> *array) >>>>>> +{ >>>>>> + struct iommu_domain *domain = >>> iommufd_viommu_to_parent_domain(viommu); >>>>>> + >>>>>> + return __arm_smmu_cache_invalidate_user( >>>>>> + to_smmu_domain(domain), viommu, array); >>>>> I'd like to have the viommu struct directly hold the VMID. The nested >>>>> parent should be sharable between multiple viommus, it doesn't make >>>>> any sense that it would hold the vmid. >>>>> >>>>> This is struggling because it is trying too hard to not have the >>>>> driver allocate the viommu, and I think we should just go ahead and do >>>>> that. Store the vmid, today copied from the nesting parent in the vmid >>>>> private struct. No need for iommufd_viommu_to_parent_domain(), just >>>>> rework the APIs to pass the vmid down not a domain. >>>> OK. When I designed all this stuff, we still haven't made mind >>>> about sharing the s2 domain, i.e. moving the VMID, which might >>>> need a couple of more patches to achieve. >>> Yes, many more patches, and don't try to do it now.. But we can copy >>> the vmid from the s2 and place it in the viommu struct during >>> allocation time. >>> >> does it assume that a viommu object cannot span multiple physical >> IOMMUs so there is only one vmid per viommu? > I think so. One the reasons of introducing vIOMMU is to maintain > the shareability across physical IOMMUs at the s2 HWPT_PAGING. My understanding of VMID is something like domain id in x86 arch's. Is my understanding correct? If a VMID for an S2 hwpt is valid on physical IOMMU A but has already been allocated for another purpose on physical IOMMU B, how can it be shared across both IOMMUs? Or the VMID is allocated globally? Thanks, baolu