* [PATCH v3 2/3] leds: is31f132xx: re-order code to remove forward declarations
2025-11-21 11:35 [PATCH v3 0/3] leds: is31f132xx: add support for is31fl3293 Daniel Mack
2025-11-21 11:35 ` [PATCH v3 1/3] dt-bindings: leds: add issi,is31fl3293 to leds-is31fl32xx Daniel Mack
@ 2025-11-21 11:35 ` Daniel Mack
2025-11-21 11:35 ` [PATCH v3 3/3] leds: is31f132xx: add support for is31fl3293 Daniel Mack
2025-11-26 15:13 ` [PATCH v3 0/3] " Lee Jones
3 siblings, 0 replies; 6+ messages in thread
From: Daniel Mack @ 2025-11-21 11:35 UTC (permalink / raw)
To: linux-leds; +Cc: lee, Daniel Mack
From: Daniel Mack <daniel@zonque.org>
Move the chipdef structs after the functions they reference so that forward
declarations become unnecessary.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
v2 -> v3: re-ordered patches to get rid of the forward declarations
before introducing more of them,
drivers/leds/leds-is31fl32xx.c | 97 ++++++++++++++++------------------
1 file changed, 47 insertions(+), 50 deletions(-)
diff --git a/drivers/leds/leds-is31fl32xx.c b/drivers/leds/leds-is31fl32xx.c
index 8793330dd414..388d6a0b6932 100644
--- a/drivers/leds/leds-is31fl32xx.c
+++ b/drivers/leds/leds-is31fl32xx.c
@@ -84,56 +84,6 @@ struct is31fl32xx_chipdef {
int (*sw_shutdown_func)(struct is31fl32xx_priv *priv, bool enable);
};
-static const struct is31fl32xx_chipdef is31fl3236_cdef = {
- .channels = 36,
- .shutdown_reg = 0x00,
- .pwm_update_reg = 0x25,
- .global_control_reg = 0x4a,
- .reset_reg = 0x4f,
- .pwm_register_base = 0x01,
- .led_control_register_base = 0x26,
- .enable_bits_per_led_control_register = 1,
-};
-
-static const struct is31fl32xx_chipdef is31fl3235_cdef = {
- .channels = 28,
- .shutdown_reg = 0x00,
- .pwm_update_reg = 0x25,
- .global_control_reg = 0x4a,
- .reset_reg = 0x4f,
- .pwm_register_base = 0x05,
- .led_control_register_base = 0x2a,
- .enable_bits_per_led_control_register = 1,
-};
-
-static const struct is31fl32xx_chipdef is31fl3218_cdef = {
- .channels = 18,
- .shutdown_reg = 0x00,
- .pwm_update_reg = 0x16,
- .global_control_reg = IS31FL32XX_REG_NONE,
- .reset_reg = 0x17,
- .pwm_register_base = 0x01,
- .led_control_register_base = 0x13,
- .enable_bits_per_led_control_register = 6,
-};
-
-static int is31fl3216_reset(struct is31fl32xx_priv *priv);
-static int is31fl3216_software_shutdown(struct is31fl32xx_priv *priv,
- bool enable);
-static const struct is31fl32xx_chipdef is31fl3216_cdef = {
- .channels = 16,
- .shutdown_reg = IS31FL32XX_REG_NONE,
- .pwm_update_reg = 0xB0,
- .global_control_reg = IS31FL32XX_REG_NONE,
- .reset_reg = IS31FL32XX_REG_NONE,
- .pwm_register_base = 0x10,
- .pwm_registers_reversed = true,
- .led_control_register_base = 0x01,
- .enable_bits_per_led_control_register = 8,
- .reset_func = is31fl3216_reset,
- .sw_shutdown_func = is31fl3216_software_shutdown,
-};
-
static int is31fl32xx_write(struct is31fl32xx_priv *priv, u8 reg, u8 val)
{
int ret;
@@ -403,6 +353,53 @@ static int is31fl32xx_parse_dt(struct device *dev,
return 0;
}
+static const struct is31fl32xx_chipdef is31fl3236_cdef = {
+ .channels = 36,
+ .shutdown_reg = 0x00,
+ .pwm_update_reg = 0x25,
+ .global_control_reg = 0x4a,
+ .reset_reg = 0x4f,
+ .pwm_register_base = 0x01,
+ .led_control_register_base = 0x26,
+ .enable_bits_per_led_control_register = 1,
+};
+
+static const struct is31fl32xx_chipdef is31fl3235_cdef = {
+ .channels = 28,
+ .shutdown_reg = 0x00,
+ .pwm_update_reg = 0x25,
+ .global_control_reg = 0x4a,
+ .reset_reg = 0x4f,
+ .pwm_register_base = 0x05,
+ .led_control_register_base = 0x2a,
+ .enable_bits_per_led_control_register = 1,
+};
+
+static const struct is31fl32xx_chipdef is31fl3218_cdef = {
+ .channels = 18,
+ .shutdown_reg = 0x00,
+ .pwm_update_reg = 0x16,
+ .global_control_reg = IS31FL32XX_REG_NONE,
+ .reset_reg = 0x17,
+ .pwm_register_base = 0x01,
+ .led_control_register_base = 0x13,
+ .enable_bits_per_led_control_register = 6,
+};
+
+static const struct is31fl32xx_chipdef is31fl3216_cdef = {
+ .channels = 16,
+ .shutdown_reg = IS31FL32XX_REG_NONE,
+ .pwm_update_reg = 0xB0,
+ .global_control_reg = IS31FL32XX_REG_NONE,
+ .reset_reg = IS31FL32XX_REG_NONE,
+ .pwm_register_base = 0x10,
+ .pwm_registers_reversed = true,
+ .led_control_register_base = 0x01,
+ .enable_bits_per_led_control_register = 8,
+ .reset_func = is31fl3216_reset,
+ .sw_shutdown_func = is31fl3216_software_shutdown,
+};
+
static const struct of_device_id of_is31fl32xx_match[] = {
{ .compatible = "issi,is31fl3236", .data = &is31fl3236_cdef, },
{ .compatible = "issi,is31fl3235", .data = &is31fl3235_cdef, },
--
2.51.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v3 3/3] leds: is31f132xx: add support for is31fl3293
2025-11-21 11:35 [PATCH v3 0/3] leds: is31f132xx: add support for is31fl3293 Daniel Mack
2025-11-21 11:35 ` [PATCH v3 1/3] dt-bindings: leds: add issi,is31fl3293 to leds-is31fl32xx Daniel Mack
2025-11-21 11:35 ` [PATCH v3 2/3] leds: is31f132xx: re-order code to remove forward declarations Daniel Mack
@ 2025-11-21 11:35 ` Daniel Mack
2025-11-26 15:14 ` Lee Jones
2025-11-26 15:13 ` [PATCH v3 0/3] " Lee Jones
3 siblings, 1 reply; 6+ messages in thread
From: Daniel Mack @ 2025-11-21 11:35 UTC (permalink / raw)
To: linux-leds; +Cc: lee, Daniel Mack
From: Daniel Mack <daniel@zonque.org>
This chip supports 3 LED channels with 4096 possible PWM values.
Extend the driver to support this variant:
* Make brightness steps configurable per device type
* Handle dual-register brightness updates
* Allow to specify values to write into the PWM update register
* Add custom init and shutdown function for 3293 variant
* Init registers after parsing DT properties
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
v1 -> v2: address styling issues
drivers/leds/leds-is31fl32xx.c | 137 +++++++++++++++++++++++++++++++--
1 file changed, 129 insertions(+), 8 deletions(-)
diff --git a/drivers/leds/leds-is31fl32xx.c b/drivers/leds/leds-is31fl32xx.c
index 388d6a0b6932..05e28257ca4b 100644
--- a/drivers/leds/leds-is31fl32xx.c
+++ b/drivers/leds/leds-is31fl32xx.c
@@ -32,10 +32,25 @@
#define IS31FL3216_CONFIG_SSD_ENABLE BIT(7)
#define IS31FL3216_CONFIG_SSD_DISABLE 0
+/* Registers for IS31FL3293 */
+#define IS31FL3293_SHUTDOWN_REG 0x01
+#define IS31FL3293_SHUTDOWN_SSD_DISABLE BIT(0)
+#define IS31FL3293_SHUTDOWN_EN1 BIT(4)
+#define IS31FL3293_SHUTDOWN_EN2 BIT(5)
+#define IS31FL3293_SHUTDOWN_EN3 BIT(6)
+#define IS31FL3293_GCC_REG 0x03
+#define IS31FL3293_GCC_LEVEL_MAX 0x3f
+#define IS31FL3293_CL_REG 0x10
+#define IS31FL3293_COLOR_UPDATE_REG 0x27
+#define IS31FL3293_COLOR_UPDATE_MAGIC 0xc5
+#define IS31FL3293_RESET_REG 0x3c
+#define IS31FL3293_RESET_MAGIC 0xc5
+
struct is31fl32xx_priv;
struct is31fl32xx_led_data {
struct led_classdev cdev;
u8 channel; /* 1-based, max priv->cdef->channels */
+ u32 max_microamp;
struct is31fl32xx_priv *priv;
};
@@ -51,12 +66,14 @@ struct is31fl32xx_priv {
* @channels : Number of LED channels
* @shutdown_reg : address of Shutdown register (optional)
* @pwm_update_reg : address of PWM Update register
+ * @pwm_update_value : value to write to PWM Update register
* @global_control_reg : address of Global Control register (optional)
* @reset_reg : address of Reset register (optional)
* @pwm_register_base : address of first PWM register
* @pwm_registers_reversed: : true if PWM registers count down instead of up
* @led_control_register_base : address of first LED control register (optional)
* @enable_bits_per_led_control_register: number of LEDs enable bits in each
+ * @brightness_steps : number of brightness steps supported by the chip
* @reset_func : pointer to reset function
* @sw_shutdown_func : pointer to software shutdown function
*
@@ -74,12 +91,14 @@ struct is31fl32xx_chipdef {
u8 channels;
u8 shutdown_reg;
u8 pwm_update_reg;
+ u8 pwm_update_value;
u8 global_control_reg;
u8 reset_reg;
u8 pwm_register_base;
bool pwm_registers_reversed;
u8 led_control_register_base;
u8 enable_bits_per_led_control_register;
+ u16 brightness_steps;
int (*reset_func)(struct is31fl32xx_priv *priv);
int (*sw_shutdown_func)(struct is31fl32xx_priv *priv, bool enable);
};
@@ -148,6 +167,62 @@ static int is31fl3216_software_shutdown(struct is31fl32xx_priv *priv,
return is31fl32xx_write(priv, IS31FL3216_CONFIG_REG, value);
}
+/*
+ * Custom Reset function for IS31FL3293. We need to set the global current limit
+ * and write to the color update register once.
+ */
+static int is31fl3293_reset(struct is31fl32xx_priv *priv)
+{
+ int i, ret;
+
+ ret = is31fl32xx_write(priv, IS31FL3293_RESET_REG,
+ IS31FL3293_RESET_MAGIC);
+ if (ret)
+ return ret;
+
+ /* Set the global current limit to maximum */
+ ret = is31fl32xx_write(priv, IS31FL3293_GCC_REG,
+ IS31FL3293_GCC_LEVEL_MAX);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < priv->num_leds; i++) {
+ struct is31fl32xx_led_data *led_data = &priv->leds[i];
+ int current_level_reg = IS31FL3293_CL_REG + led_data->channel - 1;
+ int microamp = max(led_data->max_microamp, 20000);
+ int current_level = (microamp * 0xff) / 20000;
+
+ ret = is31fl32xx_write(priv, current_level_reg, current_level);
+ if (ret)
+ return ret;
+ }
+
+ ret = is31fl32xx_write(priv, IS31FL3293_COLOR_UPDATE_REG,
+ IS31FL3293_COLOR_UPDATE_MAGIC);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+/*
+ * Custom Software-Shutdown function for IS31FL3293 because the SHUTDOWN
+ * register of this device also has bits to enable the channels.
+ */
+static int is31fl3293_software_shutdown(struct is31fl32xx_priv *priv,
+ bool enable)
+{
+ u8 value = 0;
+
+ if (!enable)
+ value = IS31FL3293_SHUTDOWN_SSD_DISABLE |
+ IS31FL3293_SHUTDOWN_EN1 |
+ IS31FL3293_SHUTDOWN_EN2 |
+ IS31FL3293_SHUTDOWN_EN3;
+
+ return is31fl32xx_write(priv, IS31FL3293_SHUTDOWN_REG, value);
+}
+
/*
* NOTE: A mutex is not needed in this function because:
* - All referenced data is read-only after probe()
@@ -186,13 +261,36 @@ static int is31fl32xx_brightness_set(struct led_classdev *led_cdev,
else
pwm_register_offset = led_data->channel - 1;
- ret = is31fl32xx_write(led_data->priv,
- cdef->pwm_register_base + pwm_register_offset,
- brightness);
- if (ret)
- return ret;
+ switch (cdef->brightness_steps) {
+ case 256:
+ ret = is31fl32xx_write(led_data->priv,
+ cdef->pwm_register_base + pwm_register_offset,
+ brightness);
+ if (ret)
+ return ret;
+
+ break;
+ case 4096:
+ /* IS31FL329x devices use two registers to store 12 bits of brightness */
+ pwm_register_offset *= 2;
- return is31fl32xx_write(led_data->priv, cdef->pwm_update_reg, 0);
+ ret = is31fl32xx_write(led_data->priv,
+ cdef->pwm_register_base + pwm_register_offset,
+ brightness & 0xff);
+ if (ret)
+ return ret;
+
+ ret = is31fl32xx_write(led_data->priv,
+ cdef->pwm_register_base + pwm_register_offset + 1,
+ (brightness >> 8) & 0xf);
+ if (ret)
+ return ret;
+
+ break;
+ }
+
+ return is31fl32xx_write(led_data->priv, cdef->pwm_update_reg,
+ cdef->pwm_update_value);
}
static int is31fl32xx_reset_regs(struct is31fl32xx_priv *priv)
@@ -291,6 +389,8 @@ static int is31fl32xx_parse_child_dt(const struct device *dev,
}
led_data->channel = reg;
+ of_property_read_u32(child, "led-max-microamp", &led_data->max_microamp);
+
cdev->brightness_set_blocking = is31fl32xx_brightness_set;
return 0;
@@ -322,6 +422,7 @@ static int is31fl32xx_parse_dt(struct device *dev,
const struct is31fl32xx_led_data *other_led_data;
led_data->priv = priv;
+ led_data->cdev.max_brightness = priv->cdef->brightness_steps - 1;
ret = is31fl32xx_parse_child_dt(dev, child, led_data);
if (ret)
@@ -362,6 +463,7 @@ static const struct is31fl32xx_chipdef is31fl3236_cdef = {
.pwm_register_base = 0x01,
.led_control_register_base = 0x26,
.enable_bits_per_led_control_register = 1,
+ .brightness_steps = 256,
};
static const struct is31fl32xx_chipdef is31fl3235_cdef = {
@@ -373,6 +475,7 @@ static const struct is31fl32xx_chipdef is31fl3235_cdef = {
.pwm_register_base = 0x05,
.led_control_register_base = 0x2a,
.enable_bits_per_led_control_register = 1,
+ .brightness_steps = 256,
};
static const struct is31fl32xx_chipdef is31fl3218_cdef = {
@@ -384,6 +487,7 @@ static const struct is31fl32xx_chipdef is31fl3218_cdef = {
.pwm_register_base = 0x01,
.led_control_register_base = 0x13,
.enable_bits_per_led_control_register = 6,
+ .brightness_steps = 256,
};
static const struct is31fl32xx_chipdef is31fl3216_cdef = {
@@ -398,9 +502,25 @@ static const struct is31fl32xx_chipdef is31fl3216_cdef = {
.enable_bits_per_led_control_register = 8,
.reset_func = is31fl3216_reset,
.sw_shutdown_func = is31fl3216_software_shutdown,
+ .brightness_steps = 256,
+};
+
+static const struct is31fl32xx_chipdef is31fl3293_cdef = {
+ .channels = 3,
+ .shutdown_reg = IS31FL32XX_REG_NONE,
+ .pwm_update_reg = 0x28,
+ .pwm_update_value = 0xc5,
+ .global_control_reg = IS31FL32XX_REG_NONE,
+ .reset_reg = IS31FL32XX_REG_NONE,
+ .pwm_register_base = 0x19,
+ .led_control_register_base = IS31FL32XX_REG_NONE,
+ .brightness_steps = 4096,
+ .reset_func = is31fl3293_reset,
+ .sw_shutdown_func = is31fl3293_software_shutdown,
};
static const struct of_device_id of_is31fl32xx_match[] = {
+ { .compatible = "issi,is31fl3293", .data = &is31fl3293_cdef, },
{ .compatible = "issi,is31fl3236", .data = &is31fl3236_cdef, },
{ .compatible = "issi,is31fl3235", .data = &is31fl3235_cdef, },
{ .compatible = "issi,is31fl3218", .data = &is31fl3218_cdef, },
@@ -435,11 +555,11 @@ static int is31fl32xx_probe(struct i2c_client *client)
priv->cdef = cdef;
i2c_set_clientdata(client, priv);
- ret = is31fl32xx_init_regs(priv);
+ ret = is31fl32xx_parse_dt(dev, priv);
if (ret)
return ret;
- ret = is31fl32xx_parse_dt(dev, priv);
+ ret = is31fl32xx_init_regs(priv);
if (ret)
return ret;
@@ -462,6 +582,7 @@ static void is31fl32xx_remove(struct i2c_client *client)
* even though it is not used for DeviceTree based instantiation.
*/
static const struct i2c_device_id is31fl32xx_id[] = {
+ { "is31fl3293" },
{ "is31fl3236" },
{ "is31fl3235" },
{ "is31fl3218" },
--
2.51.1
^ permalink raw reply related [flat|nested] 6+ messages in thread