Re: [PATCH v3 13/34] m68k: Implement the new page table range API

Geert Uytterhoeven
2023-03-05T16:49:08Z

Hi Willy,

On Sun, Mar 5, 2023 at 4:28 PM Matthew Wilcox <willy@infradead.org> wrote:
> On Sun, Mar 05, 2023 at 11:16:13AM +0100, Geert Uytterhoeven wrote:
> > > + while (nr--) {
> > > + __asm__ __volatile__("nop\n\t"
> > > + ".chip 68040\n\t"
> > > + "cpushp %%bc,(%0)\n\t"
> > > + ".chip 68k"
> > > + : : "a" (paddr + nr * PAGE_SIZE));
> >
> > As gcc (9.5.0) keeps on calculating "paddr + nr * PAGE_SIZE"
> > inside the loop (albeit using a shift instead of a multiplication),
> > please use "paddr" here, followed by "paddr += PAGE_SIZE;".
>
> Thanks. So this?
>
> +++ b/arch/m68k/include/asm/cacheflush_mm.h
> @@ -235,13 +235,14 @@ static inline void __flush_pages_to_ram(void *vaddr, unsigned int nr)
> } else if (CPU_IS_040_OR_060) {
> unsigned long paddr = __pa(vaddr);
>
> - while (nr--) {
> + do {
> __asm__ __volatile__("nop\n\t"
> ".chip 68040\n\t"
> "cpushp %%bc,(%0)\n\t"
> ".chip 68k"
> - : : "a" (paddr + nr * PAGE_SIZE));
> - }
> + : : "a" (paddr));
> + paddr += PAGE_SIZE;
> + } while (--nr);
> } else {
> unsigned long _tmp;
> __asm__ __volatile__("movec %%cacr,%0\n\t"

LGTM. Might be safer to keep the "while (nr--) {", just in case someone
ever passes zero.

> Also, I noticed that I broke sun3. It puts the PFN in bits 0-n instead
> of 12-n. New patch coming soon.

Thanks, hadn't noticed (there are no sun3-specific code changes in
this series?)

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds