Re: [PATCH v3 13/34] m68k: Implement the new page table range API

Matthew Wilcox
2023-03-05T15:28:55Z

On Sun, Mar 05, 2023 at 11:16:13AM +0100, Geert Uytterhoeven wrote:
> > + while (nr--) {
> > + __asm__ __volatile__("nop\n\t"
> > + ".chip 68040\n\t"
> > + "cpushp %%bc,(%0)\n\t"
> > + ".chip 68k"
> > + : : "a" (paddr + nr * PAGE_SIZE));
>
> As gcc (9.5.0) keeps on calculating "paddr + nr * PAGE_SIZE"
> inside the loop (albeit using a shift instead of a multiplication),
> please use "paddr" here, followed by "paddr += PAGE_SIZE;".

Thanks. So this?

+++ b/arch/m68k/include/asm/cacheflush_mm.h
@@ -235,13 +235,14 @@ static inline void __flush_pages_to_ram(void *vaddr, unsigned int nr)
} else if (CPU_IS_040_OR_060) {
unsigned long paddr = __pa(vaddr);

- while (nr--) {
+ do {
__asm__ __volatile__("nop\n\t"
".chip 68040\n\t"
"cpushp %%bc,(%0)\n\t"
".chip 68k"
- : : "a" (paddr + nr * PAGE_SIZE));
- }
+ : : "a" (paddr));
+ paddr += PAGE_SIZE;
+ } while (--nr);
} else {
unsigned long _tmp;
__asm__ __volatile__("movec %%cacr,%0\n\t"

Also, I noticed that I broke sun3. It puts the PFN in bits 0-n instead
of 12-n. New patch coming soon.