Re: [PATCH RFC 1/2] m68k: io_mm.h: conditionalize ISA address translation on Atari

Brad Boyer
2021-06-06T23:51:11Z

On Sun, Jun 06, 2021 at 05:42:30PM +1200, Michael Schmitz wrote:
> >Would (port & ~1) be faster than (port - 1) here?
>
> Perhaps it would - I'd hope the compiler will pick the most efficient
> solution here.

I'm pretty sure the compiler couldn't do that optimization. Without
more context, those two statements are not equivalent. I don't see
how the compiler could know that.

Looking at the 68040 manual, the instruction timing of ANDI and SUBQ
is mostly the same (except for immediate addressing, where ANDI is
slower). The ANDI is also going to take up extra bytes in the code
to put the bitmask in an extension word. BCLR can be faster than
ANDI or SUBQ in some cases, but it's slower in others. It also needs
an extension word when using an immediate value for the bit number.
If you presume port is in a data register, then ANDI and SUBQ have
the same timing and BCLR is slower. At that point, the difference
between ANDI and SUBQ is the size of the instruction which would
favor using SUBQ. I haven't checked if other m68k chips have similar
timings.

Unless I missed something, I don't see a better way to do the
equivalent of the and with a constant bitmask.

Brad Boyer
flar@allandria.com