Re: [PATCH 4/4 V2] Set ACR1 cache mode depending on kernel configuration.

Philippe De Muyter
2012-10-16T08:12:08Z

Hi Stany and Greg,

On Tue, Oct 16, 2012 at 03:27:26PM +1000, Greg Ungerer wrote:
> Hi Stany,
>
> On 15/10/12 23:22, Stany MARCEL wrote:
>> For coldfire with MMU enabled, data cache did not follow the configuration
>> but
>> was configured in writethrough mode.
>>
>> Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
>
> Looks good, thanks. Applied without the white space changes.

Wouldn't it be better to move the test on CONFIG_CACHE_COPYBACK outside
of the test on CONFIG_MMU instead of duplicating it ?

Philippe

>
> Regards
> Greg
>
>
>> ---
>>
>> Changes:
>> V2: This patch is now independant from the previous one
>>
>> arch/m68k/include/asm/m54xxacr.h | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/m68k/include/asm/m54xxacr.h
>> b/arch/m68k/include/asm/m54xxacr.h
>> index 192bbfe..8f932be 100644
>> --- a/arch/m68k/include/asm/m54xxacr.h
>> +++ b/arch/m68k/include/asm/m54xxacr.h
>> @@ -94,14 +94,18 @@
>> * register region as non-cacheable. And then we map all our RAM as
>> * cacheable and supervisor access only.
>> */
>> -#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
>> +#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
>> ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
>> +#if defined(CONFIG_CACHE_COPYBACK)
>> #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
>> - ACR_ENABLE+ACR_SUPER+ACR_SP)
>> + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
>> +#else
>> +#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
>> + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
>> +#endif
>> #define ACR2_MODE 0
>> #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
>> ACR_ENABLE+ACR_SUPER+ACR_SP)
>> -
>> #else
>>
>> /*
>> --
>> 1.7.9.5