From: Philippe De Muyter <phdm@macqel.be>
To: Greg Ungerer <gerg@snapgear.com>
Cc: Stany MARCEL <stany.marcel@novasys-ingenierie.com>,
linux-m68k@vger.kernel.org, gerg@uclinux.org
Subject: Re: [PATCH 4/4 V2] Set ACR1 cache mode depending on kernel configuration.
Date: Tue, 16 Oct 2012 10:12:02 +0200 [thread overview]
Message-ID: <20121016081202.GB8427@frolo.macqel> (raw)
In-Reply-To: <507CF03E.1000609@snapgear.com>
Hi Stany and Greg,
On Tue, Oct 16, 2012 at 03:27:26PM +1000, Greg Ungerer wrote:
> Hi Stany,
>
> On 15/10/12 23:22, Stany MARCEL wrote:
>> For coldfire with MMU enabled, data cache did not follow the configuration
>> but
>> was configured in writethrough mode.
>>
>> Signed-off-by: Stany MARCEL <stany.marcel@novasys-ingenierie.com>
>
> Looks good, thanks. Applied without the white space changes.
Wouldn't it be better to move the test on CONFIG_CACHE_COPYBACK outside
of the test on CONFIG_MMU instead of duplicating it ?
Philippe
>
> Regards
> Greg
>
>
>> ---
>>
>> Changes:
>> V2: This patch is now independant from the previous one
>>
>> arch/m68k/include/asm/m54xxacr.h | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/m68k/include/asm/m54xxacr.h
>> b/arch/m68k/include/asm/m54xxacr.h
>> index 192bbfe..8f932be 100644
>> --- a/arch/m68k/include/asm/m54xxacr.h
>> +++ b/arch/m68k/include/asm/m54xxacr.h
>> @@ -94,14 +94,18 @@
>> * register region as non-cacheable. And then we map all our RAM as
>> * cacheable and supervisor access only.
>> */
>> -#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
>> +#define ACR0_MODE (ACR_BA(CONFIG_MBAR)+ACR_ADMSK(0x1000000)+ \
>> ACR_ENABLE+ACR_SUPER+ACR_CM_OFF_PRE+ACR_SP)
>> +#if defined(CONFIG_CACHE_COPYBACK)
>> #define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
>> - ACR_ENABLE+ACR_SUPER+ACR_SP)
>> + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_CP)
>> +#else
>> +#define ACR1_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
>> + ACR_ENABLE+ACR_SUPER+ACR_SP+ACR_CM_WT)
>> +#endif
>> #define ACR2_MODE 0
>> #define ACR3_MODE (ACR_BA(CONFIG_RAMBASE)+ACR_ADMSK(CONFIG_RAMSIZE)+ \
>> ACR_ENABLE+ACR_SUPER+ACR_SP)
>> -
>> #else
>>
>> /*
>> --
>> 1.7.9.5
next prev parent reply other threads:[~2012-10-16 8:12 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-15 12:54 [PATCH 1/4] Add linux/io.h to make it compile Stany MARCEL
2012-10-15 12:54 ` [PATCH 2/4] Permit to read/write to shared page Stany MARCEL
2012-10-15 12:54 ` [PATCH 3/4] Add for MCF54xx a virtual non cached zone usable for data exchange with DMA Stany MARCEL
2012-10-15 13:22 ` [PATCH 3/4 V2] " Stany MARCEL
2012-10-16 5:15 ` Greg Ungerer
2012-10-16 10:46 ` Stany MARCEL
2012-10-16 11:23 ` Philippe De Muyter
2012-10-16 12:29 ` Greg Ungerer
2012-10-16 13:57 ` RE : " Stany MARCEL
2012-10-15 12:54 ` [PATCH 4/4] Set ACR1 cache mode depending on kernel configuration Stany MARCEL
2012-10-15 13:22 ` [PATCH 4/4 V2] " Stany MARCEL
2012-10-16 5:27 ` Greg Ungerer
2012-10-16 8:12 ` Philippe De Muyter [this message]
2012-10-16 12:06 ` Greg Ungerer
2012-10-15 13:58 ` [PATCH 1/4] Add linux/io.h to make it compile Philippe De Muyter
2012-10-15 14:06 ` Stany MARCEL
2012-10-15 14:39 ` Philippe De Muyter
2012-10-16 4:58 ` Greg Ungerer
2012-10-15 14:08 ` [PATCH 1/4 V2] Add linux/io.h to make m54xx_wdt.c compile with MMU enabled Stany MARCEL
2012-10-16 5:04 ` Greg Ungerer
2012-10-16 10:47 ` Stany MARCEL
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