From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77693C433EF for ; Tue, 7 Jun 2022 11:11:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241501AbiFGLLV (ORCPT ); Tue, 7 Jun 2022 07:11:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242889AbiFGLKS (ORCPT ); Tue, 7 Jun 2022 07:10:18 -0400 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1508322280 for ; Tue, 7 Jun 2022 04:08:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654600094; x=1686136094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LehJpdli2K1kf6xsEwsX5oR/25DuYLSpUF31DPXQGNU=; b=cBq83o5sp+nXdBUi91R4HBkFlcaRw1duozt5ogV+A1xEnBJofphng279 L/Hie2RY4naoacDv6sFVs94G5w9jxojfVkauuHj6otM/4L7JJayjwLMn1 Ww9wyQpBuYjp4x/swzyGDO9HnuBEgMFbgSdSI68cQjVPrkahDNFgOoneK undzJKkOjCxKw2aXIZnOcGENuFzC/Xwwj1o2QTt3lnVO0DphWyaCcNuXe T/jlMwebOxtlpracO89n2vjcWWXC1mfpfVF3v1ZHnYYYkrFs+Di3rqOum 6rnL8Tcy6qLN3DFdntl8Rwhfw5AJXMS6XI8agte1WhFgWMS+2DLxXzEgI w==; X-IronPort-AV: E=McAfee;i="6400,9594,10370"; a="259461990" X-IronPort-AV: E=Sophos;i="5.91,283,1647327600"; d="scan'208";a="259461990" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2022 04:08:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,283,1647327600"; d="scan'208";a="584155731" Received: from irvmail001.ir.intel.com ([10.43.11.63]) by fmsmga007.fm.intel.com with ESMTP; 07 Jun 2022 04:08:08 -0700 Received: from newjersey.igk.intel.com (newjersey.igk.intel.com [10.102.20.203]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 257B86Ft021369; Tue, 7 Jun 2022 12:08:06 +0100 From: Alexander Lobakin To: Mark Rutland Cc: Alexander Lobakin , Arnd Bergmann , Yury Norov , Andy Shevchenko , Richard Henderson , Matt Turner , Brian Cain , "Geert Uytterhoeven" , Yoshinori Sato , Rich Felker , "David S. Miller" , Kees Cook , "Peter Zijlstra (Intel)" , Marco Elver , Borislav Petkov , Tony Luck , "Greg Kroah-Hartman" , linux-alpha@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 5/6] bitops: wrap non-atomic bitops with a transparent macro Date: Tue, 7 Jun 2022 13:07:05 +0200 Message-Id: <20220607110705.72887-1-alexandr.lobakin@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220607105718.72434-1-alexandr.lobakin@intel.com> References: <20220606114908.962562-1-alexandr.lobakin@intel.com> <20220606114908.962562-6-alexandr.lobakin@intel.com> <20220607105718.72434-1-alexandr.lobakin@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-m68k@vger.kernel.org From: Alexander Lobakin Date: Tue, 7 Jun 2022 12:57:18 +0200 > From: Mark Rutland > Date: Mon, 6 Jun 2022 17:27:16 +0100 > > > On Mon, Jun 06, 2022 at 01:49:06PM +0200, Alexander Lobakin wrote: > > > In preparation for altering the non-atomic bitops with a macro, wrap > > > them in a transparent definition. This requires prepending one more > > > '_' to their names in order to be able to do that seamlessly. > > > sparc32 already has the triple-underscored functions, so I had to > > > rename them ('___' -> 'sp32_'). > > > > Could we use an 'arch_' prefix here, like we do for the atomics, or is that > > already overloaded? > > Yeah it is, for example, x86 has 'arch_' functions defined in its > architecture headers[0] and at the same time uses generic > instrumented '__' helpers[1], so on x86 both underscored and 'arch_' > are defined and they are not the same. Oh well, forgot to attach the links. Can be found at the bottom of this mail. > Same with those sparc32 triple-underscored, sparc32 at the same time > uses generic non-instrumented, so it has underscored, 'arch_' and > triple-underscored. > > In general, bitops are overloaded with tons of prefixes already :) > I'm not really glad that I introduced one more level, but not that > we have many options here. > > > > > Thanks, > > Mark. > > > > > > > > Signed-off-by: Alexander Lobakin > > > --- > > [...] > > > > -- > > > 2.36.1 > > Thanks, > Olek [0] https://elixir.bootlin.com/linux/v5.19-rc1/source/arch/x86/include/asm/bitops.h#L136 [1] https://elixir.bootlin.com/linux/v5.19-rc1/source/include/asm-generic/bitops/instrumented-non-atomic.h#L93 Thanks, Olek