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[35.229.176.202]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08cacbb0sm31999240a91.13.2026.09.08.02.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Sep 2026 02:40:41 -0700 (PDT) From: Kuan-Wei Chiu To: geert@linux-m68k.org, tglx@kernel.org, miodrag.dinic@mips.com Cc: radu@rendec.net, zewenchen@google.com, jamiechen@google.com, edwardwchen@google.com, marscheng@google.com, eleanor15x@gmail.com, jserv@ccns.ncku.edu.tw, linux-kernel@vger.kernel.org, linux-m68k@lists.linux-m68k.org, Kuan-Wei Chiu Subject: [PATCH 1/6] irqchip/goldfish-pic: Use gf_ioread32/gf_iowrite32 for MMIO access Date: Tue, 8 Sep 2026 09:40:11 +0000 Message-ID: <20260908094016.1997918-2-visitorckw@gmail.com> X-Mailer: git-send-email 2.55.0.979.g7e5102b832-goog In-Reply-To: <20260908094016.1997918-1-visitorckw@gmail.com> References: <20260908094016.1997918-1-visitorckw@gmail.com> Precedence: bulk X-Mailing-List: linux-m68k@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The goldfish PIC driver uses readl() and writel() directly for register accesses. On big endian architectures, goldfish devices require big endian MMIO accessors [1]. Switch to gf_ioread32() and gf_iowrite32() to make MMIO accesses endian safe. Link: https://gitlab.com/qemu-project/qemu/-/blob/stable-11.1/hw/intc/goldfish_pic.c#L130 [1] Signed-off-by: Kuan-Wei Chiu --- drivers/irqchip/irq-goldfish-pic.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldfish-pic.c index d458cf898f8e..c3c33f066140 100644 --- a/drivers/irqchip/irq-goldfish-pic.c +++ b/drivers/irqchip/irq-goldfish-pic.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -38,7 +39,7 @@ static void goldfish_pic_cascade(struct irq_desc *desc) chained_irq_enter(host_chip, desc); - pending = readl(gfpic->base + GFPIC_REG_IRQ_PENDING); + pending = gf_ioread32(gfpic->base + GFPIC_REG_IRQ_PENDING); while (pending) { hwirq = __fls(pending); generic_handle_domain_irq(gfpic->irq_domain, hwirq); @@ -52,6 +53,16 @@ static const struct irq_domain_ops goldfish_irq_domain_ops = { .xlate = irq_domain_xlate_onecell, }; +static u32 gfpic_read(void __iomem *addr) +{ + return gf_ioread32(addr); +} + +static void gfpic_write(u32 val, void __iomem *addr) +{ + gf_iowrite32(val, addr); +} + static int __init goldfish_pic_of_init(struct device_node *of_node, struct device_node *parent) { @@ -82,7 +93,7 @@ static int __init goldfish_pic_of_init(struct device_node *of_node, } /* Mask interrupts. */ - writel(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL); + gf_iowrite32(1, gfpic->base + GFPIC_REG_IRQ_DISABLE_ALL); gc = irq_alloc_generic_chip("GFPIC", 1, GFPIC_IRQ_BASE, gfpic->base, handle_level_irq); @@ -92,6 +103,9 @@ static int __init goldfish_pic_of_init(struct device_node *of_node, goto out_iounmap; } + gc->reg_readl = gfpic_read; + gc->reg_writel = gfpic_write; + ct = gc->chip_types; ct->regs.enable = GFPIC_REG_IRQ_ENABLE; ct->regs.disable = GFPIC_REG_IRQ_DISABLE; -- 2.55.0.979.g7e5102b832-goog