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([2001:df0:0:200c:adb8:c71:a09c:347f]) by smtp.gmail.com with ESMTPSA id nk4-20020a17090b194400b0029b28e6ef26sm293735pjb.11.2024.03.06.15.42.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 Mar 2024 15:42:06 -0800 (PST) Message-ID: <2f4e8b3b-9980-43d1-a2d2-d62a9c9a7d6b@gmail.com> Date: Thu, 7 Mar 2024 12:42:01 +1300 Precedence: bulk X-Mailing-List: linux-m68k@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: spinlock recursion when running q800 emulation in qemu Content-Language: en-US To: Brad Boyer Cc: Guenter Roeck , Geert Uytterhoeven , linux-m68k@lists.linux-m68k.org References: <07811b26-677c-4d05-aeb4-996cd880b789@roeck-us.net> <0ccf5e42-63ec-a63d-9ee9-7043947637c3@gmail.com> <20240306083054.GA20607@allandria.com> From: Michael Schmitz In-Reply-To: <20240306083054.GA20607@allandria.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Thanks Brad, On 6/03/24 21:30, Brad Boyer wrote: > On Wed, Mar 06, 2024 at 08:14:31PM +1300, Michael Schmitz wrote: >> Looking at the backtraces some more, I think what happens here is that the >> swapper kernel task is stalled for long enough here that on the next >> scheduler tick, it is still running. With no other tasks scheduled to run in >> the meantime, it may still be the current task. >> >> The stalled swapper task still holds the run queue lock, hence the recursion >> message. >> >> I do not think this is a bug, just a reflection of a slow system with >> nothing much to do. >> >> There does not appear to be any interrupt nesting here. I cannot recall the >> interrupt level assignment on the Q800, in particular as regards disk >> interrupts and whether both VIAs are using the same interrupt level. I'd >> suppose they would, as these chips date back a long time and probably cannot ... that should have been 'would not', of course. Autovectoring can't work otherwise. >> place a vector number on the bus as part of the interrupt stack frame? > No, a Mac with 2 VIA chips should always have them on separate interrupt > levels. The exact mapping varies by model, but every model supported > by Linux uses at least three different hardware IRQ levels. > > On most Mac models, VIA1 is IRQ1, VIA2 is IRQ2, and the SCC is IRQ4. > VIA1 would handle the timer and ADB while VIA2 handles NuBus and SCSI. > It looks like the Q800 supports switching VIA1 to IRQ6 through the > alternate IRQ mapping. Most models also are using various other chips > emulating a real VIA for VIA2 with varying levels of compatibility. > > Apple always used autovectoring and the three IPL pins to determine > the interrupt vector. Older models just have three external IRQ > sources, one matching each pin (thus the 1, 2, 4 pattern). I presume > they had some external circuit to make sure only one line is being > pulled low at a time since we never get other IRQ levels by accident. Makes sense - thanks for refreshing my memory! Cheers,     Michael > > The AV macs and the IIfx are the only models with more complex > interrupt controllers as separate chips (PSC or OSS). > > Brad Boyer > flar@allandria.com > >