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([2001:df0:0:200c:fc82:cbbc:8740:8921]) by smtp.gmail.com with ESMTPSA id u16-20020a62ed10000000b00682669dc19bsm4675216pfh.201.2023.08.20.12.19.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 20 Aug 2023 12:19:24 -0700 (PDT) Message-ID: <3afffc69-62a3-2a11-0c22-8301300e0d50@gmail.com> Date: Mon, 21 Aug 2023 07:19:16 +1200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 1/3] m68k/q40: fix IO base selection for Q40 in pata_falcon.c Content-Language: en-US To: Sergey Shtylyov , linux-ide@vger.kernel.org, linux-m68k@vger.kernel.org Cc: will@sowerbutts.com, rz@linux-m68k.org, geert@linux-m68k.org, stable@vger.kernel.org, Finn Thain References: <20230817221232.22035-1-schmitzmic@gmail.com> <20230817221232.22035-2-schmitzmic@gmail.com> <82f37617-949b-bcfa-8531-c0a9790aaf48@omp.ru> From: Michael Schmitz In-Reply-To: <82f37617-949b-bcfa-8531-c0a9790aaf48@omp.ru> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-m68k@vger.kernel.org Hi Sergey, thanks for your review! On 20/08/23 08:29, Sergey Shtylyov wrote: > Hello! > > On 8/18/23 1:12 AM, Michael Schmitz wrote: > >> With commit 44b1fbc0f5f3 ("m68k/q40: Replace q40ide driver >> with pata_falcon and falconide"), the Q40 IDE driver was >> replaced by pata_falcon.c. >> >> Both IO and memory resources were defined for the Q40 IDE >> platform device, but definition of the IDE register addresses >> was modeled after the Falcon case, both in use of the memory >> resources and in including register scale and byte vs. word >> offset in the address. >> >> This was correct for the Falcon case, which does not apply >> any address translation to the register addresses. In the >> Q40 case, all of device base address, byte access offset >> and register scaling is included in the platform specific >> ISA access translation (in asm/mm_io.h). >> >> As a consequence, such address translation gets applied >> twice, and register addresses are mangled. >> >> Use the device base address from the platform IO resource, >> and use standard register offsets from that base in order >> to calculate register addresses (the IO address translation >> will then apply the correct ISA window base and scaling). >> >> Encode PIO_OFFSET into IO port addresses for all registers >> except the data transfer register. Encode the MMIO offset >> there (pata_falcon_data_xfer() directly uses raw IO with >> no address translation). >> >> Reported-by: William R Sowerbutts >> Closes: https://lore.kernel.org/r/CAMuHMdUU62jjunJh9cqSqHT87B0H0A4udOOPs=WN7WZKpcagVA@mail.gmail.com >> Link: https://lore.kernel.org/r/CAMuHMdUU62jjunJh9cqSqHT87B0H0A4udOOPs=WN7WZKpcagVA@mail.gmail.com >> Fixes: 44b1fbc0f5f3 ("m68k/q40: Replace q40ide driver with pata_falcon and falconide") >> Cc: # 5.14 >> Cc: Finn Thain >> Cc: Geert Uytterhoeven >> Signed-off-by: Michael Schmitz > Reviewed-by: Sergey Shtylyov > > [...] >> diff --git a/drivers/ata/pata_falcon.c b/drivers/ata/pata_falcon.c >> index 996516e64f13..346259e3bbc8 100644 >> --- a/drivers/ata/pata_falcon.c >> +++ b/drivers/ata/pata_falcon.c >> @@ -123,8 +123,8 @@ static int __init pata_falcon_init_one(struct platform_device *pdev) >> struct resource *base_res, *ctl_res, *irq_res; >> struct ata_host *host; >> struct ata_port *ap; >> - void __iomem *base; >> - int irq = 0; >> + void __iomem *base, *ctl_base; >> + int irq = 0, io_offset = 1, reg_scale = 4; > Maybe reg_step? Could name it that, too. I can't recall where I picked up the term 'register scaling'... I'll see what's the consensus (if any) in drivers/. Cheers,     Michael > > [...] > > MBR, Sergey