From mboxrd@z Thu Jan 1 00:00:00 1970 From: Hannes Reinecke Subject: Re: [PATCH v3 75/77] ncr5380: Enable PDMA for DTC chips Date: Tue, 22 Dec 2015 09:08:25 +0100 Message-ID: <567904F9.8060102@suse.de> References: <20151222011737.980475848@telegraphics.com.au> <20151222011758.425517219@telegraphics.com.au> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <20151222011758.425517219@telegraphics.com.au> Sender: linux-scsi-owner@vger.kernel.org To: Finn Thain , "James E.J. Bottomley" , Michael Schmitz , linux-m68k@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, "Martin K. Petersen" Cc: Ondrej Zary List-Id: linux-m68k@vger.kernel.org On 12/22/2015 02:18 AM, Finn Thain wrote: > From: Ondrej Zary > > Add I/O register mapping for DTC chips and enable PDMA mode. > > These chips have 16-bit wide HOST BUFFER register and it must be read > by 16-bit accesses (we lose data otherwise). > > Large PIO transfers crash at least the DTCT-436P chip (all reads resu= lt > in 0xFF) so this patch actually makes it work. > > The chip also crashes when we bang on the C400 host status register t= oo > heavily after PDMA write - a small udelay is needed. > > Tested on DTCT-436P and verified that it does not break 53C400A. > > Signed-off-by: Ondrej Zary > Signed-off-by: Finn Thain > Reviewed-by: Hannes Reinecke Cheers, Hannes --=20 Dr. Hannes Reinecke zSeries & Storage hare@suse.de +49 911 74053 688 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg GF: J. Hawn, J. Guild, F. Imend=F6rffer, HRB 16746 (AG N=FCrnberg) -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" i= n the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html