From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD90BC43334 for ; Mon, 13 Jun 2022 19:01:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346492AbiFMTBj (ORCPT ); Mon, 13 Jun 2022 15:01:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346511AbiFMTAy (ORCPT ); Mon, 13 Jun 2022 15:00:54 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E2A299825 for ; Mon, 13 Jun 2022 09:26:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655137611; x=1686673611; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=XxsfHurYfgtl5B8eDXs3NdPaSjArXVczaB+F2Bn9Ek4=; b=V6jNjpMvY8yvAI9agUvHxBNeO8cMWm1GWNMZ1n9OJdPeXbiac98qLsZE s7S7CsCOVgX3pow6HLg64Bkz/+vHWi5pXY7VDag9IUiRjcI/7KhdxWm4M k6rNrOZlTUxeF6H6CMx5Cj+u826yDwcw8PUSDX8VjklCmmRjEFTXaBHNC 6btbE7J+aVyu93AV2XL3m+PPGVaUOKNebB4M8Oh3Wa5d+WDCCnU5Qvc6o YhJj9fz3hyCSVqbx3mDqHzn5kYy3oFUYjvGRQghAYj97YxeZ7LZ0dJ+lh wwb0jydoNG1mPXI82AeqK71iCBscA33+ZXbwJsI8YLPkpDTGZ3/IMC0TT A==; X-IronPort-AV: E=McAfee;i="6400,9594,10377"; a="279382471" X-IronPort-AV: E=Sophos;i="5.91,297,1647327600"; d="scan'208";a="279382471" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2022 09:26:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,297,1647327600"; d="scan'208";a="611858233" Received: from fmsmsx601.amr.corp.intel.com ([10.18.126.81]) by orsmga008.jf.intel.com with ESMTP; 13 Jun 2022 09:26:50 -0700 Received: from fmsmsx612.amr.corp.intel.com (10.18.126.92) by fmsmsx601.amr.corp.intel.com (10.18.126.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Mon, 13 Jun 2022 09:26:49 -0700 Received: from fmsmsx610.amr.corp.intel.com (10.18.126.90) by fmsmsx612.amr.corp.intel.com (10.18.126.92) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.27; Mon, 13 Jun 2022 09:26:49 -0700 Received: from fmsmsx610.amr.corp.intel.com ([10.18.126.90]) by fmsmsx610.amr.corp.intel.com ([10.18.126.90]) with mapi id 15.01.2308.027; Mon, 13 Jun 2022 09:26:49 -0700 From: "Luck, Tony" To: "Lobakin, Alexandr" , Marco Elver CC: Andy Shevchenko , Arnd Bergmann , Yury Norov , Mark Rutland , Matt Turner , Brian Cain , Geert Uytterhoeven , "Yoshinori Sato" , Rich Felker , "David S. Miller" , Kees Cook , "Peter Zijlstra (Intel)" , Borislav Petkov , "Greg Kroah-Hartman" , "linux-alpha@vger.kernel.org" , "linux-hexagon@vger.kernel.org" , "linux-ia64@vger.kernel.org" , "linux-m68k@lists.linux-m68k.org" , "linux-sh@vger.kernel.org" , "sparclinux@vger.kernel.org" , "linux-arch@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v2 2/6] bitops: always define asm-generic non-atomic bitops Thread-Topic: [PATCH v2 2/6] bitops: always define asm-generic non-atomic bitops Thread-Index: AQHYfL4xWJEoq3eTcEeKREBjFjjrHK1JHg2A//+t5kCAAH9LAIAEkeOA//+tDzA= Date: Mon, 13 Jun 2022 16:26:49 +0000 Message-ID: References: <20220610113427.908751-1-alexandr.lobakin@intel.com> <20220610113427.908751-3-alexandr.lobakin@intel.com> <22042c14bc6a437d9c6b235fbfa32c8a@intel.com> <20220613141947.1176100-1-alexandr.lobakin@intel.com> In-Reply-To: <20220613141947.1176100-1-alexandr.lobakin@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.6.500.17 x-originating-ip: [10.1.200.100] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-m68k@vger.kernel.org >> It's listed in Documentation/atomic_bitops.txt. > > Oh, so my memory was actually correct that I saw it in the docs > somewhere. > WDYT, should I mention this here in the code (block comment) as well > that it's atomic and must not lose `volatile` as Andy suggested or > it's sufficient to have it in the docs (+ it's not underscored)? I think a comment that the "volatile" is required to prevent re-ordering is enough. But maybe others are sufficiently clear on the meaning? I once wasted time looking for the non-atomic __test_bit() version (to use in some code that was already protected by a spin lock, so didn't need the overhead of an "atomic" version) before realizing there wasn't a non-atomic one. -Tony