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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b55d8c124a8sm2371766b.51.2025.10.09.08.49.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 09 Oct 2025 08:49:47 -0700 (PDT) Message-ID: <0a0afe32-7814-4901-bfbb-6694cd846257@oss.qualcomm.com> Date: Thu, 9 Oct 2025 17:49:45 +0200 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 8/8] media: iris: enable support for SC7280 platform To: Dmitry Baryshkov Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251008-iris-sc7280-v1-0-def050ba5e1f@oss.qualcomm.com> <20251008-iris-sc7280-v1-8-def050ba5e1f@oss.qualcomm.com> <3f1979d4-1438-4c9d-99db-d97a09c5c35b@oss.qualcomm.com> <1118c126-4332-4f9b-afb8-d3da4fa7fa87@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDA4MDEyMSBTYWx0ZWRfX0WnPwu2FVeFc qIgBLk++W5i+9Cwqutdunrj7dC6lYTKuLX1kzNf8kXMos8lJ2ew3mLCXDkhOMLfnwuSwghCUOZu 4A8k043MkuTRAb0AlTbbk1grO0oxCYbBBFE/GDsy+12bWNp9EhKhEl+Lq+98nBdqvHowt5P2miD JO+gv07xRm+lRLy6xAWEPrc1TeoK5MtLl77c85r/I6CWEEaIgJDdLUPAKgvIBRVZOl3LSGSERib 3r+GJStCSwS+zR7dvPizo9xoaC8NeroTPJg3TERgHuuQhFaaY5enVg66+abJsktsb/PJbq6A76E EpLWC0hheCQQd61sEkiuJGgtl7Yhy9HwUg/eOFT8YuQt76fDgR9v5MTzgrCWOJY5KvoDxQ5Qxdx 3wUIyl45tuG+k+tulLuKujXnCiyOIQ== X-Proofpoint-GUID: Uhq2Y0USuMzrTtCr1OjWE6PKIEVGJazy X-Proofpoint-ORIG-GUID: Uhq2Y0USuMzrTtCr1OjWE6PKIEVGJazy X-Authority-Analysis: v=2.4 cv=SJxPlevH c=1 sm=1 tr=0 ts=68e7d99d cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=LpQP-O61AAAA:8 a=lTMcXo_5zusfKqBCz9IA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 a=pioyyrs4ZptJ924tMmac:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-09_05,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510080121 On 10/9/25 5:00 PM, Dmitry Baryshkov wrote: > On Thu, Oct 09, 2025 at 11:19:31AM +0200, Konrad Dybcio wrote: >> On 10/8/25 9:25 PM, Dmitry Baryshkov wrote: >>> On Wed, Oct 08, 2025 at 10:26:02AM +0200, Konrad Dybcio wrote: >>>> On 10/8/25 6:33 AM, Dmitry Baryshkov wrote: >>>>> As a part of migrating code from the old Venus driver to the new Iris >>>>> one, add support for the SC7280 platform. It is very similar to SM8250, >>>>> but it (currently) uses no reset controls (there is an optional >>>>> GCC-generated reset, it will be added later) and no AON registers >>>>> region. The Venus driver names this platform "IRIS2_1", so the ops in >>>> >>>> Which we've learnt in the past is "IRIS2, 1-pipe" >>> >>> Well, I'm open for better suggestions. iris_vpu2_no_aon_ops? >> >> [...] >> >>>>> + writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, >>>>> + core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); >>>>> + writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); >>>>> + writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); >>>>> + writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); >>>>> + >>>>> +disable_power: >>>>> + iris_disable_unprepare_clock(core, IRIS_AHB_CLK); >>>> >>>> ..for this line >>> >>> Not only. You missed the absense of AON_WRAPPER_MVP_NOC_LPI_CONTROL / >>> AON_WRAPPER_MVP_NOC_LPI_STATUS. Which in theory can become a flag in >>> iris_platform_data. >>> >>>> >>>> but this could be added to that one instead, since both clk APIs and the >>>> Iris wrappers around it are happy to consume a null pointer (funnily >>>> enough this one returns !void and is never checked) >>>> >>>> similar story for other func additions >>> >>> In fact, initially I had them merged, but then I couldn't find an >>> elegant way to handle AON regs. I can squash them back, if that's the >>> consensus. Any idea regarding AON regs? >> >> Digging in techpack/video, I found: >> >> commit c543f70aca8d40c593b8ad342d42e913a422c552 >> Author: Priyanka Gujjula >> Date: Fri Feb 14 13:38:31 2020 +0530 >> >> msm: vidc: Skip AON register programming for lagoon >> >> AON register programming is used to set NOC to low >> power mode during IRIS2 power off sequence. However >> AON register memory map is not applicable and hence >> skipping AON register programming for lagoon. >> >> Change-Id: Ib63248d118ed9fecfa5fa87925e8f69625dc1ba8 >> Signed-off-by: Priyanka Gujjula >> >> >> lagoon being a downstream codename of the aforementioned sm6350 >> >> Meaning yeah it's bus topology.. so I think an if-statement within >> a common flow would be what we want here.. >> >> perhaps >> >> if (core->iris_platform_data->num_vpp_pipe == 1) >> >> just like venus and downstream do for the most part, and kick the >> can down the road.. In an unlikely event someone decides to implement >> IRIS2_1 on a brand new SoC, we can delay our worries.. > > But this function is being used for VPU3 devices too, if I'm not > mistaken. So it becomes a bit ugly... Also I'm not sure if this is > really related to a num of VPP pipes or the CVP. Oh.. hm.. maybe we can add a .aon_shutdown op? I'm not sure how to proceed either Konrad