From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tq-group.com header.i=@tq-group.com header.b="kKaR7U4M" Received: from mx1.tq-group.com (mx1.tq-group.com [93.104.207.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E77710D1 for ; Thu, 7 Dec 2023 06:15:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tq-group.com; i=@tq-group.com; q=dns/txt; s=key1; t=1701958512; x=1733494512; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2g0BGb8jIEzmfFqJKa/JvmvhUlA22LhLY7cVrJZW26A=; b=kKaR7U4MHozEGCOkuq68waDrgju/BVWUN4uTL8WrfUynN1jEiX0RMOoW j1dWg6gZQKJNBevwnTHil7HjnN8poBn6cYpWdSneotKxAtPom0FXikKN0 zw5PJo5BBq4u0HWdjj88XlRYSyzZbz7QaP5fsQh2G6NhegUOXZ66QVEyV Tlq5iFUxDLvkjJkaNu1rRv12JBexmaYcs5gUKb/l8Z1bO2N9rfuxwhpSc 21z0hoFa8Jri5XGNQCmVjZgtrdweJMVQ0/XI1HfRF1E0UH0gBUyGRLeyE 5vlbNWWpU82lAFa4iVQP+zjreeNvo70Ac1leTNCU5ydpbhQ+bmJcP/04A w==; X-IronPort-AV: E=Sophos;i="6.04,256,1695679200"; d="scan'208";a="34385625" Received: from vtuxmail01.tq-net.de ([10.115.0.20]) by mx1.tq-group.com with ESMTP; 07 Dec 2023 15:15:10 +0100 Received: from steina-w.localnet (steina-w.tq-net.de [10.123.53.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by vtuxmail01.tq-net.de (Postfix) with ESMTPSA id BBEFE280075; Thu, 7 Dec 2023 15:15:09 +0100 (CET) From: Alexander Stein To: Laurent Pinchart Cc: Mauro Carvalho Chehab , Shawn Guo , Sascha Hauer , Fabio Estevam , Pengutronix Kernel Team , NXP Linux Team , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 1/1] media: nxp: imx8-isi-debug: Add missing 36-Bit DMA registers to debugfs output Date: Thu, 07 Dec 2023 15:15:10 +0100 Message-ID: <10383921.nUPlyArG6x@steina-w> Organization: TQ-Systems GmbH In-Reply-To: <20231207135539.GJ9675@pendragon.ideasonboard.com> References: <20231207110918.1338524-1-alexander.stein@ew.tq-group.com> <20231207135539.GJ9675@pendragon.ideasonboard.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" Am Donnerstag, 7. Dezember 2023, 14:55:39 CET schrieb Laurent Pinchart: > Hi Alexander, >=20 > Thank you for the patch. >=20 > On Thu, Dec 07, 2023 at 12:09:18PM +0100, Alexander Stein wrote: > > The extended address registers are missing in the debug output register > > list. These are only available on 36-Bit DMA platforms. Due to the > > prolonged name, the output width has to be adjusted as well. > >=20 > > Signed-off-by: Alexander Stein > > --- > > Changes in v2: > > * Split register set into regular and 36-Bit DMA only > > * Adjust output width to address longer register names > >=20 > > Currently only tested on TQMa8MPxL (imx8mp-tqma8mpql-mba8mpxl.dts) > >=20 > > .../platform/nxp/imx8-isi/imx8-isi-debug.c | 28 +++++++++++++++++-- > > 1 file changed, 25 insertions(+), 3 deletions(-) > >=20 > > diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c > > b/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c index > > 6709ab7ea1f3..398864b5e506 100644 > > --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c > > +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-debug.c > > @@ -22,10 +22,11 @@ static inline u32 mxc_isi_read(struct mxc_isi_pipe > > *pipe, u32 reg)>=20 > > static int mxc_isi_debug_dump_regs_show(struct seq_file *m, void *p) > > { > > #define MXC_ISI_DEBUG_REG(name) { name, #name } > >=20 > > - static const struct { > > + struct debug_regs { > >=20 > > u32 offset; > > const char * const name; > >=20 > > - } registers[] =3D { > > + }; > > + static const struct debug_regs registers[] =3D { > >=20 > > MXC_ISI_DEBUG_REG(CHNL_CTRL), > > MXC_ISI_DEBUG_REG(CHNL_IMG_CTRL), > > MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_CTRL), > >=20 > > @@ -67,6 +68,16 @@ static int mxc_isi_debug_dump_regs_show(struct seq_f= ile > > *m, void *p)>=20 > > MXC_ISI_DEBUG_REG(CHNL_SCL_IMG_CFG), > > MXC_ISI_DEBUG_REG(CHNL_FLOW_CTRL), > > =09 > > }; > >=20 > > + /* There registers contain the upper 4Bits of 36-Bit DMA addresses=20 */ >=20 > s/There/These/ >=20 > > + static const struct debug_regs registers_36bit_dma[] =3D { > > + MXC_ISI_DEBUG_REG(CHNL_Y_BUF1_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_U_BUF1_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_V_BUF1_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_Y_BUF2_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_U_BUF2_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_V_BUF2_XTND_ADDR), > > + MXC_ISI_DEBUG_REG(CHNL_IN_BUF_XTND_ADDR), > > + }; > >=20 > > struct mxc_isi_pipe *pipe =3D m->private; > > unsigned int i; > >=20 > > @@ -77,10 +88,21 @@ static int mxc_isi_debug_dump_regs_show(struct > > seq_file *m, void *p)>=20 > > seq_printf(m, "--- ISI pipe %u registers ---\n", pipe->id); > > =09 > > for (i =3D 0; i < ARRAY_SIZE(registers); ++i) > >=20 > > - seq_printf(m, "%20s[0x%02x]: 0x%08x\n", > > + seq_printf(m, "%21s[0x%02x]: 0x%08x\n", > >=20 > > registers[i].name, registers[i].offset, > > mxc_isi_read(pipe, registers[i].offset)); > >=20 > > + if (pipe->isi->pdata->has_36bit_dma) { > > + for (i =3D 0; i < ARRAY_SIZE(registers_36bit_dma); ++i) { > > + const struct debug_regs *reg =3D=20 ®isters_36bit_dma[i]; > > + > > + seq_printf(m, "%21s[0x%02x]: 0x%08x\n", > > + reg->name, > > + reg->offset, > > + mxc_isi_read(pipe, reg->offset)); >=20 > Lines should be aligned under the "m" of the first line. >=20 > I'll fix these small issues when applying, no need to send a v3. >=20 > Reviewed-by: Laurent Pinchart =46or the records: Also tested on TQMa8MxNL (imx8mn-tqma8mqnl-mba8mx.dts). = As=20 expected it prints only the same registers as before. Thanks Alexander >=20 > > + } > > + } > > + > >=20 > > pm_runtime_put(pipe->isi->dev); > > =09 > > return 0; =2D-=20 TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht M=FCnchen, HRB 105018 Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider http://www.tq-group.com/