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[88.112.128.43]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-55943b60737sm1957066e87.156.2025.07.14.07.16.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Jul 2025 07:16:48 -0700 (PDT) Message-ID: <11b573d5-ce4d-476c-b94c-216d427cd838@linaro.org> Date: Mon, 14 Jul 2025 17:16:46 +0300 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI D-PHY driver Content-Language: ru-RU To: Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250710-x1e-csi2-phy-v1-0-74acbb5b162b@linaro.org> <20250710-x1e-csi2-phy-v1-2-74acbb5b162b@linaro.org> From: Vladimir Zapolskiy In-Reply-To: <20250710-x1e-csi2-phy-v1-2-74acbb5b162b@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/10/25 19:16, Bryan O'Donoghue wrote: > Add a new MIPI CSI2 driver in D-PHY mode initially. The entire set of > existing CAMSS CSI PHY init sequences are imported in order to save time > and effort in later patches. > > In-line with other PHY drivers the process node name is omitted from the > compat string while the soc name is included. > > At the moment we follow the assignment of lane positions - the bitmap of > physical input lanes to logical lane numbers as a linear list per the > existing DPHY @lanes data-member. > > This is fine for us in upstream since we also map the lanes contiguously > but, our hardware can support different lane mappings so we should in the > future extend out the DPHY structure to capture the mapping. > > The Qualcomm 3PH class of PHYs can do both D-PHY and C-PHY mode. For now only > D-PHY is supported. > > In porting some of the logic over from camss-csiphy*.c to here its also > possible to rationalise some of the code. > > In particular use of regulator_bulk and clk_bulk as well as dropping the > seemingly useless and unused interrupt handler. > > The PHY sequences and a lot of the logic that goes with them are well proven > in CAMSS and mature so the main thing to watch out for here is how to get > the right sequencing of regulators, clocks and register-writes. > > Signed-off-by: Bryan O'Donoghue > --- > MAINTAINERS | 11 + > drivers/phy/qualcomm/Kconfig | 11 + > drivers/phy/qualcomm/Makefile | 6 + > drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 491 +++++++++++++++++++++ > drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c | 281 ++++++++++++ > drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 101 +++++ > 6 files changed, 901 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1ef99240a57ed1ad0d4501998970c7c3b85d3b81..69519e2d6dfb65771a3245735283645bb50a249a 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -20536,6 +20536,17 @@ S: Maintained > F: Documentation/devicetree/bindings/media/qcom,*-iris.yaml > F: drivers/media/platform/qcom/iris/ > > +QUALCOMM MIPI CSI2 PHY DRIVER > +M: Bryan O'Donoghue > +L: linux-phy@lists.infradead.org > +L: linux-media@vger.kernel.org > +L: linux-arm-msm@vger.kernel.org > +S: Supported > +F: Documentation/devicetree/bindings/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml > +F: drivers/phy/qualcomm/phy-qcom-mipi-csi2*.c > +F: drivers/phy/qualcomm/phy-qcom-mipi-csi2*.h > +F: include/dt-bindings/phy/phy-qcom-mipi-csi2* > + > QUALCOMM NAND CONTROLLER DRIVER > M: Manivannan Sadhasivam > L: linux-mtd@lists.infradead.org > diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig > index ef14f4e33973cff4103d8ea3b07cfd62d344e450..d0ab70827519c2b046d0fb03c14bb4d8ae2ec9a1 100644 > --- a/drivers/phy/qualcomm/Kconfig > +++ b/drivers/phy/qualcomm/Kconfig > @@ -28,6 +28,17 @@ config PHY_QCOM_EDP > Enable this driver to support the Qualcomm eDP PHY found in various > Qualcomm chipsets. > > +config PHY_QCOM_MIPI_CSI2 > + tristate "Qualcomm MIPI CSI2 PHY driver" > + depends on ARCH_QCOM || COMPILE_TEST > + depends on OF > + depends on COMMON_CLK > + select GENERIC_PHY > + select GENERIC_PHY_MIPI_DPHY > + help > + Enable this to support the MIPI CSI2 PHY driver found in various > + Qualcomm chipsets. > + > config PHY_QCOM_IPQ4019_USB > tristate "Qualcomm IPQ4019 USB PHY driver" > depends on OF && (ARCH_QCOM || COMPILE_TEST) > diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile > index 3851e28a212d4a677a5b41805868f38b9ab49841..67013d27cb0387b9d65dcbe030ea6e5eaaabbe91 100644 > --- a/drivers/phy/qualcomm/Makefile > +++ b/drivers/phy/qualcomm/Makefile > @@ -5,6 +5,12 @@ obj-$(CONFIG_PHY_QCOM_EDP) += phy-qcom-edp.o > obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o > obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o > obj-$(CONFIG_PHY_QCOM_M31_USB) += phy-qcom-m31.o > + > +phy-qcom-mipi-csi2-objs += phy-qcom-mipi-csi2-core.o \ > + phy-qcom-mipi-csi2-3ph-dphy.o > + > +obj-$(CONFIG_PHY_QCOM_MIPI_CSI2) += phy-qcom-mipi-csi2.o > + > obj-$(CONFIG_PHY_QCOM_PCIE2) += phy-qcom-pcie2.o > > obj-$(CONFIG_PHY_QCOM_QMP_COMBO) += phy-qcom-qmp-combo.o phy-qcom-qmp-usbc.o > diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > new file mode 100644 > index 0000000000000000000000000000000000000000..1a99efee88cc94ec0d29a335cd29f88af8a00c02 > --- /dev/null > +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c > @@ -0,0 +1,491 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * camss-phy_qcom_mipi_csi2-3ph-1-0.c > + * > + * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0 > + * > + * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. > + * Copyright (C) 2016-2025 Linaro Ltd. > + */ > +#define DEBUG Still under debugging?.. Well, the phy should be a multimedia device, and this driver is not the one, thus you can not use it to connect sensors and put the IP into a media pipeline. -- Best wishes, Vladimir