Re: [PATCH 13/13] IR: Port ene driver to new IR subsystem and enable it.

Maxim Levitsky
2010-07-31T14:51:37Z

On Sat, 2010-07-31 at 10:37 -0400, Jon Smirl wrote:
> On Sat, Jul 31, 2010 at 10:28 AM, Maxim Levitsky
> <maximlevitsky@gmail.com> wrote:
> > On Sat, 2010-07-31 at 09:55 -0400, Andy Walls wrote:
> >> On Fri, 2010-07-30 at 15:45 +0300, Maxim Levitsky wrote:
> >> > On Fri, 2010-07-30 at 08:07 -0400, Jon Smirl wrote:
> >> > > On Fri, Jul 30, 2010 at 8:02 AM, Jon Smirl <jonsmirl@gmail.com> wrote:
> >> > > > On Fri, Jul 30, 2010 at 7:54 AM, Maxim Levitsky <maximlevitsky@gmail.com> wrote:
> >>
> >> >
> >> > > >
> >> > > > + pll_freq = (ene_hw_read_reg(dev, ENE_PLLFRH) << 4) +
> >> > > > + (ene_hw_read_reg(dev, ENE_PLLFRL) >> 2);
> >> > >
> >> >
> >> >
> >> > > I can understand the shift of the high bits, but that shift of the low
> >> > > bits is unlikely. A manual would tell us if it is right.
> >> > >
> >> > This shift is correct (according to datasheet, which contains mostly
> >> > useless info, but it does dociment this reg briefly.)
> >>
> >> The KB3700 series datasheet indicates that the value from ENE_PLLFRL
> >> should be shifted by >> 4 bits, not by >> 2. Of course, the KB3700
> >> isn't the exact same chip.
> > You are right about that, thanks!
>
> I looked at KB3700 manual. It says it is trying to make a 32Mhz clock
> by multiplying 32.768Khz * 1000.
>
> 32,768 * 1000 = 32.768Mhz is a 2.4% error.
>
> When you are computing the timings of the pulses did you assume a
> 32Mhz clock? It looks like the clock is actuall 32.768Mhz.
No, I just take the samples hardware give me.
Lets just leave this as is.

Best regards,
Maxim Levitsky