* [PATCH 00/25] Add PCTV-80e Support to v4l
@ 2011-11-10 23:31 Patrick Dickey
2011-11-10 23:31 ` [PATCH 01/25] added PCTV80e information to cardlist file Patrick Dickey
` (22 more replies)
0 siblings, 23 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
These are the files required to support the Pinnacle PCTV-80e USB Tuner in
video-4-linux. The files were originally downloaded from
http://www.kernellabs.com/hg/~dheitmueller/v4l-dvb-80e and modified to fix
compilation errors and also to move the driver files from the drx39xy
subdirectory to the frontends directory.
There are still coding style errors (mainly trailing whitespace and DOS Line
Endings, but some other style errors exist as well). I have successfully
compiled and installed this under the 3.0.x kernel, but haven't tried under any
later kernels.
Patrick Dickey (25):
added PCTV80e information to cardlist file
added bsp_host for pctv80e support
added bsp_i2c for pctv80e support
added bsp_tuner for pctv80e support
added bsp_types for pctv80e support
added drx39xxj for pctv80e support
added drx39xxj header for pctv80e support
added drx39_dummy for pctv80e support
added drx_dap_fasi for pctv80e support
added drx_dap_fasi header for pctv80e support
added drx_driver for pctv80e support
added drx_driver header for pctv80e support
added drx_driver_version header for pctv80e support
added drxj for pctv80e support
added drxj header for pctv80e support
added drxj_map header for pctv80e support
added drxj_mc header for pctv80e support
added drxj_mc_vsb header for pctv80e support
added drxj_mc_vsbqam header for pctv80e support
added drxj_options header for pctv80e support
modified Kconfig to include pctv80e support
modified Makefile for pctv80e support
modified em28xx-cards for pctv80e support
modified em28xx-dvb for pctv80e support
modified em28xx header for pctv80e support
Documentation/video4linux/CARDLIST.em28xx | 1 +
drivers/media/dvb/frontends/Kconfig | 8 +
drivers/media/dvb/frontends/Makefile | 2 +
drivers/media/dvb/frontends/bsp_host.h | 80 +
drivers/media/dvb/frontends/bsp_i2c.h | 217 +
drivers/media/dvb/frontends/bsp_tuner.h | 215 +
drivers/media/dvb/frontends/bsp_types.h | 229 +
drivers/media/dvb/frontends/drx39xxj.c | 464 +
drivers/media/dvb/frontends/drx39xxj.h | 40 +
drivers/media/dvb/frontends/drx39xxj_dummy.c | 135 +
drivers/media/dvb/frontends/drx_dap_fasi.c | 670 +
drivers/media/dvb/frontends/drx_dap_fasi.h | 268 +
drivers/media/dvb/frontends/drx_driver.c | 1504 +++
drivers/media/dvb/frontends/drx_driver.h | 2588 ++++
drivers/media/dvb/frontends/drx_driver_version.h | 82 +
drivers/media/dvb/frontends/drxj.c |15732 ++++++++++++++++++++++
drivers/media/dvb/frontends/drxj.h | 990 ++
drivers/media/dvb/frontends/drxj_map.h |15359 +++++++++++++++++++++
drivers/media/dvb/frontends/drxj_mc.h | 3939 ++++++
drivers/media/dvb/frontends/drxj_mc_vsb.h | 744 +
drivers/media/dvb/frontends/drxj_mc_vsbqam.h | 1437 ++
drivers/media/dvb/frontends/drxj_options.h | 65 +
drivers/media/video/em28xx/em28xx-cards.c | 20 +
drivers/media/video/em28xx/em28xx-dvb.c | 25 +
drivers/media/video/em28xx/em28xx.h | 1 +
25 files changed, 44815 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/bsp_host.h
create mode 100644 drivers/media/dvb/frontends/bsp_i2c.h
create mode 100644 drivers/media/dvb/frontends/bsp_tuner.h
create mode 100644 drivers/media/dvb/frontends/bsp_types.h
create mode 100644 drivers/media/dvb/frontends/drx39xxj.c
create mode 100644 drivers/media/dvb/frontends/drx39xxj.h
create mode 100644 drivers/media/dvb/frontends/drx39xxj_dummy.c
create mode 100644 drivers/media/dvb/frontends/drx_dap_fasi.c
create mode 100644 drivers/media/dvb/frontends/drx_dap_fasi.h
create mode 100644 drivers/media/dvb/frontends/drx_driver.c
create mode 100644 drivers/media/dvb/frontends/drx_driver.h
create mode 100644 drivers/media/dvb/frontends/drx_driver_version.h
create mode 100644 drivers/media/dvb/frontends/drxj.c
create mode 100644 drivers/media/dvb/frontends/drxj.h
create mode 100644 drivers/media/dvb/frontends/drxj_map.h
create mode 100644 drivers/media/dvb/frontends/drxj_mc.h
create mode 100644 drivers/media/dvb/frontends/drxj_mc_vsb.h
create mode 100644 drivers/media/dvb/frontends/drxj_mc_vsbqam.h
create mode 100644 drivers/media/dvb/frontends/drxj_options.h
--
1.7.5.4
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/25] added PCTV80e information to cardlist file
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 02/25] added bsp_host for pctv80e support Patrick Dickey
` (21 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
Documentation/video4linux/CARDLIST.em28xx | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx
index d8c8544..319a9b2 100644
--- a/Documentation/video4linux/CARDLIST.em28xx
+++ b/Documentation/video4linux/CARDLIST.em28xx
@@ -78,3 +78,4 @@
78 -> PCTV nanoStick T2 290e (em28174)
79 -> Terratec Cinergy H5 (em2884) [0ccd:0043,0ccd:10a2]
80 -> PCTV DVB-S2 Stick (460e) (em28174)
+81 -> Pinnacle PCTV HD Mini (em2874) [2304:023f]
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 02/25] added bsp_host for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
2011-11-10 23:31 ` [PATCH 01/25] added PCTV80e information to cardlist file Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 03/25] added bsp_i2c " Patrick Dickey
` (20 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/bsp_host.h | 80 ++++++++++++++++++++++++++++++++
1 files changed, 80 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/bsp_host.h
diff --git a/drivers/media/dvb/frontends/bsp_host.h b/drivers/media/dvb/frontends/bsp_host.h
new file mode 100644
index 0000000..75a5f7b
--- /dev/null
+++ b/drivers/media/dvb/frontends/bsp_host.h
@@ -0,0 +1,80 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/**
+* \file $Id: bsp_host.h,v 1.3 2009/07/07 14:20:30 justin Exp $
+*
+* \brief Host and OS dependent type definitions, macro's and functions
+*
+*/
+
+#ifndef __DRXBSP_HOST_H__
+#define __DRXBSP_HOST_H__
+/*-------------------------------------------------------------------------
+INCLUDES
+-------------------------------------------------------------------------*/
+#include "bsp_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-------------------------------------------------------------------------
+TYPEDEFS
+-------------------------------------------------------------------------*/
+
+
+/*-------------------------------------------------------------------------
+DEFINES
+-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------
+Exported FUNCTIONS
+-------------------------------------------------------------------------*/
+DRXStatus_t DRXBSP_HST_Init(void);
+
+DRXStatus_t DRXBSP_HST_Term(void);
+
+void* DRXBSP_HST_Memcpy(void *to, void *from, u32_t n);
+
+int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n);
+
+u32_t DRXBSP_HST_Clock(void);
+
+DRXStatus_t DRXBSP_HST_Sleep(u32_t n);
+
+/*-------------------------------------------------------------------------
+THE END
+-------------------------------------------------------------------------*/
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRXBSP_HOST_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 03/25] added bsp_i2c for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
2011-11-10 23:31 ` [PATCH 01/25] added PCTV80e information to cardlist file Patrick Dickey
2011-11-10 23:31 ` [PATCH 02/25] added bsp_host for pctv80e support Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 04/25] added bsp_tuner " Patrick Dickey
` (19 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/bsp_i2c.h | 217 +++++++++++++++++++++++++++++++++
1 files changed, 217 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/bsp_i2c.h
diff --git a/drivers/media/dvb/frontends/bsp_i2c.h b/drivers/media/dvb/frontends/bsp_i2c.h
new file mode 100644
index 0000000..628c616
--- /dev/null
+++ b/drivers/media/dvb/frontends/bsp_i2c.h
@@ -0,0 +1,217 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/**
+* \file $Id: bsp_i2c.h,v 1.5 2009/07/07 14:20:30 justin Exp $
+*
+* \brief I2C API, implementation depends on board specifics
+*
+* This module encapsulates I2C access.In some applications several devices
+* share one I2C bus. If these devices have the same I2C address some kind
+* off "switch" must be implemented to ensure error free communication with
+* one device. In case such a "switch" is used, the device ID can be used
+* to implement control over this "switch".
+*
+*
+*/
+
+#ifndef __BSPI2C_H__
+#define __BSPI2C_H__
+/*------------------------------------------------------------------------------
+INCLUDES
+------------------------------------------------------------------------------*/
+#include "bsp_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*------------------------------------------------------------------------------
+TYPEDEFS
+------------------------------------------------------------------------------*/
+/**
+* \typedef I2Caddr_t
+* \brief I2C device address (7-bit or 10-bit)
+*/
+typedef u16_t I2Caddr_t;
+
+/**
+* \typedef I2CdevId_t
+* \brief Device identifier.
+*
+* The device ID can be useful if several devices share an I2C address,
+* or if multiple I2C busses are used.
+* It can be used to control a "switch" selecting the correct device and/or
+* I2C bus.
+*
+*/
+typedef u16_t I2CdevId_t;
+
+/**
+* \struct _I2CDeviceAddr_t
+* \brief I2C device parameters.
+*
+* This structure contains the I2C address, the device ID and a userData pointer.
+* The userData pointer can be used for application specific purposes.
+*
+*/
+struct _I2CDeviceAddr_t {
+ I2Caddr_t i2cAddr; /**< The I2C address of the device. */
+ I2CdevId_t i2cDevId; /**< The device identifier. */
+ void *userData; /**< User data pointer */
+};
+
+/**
+* \typedef I2CDeviceAddr_t
+* \brief I2C device parameters.
+*
+* This structure contains the I2C address and the device ID.
+*
+*/
+typedef struct _I2CDeviceAddr_t I2CDeviceAddr_t;
+
+/**
+* \typedef pI2CDeviceAddr_t
+* \brief Pointer to I2C device parameters.
+*/
+typedef I2CDeviceAddr_t *pI2CDeviceAddr_t;
+
+/*------------------------------------------------------------------------------
+DEFINES
+------------------------------------------------------------------------------*/
+
+/*------------------------------------------------------------------------------
+MACROS
+------------------------------------------------------------------------------*/
+
+/**
+* \def IS_I2C_10BIT(addr)
+* \brief Determine if I2C address 'addr' is a 10 bits address or not.
+* \param addr The I2C address.
+* \return int.
+* \retval 0 if address is not a 10 bits I2C address.
+* \retval 1 if address is a 10 bits I2C address.
+*/
+#define IS_I2C_10BIT(addr) \
+ (((addr) & 0xF8) == 0xF0)
+
+/*------------------------------------------------------------------------------
+ENUM
+------------------------------------------------------------------------------*/
+
+/*------------------------------------------------------------------------------
+STRUCTS
+------------------------------------------------------------------------------*/
+
+/*------------------------------------------------------------------------------
+Exported FUNCTIONS
+------------------------------------------------------------------------------*/
+
+
+/**
+* \fn DRXBSP_I2C_Init()
+* \brief Initialize I2C communication module.
+* \return DRXStatus_t Return status.
+* \retval DRX_STS_OK Initialization successful.
+* \retval DRX_STS_ERROR Initialization failed.
+*/
+DRXStatus_t DRXBSP_I2C_Init(void);
+
+
+/**
+* \fn DRXBSP_I2C_Term()
+* \brief Terminate I2C communication module.
+* \return DRXStatus_t Return status.
+* \retval DRX_STS_OK Termination successful.
+* \retval DRX_STS_ERROR Termination failed.
+*/
+DRXStatus_t DRXBSP_I2C_Term(void);
+
+/**
+* \fn DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr,
+* u16_t wCount,
+* pu8_t wData,
+* pI2CDeviceAddr_t rDevAddr,
+* u16_t rCount,
+* pu8_t rData)
+* \brief Read and/or write count bytes from I2C bus, store them in data[].
+* \param wDevAddr The device i2c address and the device ID to write to
+* \param wCount The number of bytes to write
+* \param wData The array to write the data to
+* \param rDevAddr The device i2c address and the device ID to read from
+* \param rCount The number of bytes to read
+* \param rData The array to read the data from
+* \return DRXStatus_t Return status.
+* \retval DRX_STS_OK Succes.
+* \retval DRX_STS_ERROR Failure.
+* \retval DRX_STS_INVALID_ARG Parameter 'wcount' is not zero but parameter
+* 'wdata' contains NULL.
+* Idem for 'rcount' and 'rdata'.
+* Both wDevAddr and rDevAddr are NULL.
+*
+* This function must implement an atomic write and/or read action on the I2C bus
+* No other process may use the I2C bus when this function is executing.
+* The critical section of this function runs from and including the I2C
+* write, up to and including the I2C read action.
+*
+* The device ID can be useful if several devices share an I2C address.
+* It can be used to control a "switch" on the I2C bus to the correct device.
+*/
+DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr,
+ u16_t wCount,
+ pu8_t wData,
+ pI2CDeviceAddr_t rDevAddr,
+ u16_t rCount,
+ pu8_t rData);
+
+
+/**
+* \fn DRXBSP_I2C_ErrorText()
+* \brief Returns a human readable error.
+* Counter part of numerical DRX_I2C_Error_g.
+*
+* \return char* Pointer to human readable error text.
+*/
+char* DRXBSP_I2C_ErrorText(void);
+
+/**
+* \var DRX_I2C_Error_g;
+* \brief I2C specific error codes, platform dependent.
+*/
+extern int DRX_I2C_Error_g;
+
+
+/*------------------------------------------------------------------------------
+THE END
+------------------------------------------------------------------------------*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* __BSPI2C_H__ */
+
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 04/25] added bsp_tuner for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (2 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 03/25] added bsp_i2c " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 05/25] added bsp_types " Patrick Dickey
` (18 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/bsp_tuner.h | 215 +++++++++++++++++++++++++++++++
1 files changed, 215 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/bsp_tuner.h
diff --git a/drivers/media/dvb/frontends/bsp_tuner.h b/drivers/media/dvb/frontends/bsp_tuner.h
new file mode 100644
index 0000000..b67027f
--- /dev/null
+++ b/drivers/media/dvb/frontends/bsp_tuner.h
@@ -0,0 +1,215 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/**
+* \file $Id: bsp_tuner.h,v 1.5 2009/10/19 22:15:13 dingtao Exp $
+*
+* \brief Tuner dependable type definitions, macro's and functions
+*
+*/
+
+#ifndef __DRXBSP_TUNER_H__
+#define __DRXBSP_TUNER_H__
+/*------------------------------------------------------------------------------
+INCLUDES
+------------------------------------------------------------------------------*/
+#include "bsp_types.h"
+#include "bsp_i2c.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+DEFINES
+------------------------------------------------------------------------------*/
+
+
+ /* Sub-mode bits should be adjacent and incremental */
+#define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
+#define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
+#define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
+#define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */
+#define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */
+#define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */
+#define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */
+#define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */
+
+#define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */
+#define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */
+#define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */
+#define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */
+#define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */
+#define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */
+#define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
+
+#define TUNER_MODE_SUB_MAX 8
+#define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
+ TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \
+ TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \
+ TUNER_MODE_SUB6 | TUNER_MODE_SUB7)
+
+/*------------------------------------------------------------------------------
+TYPEDEFS
+------------------------------------------------------------------------------*/
+
+typedef u32_t TUNERMode_t;
+typedef pu32_t pTUNERMode_t;
+
+typedef char* TUNERSubMode_t; /* description of submode */
+typedef TUNERSubMode_t *pTUNERSubMode_t;
+
+
+typedef enum {
+
+ TUNER_LOCKED,
+ TUNER_NOT_LOCKED
+
+} TUNERLockStatus_t, *pTUNERLockStatus_t;
+
+
+typedef struct {
+
+ char *name; /* Tuner brand & type name */
+ DRXFrequency_t minFreqRF; /* Lowest RF input frequency, in kHz */
+ DRXFrequency_t maxFreqRF; /* Highest RF input frequency, in kHz */
+
+ u8_t subMode; /* Index to sub-mode in use */
+ pTUNERSubMode_t subModeDescriptions; /* Pointer to description of sub-modes*/
+ u8_t subModes; /* Number of available sub-modes */
+
+ /* The following fields will be either 0, NULL or FALSE and do not need
+ initialisation */
+ void *selfCheck; /* gives proof of initialization */
+ Bool_t programmed; /* only valid if selfCheck is OK */
+ DRXFrequency_t RFfrequency; /* only valid if programmed */
+ DRXFrequency_t IFfrequency; /* only valid if programmed */
+
+ void* myUserData; /* pointer to associated demod instance */
+ u16_t myCapabilities; /* value for storing application flags */
+
+} TUNERCommonAttr_t, *pTUNERCommonAttr_t;
+
+
+/*
+* Generic functions for DRX devices.
+*/
+typedef struct TUNERInstance_s *pTUNERInstance_t;
+
+typedef DRXStatus_t (*TUNEROpenFunc_t)(pTUNERInstance_t tuner);
+typedef DRXStatus_t (*TUNERCloseFunc_t)(pTUNERInstance_t tuner);
+
+typedef DRXStatus_t (*TUNERSetFrequencyFunc_t)(pTUNERInstance_t tuner,
+ TUNERMode_t mode,
+ DRXFrequency_t frequency);
+
+typedef DRXStatus_t (*TUNERGetFrequencyFunc_t)(pTUNERInstance_t tuner,
+ TUNERMode_t mode,
+ pDRXFrequency_t RFfrequency,
+ pDRXFrequency_t IFfrequency);
+
+typedef DRXStatus_t (*TUNERLockStatusFunc_t)(pTUNERInstance_t tuner,
+ pTUNERLockStatus_t lockStat);
+
+typedef DRXStatus_t (*TUNERi2cWriteReadFunc_t)(pTUNERInstance_t tuner,
+ pI2CDeviceAddr_t wDevAddr,
+ u16_t wCount,
+ pu8_t wData,
+ pI2CDeviceAddr_t rDevAddr,
+ u16_t rCount,
+ pu8_t rData);
+
+typedef struct
+{
+ TUNEROpenFunc_t openFunc;
+ TUNERCloseFunc_t closeFunc;
+ TUNERSetFrequencyFunc_t setFrequencyFunc;
+ TUNERGetFrequencyFunc_t getFrequencyFunc;
+ TUNERLockStatusFunc_t lockStatusFunc;
+ TUNERi2cWriteReadFunc_t i2cWriteReadFunc;
+
+} TUNERFunc_t, *pTUNERFunc_t;
+
+typedef struct TUNERInstance_s {
+
+ I2CDeviceAddr_t myI2CDevAddr;
+ pTUNERCommonAttr_t myCommonAttr;
+ void* myExtAttr;
+ pTUNERFunc_t myFunct;
+
+} TUNERInstance_t;
+
+
+/*------------------------------------------------------------------------------
+ENUM
+------------------------------------------------------------------------------*/
+
+/*------------------------------------------------------------------------------
+STRUCTS
+------------------------------------------------------------------------------*/
+
+
+/*------------------------------------------------------------------------------
+Exported FUNCTIONS
+------------------------------------------------------------------------------*/
+
+DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner);
+
+DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner);
+
+DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner,
+ TUNERMode_t mode,
+ DRXFrequency_t frequency);
+
+DRXStatus_t DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner,
+ TUNERMode_t mode,
+ pDRXFrequency_t RFfrequency,
+ pDRXFrequency_t IFfrequency);
+
+DRXStatus_t DRXBSP_TUNER_LockStatus(pTUNERInstance_t tuner,
+ pTUNERLockStatus_t lockStat);
+
+DRXStatus_t DRXBSP_TUNER_DefaultI2CWriteRead(pTUNERInstance_t tuner,
+ pI2CDeviceAddr_t wDevAddr,
+ u16_t wCount,
+ pu8_t wData,
+ pI2CDeviceAddr_t rDevAddr,
+ u16_t rCount,
+ pu8_t rData);
+
+/*------------------------------------------------------------------------------
+THE END
+------------------------------------------------------------------------------*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* __DRXBSP_TUNER_H__ */
+
+/* End of file */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 05/25] added bsp_types for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (3 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 04/25] added bsp_tuner " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 06/25] added drx39xxj " Patrick Dickey
` (17 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/bsp_types.h | 229 +++++++++++++++++++++++++++++++
1 files changed, 229 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/bsp_types.h
diff --git a/drivers/media/dvb/frontends/bsp_types.h b/drivers/media/dvb/frontends/bsp_types.h
new file mode 100644
index 0000000..1c48046
--- /dev/null
+++ b/drivers/media/dvb/frontends/bsp_types.h
@@ -0,0 +1,229 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/**
+* \file $Id: bsp_types.h,v 1.5 2009/08/06 12:55:57 carlo Exp $
+*
+* \brief General type definitions for board support packages
+*
+* This file contains type definitions that are needed for almost any
+* board support package.
+* The definitions are host and project independent.
+*
+*/
+
+#ifndef __BSP_TYPES_H__
+#define __BSP_TYPES_H__
+/*-------------------------------------------------------------------------
+INCLUDES
+-------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*-------------------------------------------------------------------------
+TYPEDEFS
+-------------------------------------------------------------------------*/
+
+/**
+* \typedef unsigned char u8_t
+* \brief type definition of an unsigned 8 bits integer
+*/
+typedef unsigned char u8_t;
+/**
+* \typedef char s8_t
+* \brief type definition of a signed 8 bits integer
+*/
+typedef char s8_t;
+/**
+* \typedef unsigned short u16_t *pu16_t
+* \brief type definition of an unsigned 16 bits integer
+*/
+typedef unsigned short u16_t;
+/**
+* \typedef short s16_t
+* \brief type definition of a signed 16 bits integer
+*/
+typedef short s16_t;
+/**
+* \typedef unsigned long u32_t
+* \brief type definition of an unsigned 32 bits integer
+*/
+typedef unsigned long u32_t;
+/**
+* \typedef long s32_t
+* \brief type definition of a signed 32 bits integer
+*/
+typedef long s32_t;
+/*
+* \typedef struct ... u64_t
+* \brief type definition of an usigned 64 bits integer
+*/
+typedef struct {
+ u32_t MSLW;
+ u32_t LSLW;
+} u64_t;
+/*
+* \typedef struct ... i64_t
+* \brief type definition of a signed 64 bits integer
+*/
+typedef struct {
+ s32_t MSLW;
+ u32_t LSLW;
+} s64_t;
+
+/**
+* \typedef u8_t *pu8_t
+* \brief type definition of pointer to an unsigned 8 bits integer
+*/
+typedef u8_t *pu8_t;
+/**
+* \typedef s8_t *ps8_t
+* \brief type definition of pointer to a signed 8 bits integer
+*/
+typedef s8_t *ps8_t;
+/**
+* \typedef u16_t *pu16_t
+* \brief type definition of pointer to an unsigned 16 bits integer
+*/
+typedef u16_t *pu16_t;
+/**
+* \typedef s16_t *ps16_t
+* \brief type definition of pointer to a signed 16 bits integer
+*/
+typedef s16_t *ps16_t;
+/**
+* \typedef u32_t *pu32_t
+* \brief type definition of pointer to an unsigned 32 bits integer
+*/
+typedef u32_t *pu32_t;
+/**
+* \typedef s32_t *ps32_t
+* \brief type definition of pointer to a signed 32 bits integer
+*/
+typedef s32_t *ps32_t;
+/**
+* \typedef u64_t *pu64_t
+* \brief type definition of pointer to an usigned 64 bits integer
+*/
+typedef u64_t *pu64_t;
+/**
+* \typedef s64_t *ps64_t
+* \brief type definition of pointer to a signed 64 bits integer
+*/
+typedef s64_t *ps64_t;
+
+
+/**
+* \typedef s32_t DRXFrequency_t
+* \brief type definition of frequency
+*/
+typedef s32_t DRXFrequency_t;
+
+/**
+* \typedef DRXFrequency_t *pDRXFrequency_t
+* \brief type definition of a pointer to a frequency
+*/
+typedef DRXFrequency_t *pDRXFrequency_t;
+
+/**
+* \typedef u32_t DRXSymbolrate_t
+* \brief type definition of symbol rate
+*/
+typedef u32_t DRXSymbolrate_t;
+
+/**
+* \typedef DRXSymbolrate_t *pDRXSymbolrate_t
+* \brief type definition of a pointer to a symbol rate
+*/
+typedef DRXSymbolrate_t *pDRXSymbolrate_t;
+
+/*-------------------------------------------------------------------------
+DEFINES
+-------------------------------------------------------------------------*/
+/**
+* \def NULL
+* \brief Define NULL for target.
+*/
+#ifndef NULL
+#define NULL (0)
+#endif
+
+/*-------------------------------------------------------------------------
+ENUM
+-------------------------------------------------------------------------*/
+
+/*
+* Boolean datatype. Only define if not already defined TRUE or FALSE.
+*/
+#if defined (TRUE) || defined (FALSE)
+typedef int Bool_t;
+#else
+/**
+* \enum Bool_t
+* \brief Boolean type
+*/
+typedef enum {
+ FALSE = 0,
+ TRUE
+} Bool_t;
+#endif
+typedef Bool_t *pBool_t;
+
+/**
+* \enum DRXStatus_t
+* \brief Various return statusses
+*/
+typedef enum {
+ DRX_STS_READY = 3, /**< device/service is ready */
+ DRX_STS_BUSY = 2, /**< device/service is busy */
+ DRX_STS_OK = 1, /**< everything is OK */
+ DRX_STS_INVALID_ARG = -1, /**< invalid arguments */
+ DRX_STS_ERROR = -2, /**< general error */
+ DRX_STS_FUNC_NOT_AVAILABLE = -3 /**< unavailable functionality */
+} DRXStatus_t, *pDRXStatus_t;
+
+
+/*-------------------------------------------------------------------------
+STRUCTS
+-------------------------------------------------------------------------*/
+
+/**
+Exported FUNCTIONS
+-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------
+THE END
+-------------------------------------------------------------------------*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* __BSP_TYPES_H__ */
+
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 06/25] added drx39xxj for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (4 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 05/25] added bsp_types " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 07/25] added drx39xxj header " Patrick Dickey
` (16 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drx39xxj.c | 464 ++++++++++++++++++++++++++++++++
1 files changed, 464 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drx39xxj.c
diff --git a/drivers/media/dvb/frontends/drx39xxj.c b/drivers/media/dvb/frontends/drx39xxj.c
new file mode 100644
index 0000000..a74e81b
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx39xxj.c
@@ -0,0 +1,464 @@
+/*
+ * Driver for Micronas DRX39xx family (drx3933j)
+ *
+ * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+
+#include "dvb_frontend.h"
+#include "drx39xxj.h"
+#include "drx_driver.h"
+#include "bsp_types.h"
+#include "bsp_tuner.h"
+#include "drxj_mc.h"
+#include "drxj.h"
+
+static int drx39xxj_set_powerstate(struct dvb_frontend* fe, int enable)
+{
+ struct drx39xxj_state *state = fe->demodulator_priv;
+ DRXDemodInstance_t *demod = state->demod;
+ DRXStatus_t result;
+ DRXPowerMode_t powerMode;
+
+ if (enable)
+ powerMode = DRX_POWER_UP;
+ else
+ powerMode = DRX_POWER_DOWN;
+
+ result = DRX_Ctrl(demod, DRX_CTRL_POWER_MODE, &powerMode);
+ if (result != DRX_STS_OK) {
+ printk("Power state change failed\n");
+ return 0;
+ }
+
+ state->powered_up = enable;
+ return 0;
+}
+
+static int drx39xxj_read_status(struct dvb_frontend* fe, fe_status_t* status)
+{
+ struct drx39xxj_state* state = fe->demodulator_priv;
+ DRXDemodInstance_t *demod = state->demod;
+ DRXStatus_t result;
+ DRXLockStatus_t lock_status;
+
+ *status = 0;
+
+ result = DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lock_status);
+ if (result != DRX_STS_OK) {
+ printk("drx39xxj: could not get lock status!\n");
+ *status = 0;
+ }
+
+ switch (lock_status) {
+ case DRX_NEVER_LOCK:
+ *status = 0;
+ printk("drx says NEVER_LOCK\n");
+ break;
+ case DRX_NOT_LOCKED:
+ *status = 0;
+ break;
+ case DRX_LOCK_STATE_1:
+ case DRX_LOCK_STATE_2:
+ case DRX_LOCK_STATE_3:
+ case DRX_LOCK_STATE_4:
+ case DRX_LOCK_STATE_5:
+ case DRX_LOCK_STATE_6:
+ case DRX_LOCK_STATE_7:
+ case DRX_LOCK_STATE_8:
+ case DRX_LOCK_STATE_9:
+ *status = FE_HAS_SIGNAL
+ | FE_HAS_CARRIER
+ | FE_HAS_VITERBI
+ | FE_HAS_SYNC;
+ break;
+ case DRX_LOCKED:
+ *status = FE_HAS_SIGNAL
+ | FE_HAS_CARRIER
+ | FE_HAS_VITERBI
+ | FE_HAS_SYNC
+ | FE_HAS_LOCK;
+ break;
+ default:
+ printk("Lock state unknown %d\n", lock_status);
+ }
+
+ return 0;
+}
+
+static int drx39xxj_read_ber(struct dvb_frontend* fe, u32* ber)
+{
+ struct drx39xxj_state* state = fe->demodulator_priv;
+ DRXDemodInstance_t *demod = state->demod;
+ DRXStatus_t result;
+ DRXSigQuality_t sig_quality;
+
+ result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
+ if (result != DRX_STS_OK) {
+ printk("drx39xxj: could not get ber!\n");
+ *ber = 0;
+ return 0;
+ }
+
+ *ber = sig_quality.postReedSolomonBER;
+ return 0;
+}
+
+static int drx39xxj_read_signal_strength(struct dvb_frontend* fe, u16* strength)
+{
+ struct drx39xxj_state* state = fe->demodulator_priv;
+ DRXDemodInstance_t *demod = state->demod;
+ DRXStatus_t result;
+ DRXSigQuality_t sig_quality;
+
+ result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
+ if (result != DRX_STS_OK) {
+ printk("drx39xxj: could not get signal strength!\n");
+ *strength = 0;
+ return 0;
+ }
+
+ /* 1-100% scaled to 0-65535 */
+ *strength = (sig_quality.indicator * 65535 / 100);
+ return 0;
+}
+
+static int drx39xxj_read_snr(struct dvb_frontend* fe, u16* snr)
+{
+ struct drx39xxj_state* state = fe->demodulator_priv;
+ DRXDemodInstance_t *demod = state->demod;
+ DRXStatus_t result;
+ DRXSigQuality_t sig_quality;
+
+ result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
+ if (result != DRX_STS_OK) {
+ printk("drx39xxj: could not read snr!\n");
+ *snr = 0;
+ return 0;
+ }
+
+ *snr = sig_quality.MER;
+ return 0;
+}
+
+static int drx39xxj_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
+{
+ struct drx39xxj_state* state = fe->demodulator_priv;
+ DRXDemodInstance_t *demod = state->demod;
+ DRXStatus_t result;
+ DRXSigQuality_t sig_quality;
+
+ result = DRX_Ctrl(demod, DRX_CTRL_SIG_QUALITY, &sig_quality);
+ if (result != DRX_STS_OK) {
+ printk("drx39xxj: could not get uc blocks!\n");
+ *ucblocks = 0;
+ return 0;
+ }
+
+ *ucblocks = sig_quality.packetError;
+ return 0;
+}
+
+static int drx39xxj_get_frontend(struct dvb_frontend* fe,
+ struct dvb_frontend_parameters *p)
+{
+ return 0;
+}
+
+static int drx39xxj_set_frontend(struct dvb_frontend* fe,
+ struct dvb_frontend_parameters *p)
+{
+#ifdef DJH_DEBUG
+ int i;
+#endif
+
+ struct drx39xxj_state* state = fe->demodulator_priv;
+ DRXDemodInstance_t *demod = state->demod;
+ DRXStandard_t standard = DRX_STANDARD_8VSB;
+ DRXChannel_t channel;
+ DRXStatus_t result;
+ DRXUIOData_t uioData;
+ DRXChannel_t defChannel = {/* frequency */ 0,
+ /* bandwidth */ DRX_BANDWIDTH_6MHZ,
+ /* mirror */ DRX_MIRROR_NO,
+ /* constellation */ DRX_CONSTELLATION_AUTO,
+ /* hierarchy */ DRX_HIERARCHY_UNKNOWN,
+ /* priority */ DRX_PRIORITY_UNKNOWN,
+ /* coderate */ DRX_CODERATE_UNKNOWN,
+ /* guard */ DRX_GUARD_UNKNOWN,
+ /* fftmode */ DRX_FFTMODE_UNKNOWN,
+ /* classification */ DRX_CLASSIFICATION_AUTO,
+ /* symbolrate */ 5057000,
+ /* interleavemode */ DRX_INTERLEAVEMODE_UNKNOWN,
+ /* ldpc */ DRX_LDPC_UNKNOWN,
+ /* carrier */ DRX_CARRIER_UNKNOWN,
+ /* frame mode */ DRX_FRAMEMODE_UNKNOWN
+ };
+
+ /* Bring the demod out of sleep */
+ drx39xxj_set_powerstate(fe, 1);
+
+ /* Now make the tuner do it's thing... */
+ if (fe->ops.tuner_ops.set_params) {
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+ fe->ops.tuner_ops.set_params(fe, p);
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+ }
+
+ if (standard != state->current_standard || state->powered_up == 0) {
+ /* Set the standard (will be powered up if necessary */
+ result = DRX_Ctrl(demod, DRX_CTRL_SET_STANDARD, &standard);
+ if (result != DRX_STS_OK) {
+ printk("Failed to set standard! result=%02x\n", result);
+ return -EINVAL;
+ }
+ state->powered_up = 1;
+ state->current_standard = standard;
+ }
+
+ /* set channel parameters */
+ channel = defChannel;
+ channel.frequency = p->frequency / 1000;
+ channel.bandwidth = DRX_BANDWIDTH_6MHZ;
+ channel.constellation = DRX_CONSTELLATION_AUTO;
+
+ /* program channel */
+ result = DRX_Ctrl(demod, DRX_CTRL_SET_CHANNEL, &channel);
+ if (result != DRX_STS_OK) {
+ printk("Failed to set channel!\n");
+ return -EINVAL;
+ }
+
+ // Just for giggles, let's shut off the LNA again....
+ uioData.uio = DRX_UIO1;
+ uioData.value = FALSE;
+ result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
+ if (result != DRX_STS_OK) {
+ printk("Failed to disable LNA!\n");
+ return 0;
+ }
+
+#ifdef DJH_DEBUG
+ for(i = 0; i < 2000; i++) {
+ fe_status_t status;
+ drx39xxj_read_status(fe, &status);
+ printk("i=%d status=%d\n", i, status);
+ msleep(100);
+ i += 100;
+ }
+#endif
+
+ return 0;
+}
+
+
+static int drx39xxj_sleep(struct dvb_frontend* fe)
+{
+ /* power-down the demodulator */
+ return drx39xxj_set_powerstate(fe, 0);
+}
+
+static int drx39xxj_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+ struct drx39xxj_state *state = fe->demodulator_priv;
+ DRXDemodInstance_t *demod = state->demod;
+ Bool_t i2c_gate_state;
+ DRXStatus_t result;
+
+#ifdef DJH_DEBUG
+ printk("i2c gate call: enable=%d state=%d\n", enable,
+ state->i2c_gate_open);
+#endif
+
+ if (enable)
+ i2c_gate_state = TRUE;
+ else
+ i2c_gate_state = FALSE;
+
+ if (state->i2c_gate_open == enable) {
+ /* We're already in the desired state */
+ return 0;
+ }
+
+ result = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &i2c_gate_state);
+ if (result != DRX_STS_OK) {
+ printk("drx39xxj: could not open i2c gate [%d]\n", result);
+ dump_stack();
+ } else {
+ state->i2c_gate_open = enable;
+ }
+ return 0;
+}
+
+
+static int drx39xxj_init(struct dvb_frontend* fe)
+{
+ /* Bring the demod out of sleep */
+ drx39xxj_set_powerstate(fe, 1);
+
+ return 0;
+}
+
+static int drx39xxj_get_tune_settings(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *tune)
+{
+ tune->min_delay_ms = 1000;
+ return 0;
+}
+
+static void drx39xxj_release(struct dvb_frontend* fe)
+{
+ struct drx39xxj_state* state = fe->demodulator_priv;
+ kfree(state);
+}
+
+static struct dvb_frontend_ops drx39xxj_ops;
+
+struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c)
+{
+ struct drx39xxj_state* state = NULL;
+
+ I2CDeviceAddr_t *demodAddr = NULL;
+ DRXCommonAttr_t *demodCommAttr = NULL;
+ DRXJData_t *demodExtAttr = NULL;
+ DRXDemodInstance_t *demod = NULL;
+ DRXUIOCfg_t uioCfg;
+ DRXUIOData_t uioData;
+ DRXStatus_t result;
+
+ /* allocate memory for the internal state */
+ state = kmalloc(sizeof(struct drx39xxj_state), GFP_KERNEL);
+ if (state == NULL)
+ goto error;
+
+ demod = kmalloc(sizeof(DRXDemodInstance_t), GFP_KERNEL);
+ if (demod == NULL)
+ goto error;
+
+ demodAddr = kmalloc(sizeof(I2CDeviceAddr_t), GFP_KERNEL);
+ if (demodAddr == NULL)
+ goto error;
+
+ demodCommAttr = kmalloc(sizeof(DRXCommonAttr_t), GFP_KERNEL);
+ if (demodCommAttr == NULL)
+ goto error;
+
+ demodExtAttr = kmalloc(sizeof(DRXJData_t), GFP_KERNEL);
+ if (demodExtAttr == NULL)
+ goto error;
+
+ /* setup the state */
+ state->i2c = i2c;
+ state->demod = demod;
+
+ memcpy(demod, &DRXJDefaultDemod_g, sizeof(DRXDemodInstance_t));
+
+ demod->myI2CDevAddr = demodAddr;
+ memcpy(demod->myI2CDevAddr, &DRXJDefaultAddr_g,
+ sizeof(I2CDeviceAddr_t));
+ demod->myI2CDevAddr->userData = state;
+ demod->myCommonAttr = demodCommAttr;
+ memcpy(demod->myCommonAttr, &DRXJDefaultCommAttr_g,
+ sizeof(DRXCommonAttr_t));
+ demod->myCommonAttr->microcode = DRXJ_MC_MAIN;
+ // demod->myCommonAttr->verifyMicrocode = FALSE;
+ demod->myCommonAttr->verifyMicrocode = TRUE;
+ demod->myCommonAttr->intermediateFreq = 5000;
+
+ demod->myExtAttr = demodExtAttr;
+ memcpy(demod->myExtAttr, &DRXJData_g, sizeof(DRXJData_t));
+ ((DRXJData_t *) demod->myExtAttr)->uioSmaTxMode = DRX_UIO_MODE_READWRITE;
+
+ demod->myTuner = NULL;
+
+ result = DRX_Open(demod);
+ if (result != DRX_STS_OK) {
+ printk("DRX open failed! Aborting\n");
+ kfree(state);
+ return NULL;
+ }
+
+ /* Turn off the LNA */
+ uioCfg.uio = DRX_UIO1;
+ uioCfg.mode = DRX_UIO_MODE_READWRITE;
+ /* Configure user-I/O #3: enable read/write */
+ result = DRX_Ctrl(demod, DRX_CTRL_UIO_CFG, &uioCfg);
+ if (result != DRX_STS_OK) {
+ printk("Failed to setup LNA GPIO!\n");
+ return NULL;
+ }
+
+ uioData.uio = DRX_UIO1;
+ uioData.value = FALSE;
+ result = DRX_Ctrl(demod, DRX_CTRL_UIO_WRITE, &uioData);
+ if (result != DRX_STS_OK) {
+ printk("Failed to disable LNA!\n");
+ return NULL;
+ }
+
+ /* create dvb_frontend */
+ memcpy(&state->frontend.ops, &drx39xxj_ops,
+ sizeof(struct dvb_frontend_ops));
+
+ state->frontend.demodulator_priv = state;
+ return &state->frontend;
+
+error:
+ if (state != NULL)
+ kfree(state);
+ if (demod != NULL)
+ kfree(demod);
+ return NULL;
+}
+
+static struct dvb_frontend_ops drx39xxj_ops = {
+
+ .info = {
+ .name = "Micronas DRX39xxj family Frontend",
+ .type = FE_ATSC | FE_QAM,
+ .frequency_stepsize = 62500,
+ .frequency_min = 51000000,
+ .frequency_max = 858000000,
+ .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
+ },
+
+ .init = drx39xxj_init,
+ .i2c_gate_ctrl = drx39xxj_i2c_gate_ctrl,
+ .sleep = drx39xxj_sleep,
+ .set_frontend = drx39xxj_set_frontend,
+ .get_frontend = drx39xxj_get_frontend,
+ .get_tune_settings = drx39xxj_get_tune_settings,
+ .read_status = drx39xxj_read_status,
+ .read_ber = drx39xxj_read_ber,
+ .read_signal_strength = drx39xxj_read_signal_strength,
+ .read_snr = drx39xxj_read_snr,
+ .read_ucblocks = drx39xxj_read_ucblocks,
+ .release = drx39xxj_release,
+};
+
+MODULE_DESCRIPTION("Micronas DRX39xxj Frontend");
+MODULE_AUTHOR("Devin Heitmueller");
+MODULE_LICENSE("GPL");
+
+EXPORT_SYMBOL(drx39xxj_attach);
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 07/25] added drx39xxj header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (5 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 06/25] added drx39xxj " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 08/25] added drx39_dummy " Patrick Dickey
` (15 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drx39xxj.h | 40 ++++++++++++++++++++++++++++++++
1 files changed, 40 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drx39xxj.h
diff --git a/drivers/media/dvb/frontends/drx39xxj.h b/drivers/media/dvb/frontends/drx39xxj.h
new file mode 100644
index 0000000..168d251
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx39xxj.h
@@ -0,0 +1,40 @@
+/*
+ * Driver for Micronas DRX39xx family (drx3933j)
+ *
+ * Written by Devin Heitmueller <devin.heitmueller@kernellabs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
+ */
+
+#ifndef DRX39XXJ_H
+#define DRX39XXJ_H
+
+#include <linux/dvb/frontend.h>
+#include "dvb_frontend.h"
+#include "drx_driver.h"
+
+struct drx39xxj_state {
+ struct i2c_adapter *i2c;
+ DRXDemodInstance_t *demod;
+ DRXStandard_t current_standard;
+ struct dvb_frontend frontend;
+ int powered_up:1;
+ unsigned int i2c_gate_open:1;
+};
+
+extern struct dvb_frontend *drx39xxj_attach(struct i2c_adapter *i2c);
+
+#endif // DRX39XXJ_H
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 08/25] added drx39_dummy for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (6 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 07/25] added drx39xxj header " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 09/25] added drx_dap_fasi " Patrick Dickey
` (14 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drx39xxj_dummy.c | 135 ++++++++++++++++++++++++++
1 files changed, 135 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drx39xxj_dummy.c
diff --git a/drivers/media/dvb/frontends/drx39xxj_dummy.c b/drivers/media/dvb/frontends/drx39xxj_dummy.c
new file mode 100644
index 0000000..3ed2c39
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx39xxj_dummy.c
@@ -0,0 +1,135 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/jiffies.h>
+#include <linux/types.h>
+
+#include "drx_driver.h"
+#include "bsp_types.h"
+#include "bsp_tuner.h"
+#include "drx39xxj.h"
+
+/* Dummy function to satisfy drxj.c */
+DRXStatus_t DRXBSP_TUNER_Open(pTUNERInstance_t tuner)
+{
+ return DRX_STS_OK;
+}
+
+DRXStatus_t DRXBSP_TUNER_Close(pTUNERInstance_t tuner)
+{
+ return DRX_STS_OK;
+}
+
+DRXStatus_t DRXBSP_TUNER_SetFrequency(pTUNERInstance_t tuner,
+ TUNERMode_t mode,
+ DRXFrequency_t centerFrequency)
+{
+ return DRX_STS_OK;
+}
+
+DRXStatus_t
+DRXBSP_TUNER_GetFrequency(pTUNERInstance_t tuner,
+ TUNERMode_t mode,
+ pDRXFrequency_t RFfrequency,
+ pDRXFrequency_t IFfrequency)
+{
+ return DRX_STS_OK;
+}
+
+DRXStatus_t DRXBSP_HST_Sleep(u32_t n)
+{
+ msleep(n);
+ return DRX_STS_OK;
+}
+
+u32_t DRXBSP_HST_Clock(void)
+{
+ return jiffies_to_msecs(jiffies);
+}
+
+int DRXBSP_HST_Memcmp(void *s1, void *s2, u32_t n)
+{
+ return (memcmp(s1, s2, (size_t) n));
+}
+
+void* DRXBSP_HST_Memcpy(void *to, void *from, u32_t n)
+{
+ return (memcpy(to, from, (size_t) n));
+}
+
+DRXStatus_t DRXBSP_I2C_WriteRead(pI2CDeviceAddr_t wDevAddr,
+ u16_t wCount,
+ pu8_t wData,
+ pI2CDeviceAddr_t rDevAddr,
+ u16_t rCount,
+ pu8_t rData)
+{
+ struct drx39xxj_state *state;
+ struct i2c_msg msg[2];
+ unsigned int num_msgs;
+
+ if (wDevAddr == NULL) {
+ /* Read only */
+ state = rDevAddr->userData;
+ msg[0].addr = rDevAddr->i2cAddr >> 1;
+ msg[0].flags = I2C_M_RD;
+ msg[0].buf = rData;
+ msg[0].len = rCount;
+ num_msgs = 1;
+ } else if (rDevAddr == NULL) {
+ /* Write only */
+ state = wDevAddr->userData;
+ msg[0].addr = wDevAddr->i2cAddr >> 1;
+ msg[0].flags = 0;
+ msg[0].buf = wData;
+ msg[0].len = wCount;
+ num_msgs = 1;
+ } else {
+ /* Both write and read */
+ state = wDevAddr->userData;
+ msg[0].addr = wDevAddr->i2cAddr >> 1;
+ msg[0].flags = 0;
+ msg[0].buf = wData;
+ msg[0].len = wCount;
+ msg[1].addr = rDevAddr->i2cAddr >> 1;
+ msg[1].flags = I2C_M_RD;
+ msg[1].buf = rData;
+ msg[1].len = rCount;
+ num_msgs = 2;
+ }
+
+ if (state->i2c == NULL) {
+ printk("i2c was zero, aborting\n");
+ return 0;
+ }
+ if (i2c_transfer(state->i2c, msg, num_msgs) != num_msgs) {
+ printk(KERN_WARNING "drx3933: I2C write/read failed\n");
+ return -EREMOTEIO;
+ }
+
+ return DRX_STS_OK;
+
+#ifdef DJH_DEBUG
+
+ struct drx39xxj_state *state = wDevAddr->userData;
+
+ struct i2c_msg msg[2] = {
+ { .addr = wDevAddr->i2cAddr,
+ .flags = 0, .buf = wData, .len = wCount },
+ { .addr = rDevAddr->i2cAddr,
+ .flags = I2C_M_RD, .buf = rData, .len = rCount },
+ };
+
+ printk("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
+ wDevAddr->i2cAddr, state->i2c, wCount, rCount);
+
+ if (i2c_transfer(state->i2c, msg, 2) != 2) {
+ printk(KERN_WARNING "drx3933: I2C write/read failed\n");
+ return -EREMOTEIO;
+ }
+#endif
+ return 0;
+}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 09/25] added drx_dap_fasi for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (7 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 08/25] added drx39_dummy " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 10/25] added drx_dap_fasi header " Patrick Dickey
` (13 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drx_dap_fasi.c | 670 ++++++++++++++++++++++++++++
1 files changed, 670 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drx_dap_fasi.c
diff --git a/drivers/media/dvb/frontends/drx_dap_fasi.c b/drivers/media/dvb/frontends/drx_dap_fasi.c
new file mode 100644
index 0000000..f34641d
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx_dap_fasi.c
@@ -0,0 +1,670 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*******************************************************************************
+* FILENAME: $Id: drx_dap_fasi.c,v 1.7 2009/12/28 14:36:21 carlo Exp $
+*
+* DESCRIPTION:
+* Part of DRX driver.
+* Data access protocol: Fast Access Sequential Interface (fasi)
+* Fast access, because of short addressing format (16 instead of 32 bits addr)
+* Sequential, because of I2C.
+* These functions know how the chip's memory and registers are to be accessed,
+* but nothing more.
+*
+* These functions should not need adapting to a new platform.
+*
+* USAGE:
+* -
+*
+* NOTES:
+*
+*
+*******************************************************************************/
+
+#include "drx_dap_fasi.h"
+#include "bsp_host.h" /* for DRXBSP_HST_Memcpy() */
+
+/*============================================================================*/
+
+/* Function prototypes */
+static DRXStatus_t DRXDAP_FASI_WriteBlock (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ u16_t datasize, /* size of data */
+ pu8_t data, /* data to send */
+ DRXflags_t flags); /* special device flags */
+
+static DRXStatus_t DRXDAP_FASI_ReadBlock (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ u16_t datasize, /* size of data */
+ pu8_t data, /* data to send */
+ DRXflags_t flags); /* special device flags */
+
+static DRXStatus_t DRXDAP_FASI_WriteReg8 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register */
+ u8_t data, /* data to write */
+ DRXflags_t flags); /* special device flags */
+
+static DRXStatus_t DRXDAP_FASI_ReadReg8 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register */
+ pu8_t data, /* buffer to receive data */
+ DRXflags_t flags); /* special device flags */
+
+static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t waddr, /* address of register */
+ DRXaddr_t raddr, /* address to read back from */
+ u8_t datain, /* data to send */
+ pu8_t dataout); /* data to receive back */
+
+static DRXStatus_t DRXDAP_FASI_WriteReg16 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register */
+ u16_t data, /* data to write */
+ DRXflags_t flags); /* special device flags */
+
+static DRXStatus_t DRXDAP_FASI_ReadReg16 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register */
+ pu16_t data, /* buffer to receive data */
+ DRXflags_t flags); /* special device flags */
+
+static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t waddr, /* address of register */
+ DRXaddr_t raddr, /* address to read back from */
+ u16_t datain, /* data to send */
+ pu16_t dataout); /* data to receive back */
+
+static DRXStatus_t DRXDAP_FASI_WriteReg32 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register */
+ u32_t data, /* data to write */
+ DRXflags_t flags); /* special device flags */
+
+static DRXStatus_t DRXDAP_FASI_ReadReg32 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register */
+ pu32_t data, /* buffer to receive data */
+ DRXflags_t flags); /* special device flags */
+
+static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t waddr, /* address of register */
+ DRXaddr_t raddr, /* address to read back from */
+ u32_t datain, /* data to send */
+ pu32_t dataout); /* data to receive back */
+
+/* The version structure of this protocol implementation */
+char drxDapFASIModuleName[] = "FASI Data Access Protocol";
+char drxDapFASIVersionText[] = "";
+
+DRXVersion_t drxDapFASIVersion =
+{
+ DRX_MODULE_DAP, /**< type identifier of the module */
+ drxDapFASIModuleName, /**< name or description of module */
+
+ 0, /**< major version number */
+ 0, /**< minor version number */
+ 0, /**< patch version number */
+ drxDapFASIVersionText /**< version as text string */
+};
+
+/* The structure containing the protocol interface */
+DRXAccessFunc_t drxDapFASIFunct_g =
+{
+ &drxDapFASIVersion,
+ DRXDAP_FASI_WriteBlock, /* Supported */
+ DRXDAP_FASI_ReadBlock, /* Supported */
+ DRXDAP_FASI_WriteReg8, /* Not supported */
+ DRXDAP_FASI_ReadReg8, /* Not supported */
+ DRXDAP_FASI_ReadModifyWriteReg8, /* Not supported */
+ DRXDAP_FASI_WriteReg16, /* Supported */
+ DRXDAP_FASI_ReadReg16, /* Supported */
+ DRXDAP_FASI_ReadModifyWriteReg16, /* Supported */
+ DRXDAP_FASI_WriteReg32, /* Supported */
+ DRXDAP_FASI_ReadReg32, /* Supported */
+ DRXDAP_FASI_ReadModifyWriteReg32 /* Not supported */
+};
+
+/*============================================================================*/
+
+/* Functions not supported by protocol*/
+
+static DRXStatus_t DRXDAP_FASI_WriteReg8 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register */
+ u8_t data, /* data to write */
+ DRXflags_t flags) /* special device flags */
+{
+ return DRX_STS_ERROR;
+}
+
+static DRXStatus_t DRXDAP_FASI_ReadReg8 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register */
+ pu8_t data, /* buffer to receive data */
+ DRXflags_t flags) /* special device flags */
+{
+ return DRX_STS_ERROR;
+}
+
+static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg8 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t waddr, /* address of register */
+ DRXaddr_t raddr, /* address to read back from */
+ u8_t datain, /* data to send */
+ pu8_t dataout) /* data to receive back */
+{
+ return DRX_STS_ERROR;
+}
+
+static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg32 (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t waddr, /* address of register */
+ DRXaddr_t raddr, /* address to read back from */
+ u32_t datain, /* data to send */
+ pu32_t dataout) /* data to receive back */
+{
+ return DRX_STS_ERROR;
+}
+
+/*============================================================================*/
+
+/******************************
+*
+* DRXStatus_t DRXDAP_FASI_ReadBlock (
+* pI2CDeviceAddr_t devAddr, -- address of I2C device
+* DRXaddr_t addr, -- address of chip register/memory
+* u16_t datasize, -- number of bytes to read
+* pu8_t data, -- data to receive
+* DRXflags_t flags) -- special device flags
+*
+* Read block data from chip address. Because the chip is word oriented,
+* the number of bytes to read must be even.
+*
+* Make sure that the buffer to receive the data is large enough.
+*
+* Although this function expects an even number of bytes, it is still byte
+* oriented, and the data read back is NOT translated to the endianness of
+* the target platform.
+*
+* Output:
+* - DRX_STS_OK if reading was successful
+* in that case: data read is in *data.
+* - DRX_STS_ERROR if anything went wrong
+*
+******************************/
+
+static DRXStatus_t DRXDAP_FASI_ReadBlock (pI2CDeviceAddr_t devAddr,
+ DRXaddr_t addr,
+ u16_t datasize,
+ pu8_t data,
+ DRXflags_t flags)
+{
+ u8_t buf[4];
+ u16_t bufx;
+ DRXStatus_t rc;
+ u16_t overheadSize = 0;
+
+ /* Check parameters ********************************************************/
+ if (devAddr == NULL)
+ {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
+ (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
+
+ if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
+ ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
+ DRXDAP_FASI_LONG_FORMAT(addr)) ||
+ (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
+ ((datasize!=0) && (data==NULL)) ||
+ ((datasize & 1)==1))
+ {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ /* ReadModifyWrite & mode flag bits are not allowed */
+ flags &= (~DRXDAP_FASI_RMW & ~DRXDAP_FASI_MODEFLAGS);
+#if DRXDAP_SINGLE_MASTER
+ flags |= DRXDAP_FASI_SINGLE_MASTER;
+#endif
+
+ /* Read block from I2C *****************************************************/
+ do {
+ u16_t todo = (datasize < DRXDAP_MAX_RCHUNKSIZE ?
+ datasize : DRXDAP_MAX_RCHUNKSIZE);
+
+ bufx = 0;
+
+ addr &= ~DRXDAP_FASI_FLAGS;
+ addr |= flags;
+
+#if ((DRXDAPFASI_LONG_ADDR_ALLOWED==1) && \
+ (DRXDAPFASI_SHORT_ADDR_ALLOWED==1))
+ /* short format address preferred but long format otherwise */
+ if (DRXDAP_FASI_LONG_FORMAT(addr))
+ {
+#endif
+#if (DRXDAPFASI_LONG_ADDR_ALLOWED==1)
+ buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
+ buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
+ buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
+ buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
+#endif
+#if ((DRXDAPFASI_LONG_ADDR_ALLOWED==1) && \
+ (DRXDAPFASI_SHORT_ADDR_ALLOWED==1))
+ } else {
+#endif
+#if (DRXDAPFASI_SHORT_ADDR_ALLOWED==1)
+ buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
+ buf[bufx++] = (u8_t) (((addr >> 16) & 0x0F) | ((addr >> 18) & 0xF0));
+#endif
+#if ((DRXDAPFASI_LONG_ADDR_ALLOWED==1) && \
+ (DRXDAPFASI_SHORT_ADDR_ALLOWED==1))
+ }
+#endif
+
+
+
+
+#if DRXDAP_SINGLE_MASTER
+ /*
+ * In single master mode, split the read and write actions.
+ * No special action is needed for write chunks here.
+ */
+ rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, 0, 0, 0);
+ if (rc == DRX_STS_OK) {
+ rc = DRXBSP_I2C_WriteRead (0, 0, 0, devAddr, todo, data);
+ }
+#else
+ /* In multi master mode, do everything in one RW action */
+ rc = DRXBSP_I2C_WriteRead (devAddr, bufx, buf, devAddr, todo, data);
+#endif
+ data += todo;
+ addr += (todo >> 1);
+ datasize -= todo;
+ } while (datasize && rc == DRX_STS_OK);
+
+ return rc;
+}
+
+
+
+
+/******************************
+*
+* DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (
+* pI2CDeviceAddr_t devAddr, -- address of I2C device
+* DRXaddr_t waddr, -- address of chip register/memory
+* DRXaddr_t raddr, -- chip address to read back from
+* u16_t wdata, -- data to send
+* pu16_t rdata) -- data to receive back
+*
+* Write 16-bit data, then read back the original contents of that location.
+* Requires long addressing format to be allowed.
+*
+* Before sending data, the data is converted to little endian. The
+* data received back is converted back to the target platform's endianness.
+*
+* WARNING: This function is only guaranteed to work if there is one
+* master on the I2C bus.
+*
+* Output:
+* - DRX_STS_OK if reading was successful
+* in that case: read back data is at *rdata
+* - DRX_STS_ERROR if anything went wrong
+*
+******************************/
+
+static DRXStatus_t DRXDAP_FASI_ReadModifyWriteReg16 (pI2CDeviceAddr_t devAddr,
+ DRXaddr_t waddr,
+ DRXaddr_t raddr,
+ u16_t wdata,
+ pu16_t rdata)
+{
+ DRXStatus_t rc=DRX_STS_ERROR;
+
+#if (DRXDAPFASI_LONG_ADDR_ALLOWED==1)
+ if (rdata == NULL) {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ rc = DRXDAP_FASI_WriteReg16 (devAddr, waddr, wdata, DRXDAP_FASI_RMW);
+ if (rc == DRX_STS_OK) {
+ rc = DRXDAP_FASI_ReadReg16 (devAddr, raddr, rdata, 0);
+ }
+#endif
+
+ return rc;
+}
+
+
+
+
+/******************************
+*
+* DRXStatus_t DRXDAP_FASI_ReadReg16 (
+* pI2CDeviceAddr_t devAddr, -- address of I2C device
+* DRXaddr_t addr, -- address of chip register/memory
+* pu16_t data, -- data to receive
+* DRXflags_t flags) -- special device flags
+*
+* Read one 16-bit register or memory location. The data received back is
+* converted back to the target platform's endianness.
+*
+* Output:
+* - DRX_STS_OK if reading was successful
+* in that case: read data is at *data
+* - DRX_STS_ERROR if anything went wrong
+*
+******************************/
+
+static DRXStatus_t DRXDAP_FASI_ReadReg16 (pI2CDeviceAddr_t devAddr,
+ DRXaddr_t addr,
+ pu16_t data,
+ DRXflags_t flags)
+{
+ u8_t buf[sizeof (*data)];
+ DRXStatus_t rc;
+
+ if (!data) {
+ return DRX_STS_INVALID_ARG;
+ }
+ rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
+ *data = buf[0] + (((u16_t) buf[1]) << 8);
+ return rc;
+}
+
+
+
+
+/******************************
+*
+* DRXStatus_t DRXDAP_FASI_ReadReg32 (
+* pI2CDeviceAddr_t devAddr, -- address of I2C device
+* DRXaddr_t addr, -- address of chip register/memory
+* pu32_t data, -- data to receive
+* DRXflags_t flags) -- special device flags
+*
+* Read one 32-bit register or memory location. The data received back is
+* converted back to the target platform's endianness.
+*
+* Output:
+* - DRX_STS_OK if reading was successful
+* in that case: read data is at *data
+* - DRX_STS_ERROR if anything went wrong
+*
+******************************/
+
+static DRXStatus_t DRXDAP_FASI_ReadReg32 (pI2CDeviceAddr_t devAddr,
+ DRXaddr_t addr,
+ pu32_t data,
+ DRXflags_t flags)
+{
+ u8_t buf[sizeof (*data)];
+ DRXStatus_t rc;
+
+ if (!data) {
+ return DRX_STS_INVALID_ARG;
+ }
+ rc = DRXDAP_FASI_ReadBlock (devAddr, addr, sizeof (*data), buf, flags);
+ *data = (((u32_t) buf[0]) << 0) +
+ (((u32_t) buf[1]) << 8) +
+ (((u32_t) buf[2]) << 16) +
+ (((u32_t) buf[3]) << 24);
+ return rc;
+}
+
+
+
+
+/******************************
+*
+* DRXStatus_t DRXDAP_FASI_WriteBlock (
+* pI2CDeviceAddr_t devAddr, -- address of I2C device
+* DRXaddr_t addr, -- address of chip register/memory
+* u16_t datasize, -- number of bytes to read
+* pu8_t data, -- data to receive
+* DRXflags_t flags) -- special device flags
+*
+* Write block data to chip address. Because the chip is word oriented,
+* the number of bytes to write must be even.
+*
+* Although this function expects an even number of bytes, it is still byte
+* oriented, and the data being written is NOT translated from the endianness of
+* the target platform.
+*
+* Output:
+* - DRX_STS_OK if writing was successful
+* - DRX_STS_ERROR if anything went wrong
+*
+******************************/
+
+static DRXStatus_t DRXDAP_FASI_WriteBlock (pI2CDeviceAddr_t devAddr,
+ DRXaddr_t addr,
+ u16_t datasize,
+ pu8_t data,
+ DRXflags_t flags)
+{
+ u8_t buf[ DRXDAP_MAX_WCHUNKSIZE ];
+ DRXStatus_t st = DRX_STS_ERROR;
+ DRXStatus_t firstErr = DRX_STS_OK;
+ u16_t overheadSize = 0;
+ u16_t blockSize = 0;
+
+ /* Check parameters ********************************************************/
+ if (devAddr == NULL) {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ overheadSize = (IS_I2C_10BIT (devAddr->i2cAddr) ? 2 : 1) +
+ (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
+
+ if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
+ ((!(DRXDAPFASI_LONG_ADDR_ALLOWED)) &&
+ DRXDAP_FASI_LONG_FORMAT(addr)) ||
+ (overheadSize > (DRXDAP_MAX_WCHUNKSIZE)) ||
+ ((datasize!=0) && (data==NULL)) ||
+ ((datasize & 1)==1)) {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ flags &= DRXDAP_FASI_FLAGS;
+ flags &= ~DRXDAP_FASI_MODEFLAGS;
+#if DRXDAP_SINGLE_MASTER
+ flags |= DRXDAP_FASI_SINGLE_MASTER;
+#endif
+
+ /* Write block to I2C ******************************************************/
+ blockSize = ((DRXDAP_MAX_WCHUNKSIZE) - overheadSize) & ~1;
+ do
+ {
+ u16_t todo = 0;
+ u16_t bufx = 0;
+
+ /* Buffer device address */
+ addr &= ~DRXDAP_FASI_FLAGS;
+ addr |= flags;
+ #if (((DRXDAPFASI_LONG_ADDR_ALLOWED)==1) && \
+ ((DRXDAPFASI_SHORT_ADDR_ALLOWED)==1))
+ /* short format address preferred but long format otherwise */
+ if (DRXDAP_FASI_LONG_FORMAT(addr)) {
+ #endif
+ #if ((DRXDAPFASI_LONG_ADDR_ALLOWED)==1)
+ buf[bufx++] = (u8_t) (((addr << 1) & 0xFF)|0x01);
+ buf[bufx++] = (u8_t) ((addr >> 16) & 0xFF);
+ buf[bufx++] = (u8_t) ((addr >> 24) & 0xFF);
+ buf[bufx++] = (u8_t) ((addr >> 7) & 0xFF);
+ #endif
+ #if (((DRXDAPFASI_LONG_ADDR_ALLOWED)==1) && \
+ ((DRXDAPFASI_SHORT_ADDR_ALLOWED)==1))
+ } else {
+ #endif
+ #if ((DRXDAPFASI_SHORT_ADDR_ALLOWED)==1)
+ buf[bufx++] = (u8_t) ((addr << 1) & 0xFF);
+ buf[bufx++] = (u8_t) (((addr >> 16) & 0x0F) |
+ ((addr >> 18) & 0xF0));
+ #endif
+ #if (((DRXDAPFASI_LONG_ADDR_ALLOWED)==1) && \
+ ((DRXDAPFASI_SHORT_ADDR_ALLOWED)==1))
+ }
+ #endif
+
+ /*
+ In single master mode blockSize can be 0. In such a case this I2C
+ sequense will be visible: (1) write address {i2c addr,
+ 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
+ (3) write address (4) write data etc...
+ Addres must be rewriten because HI is reset after data transport and
+ expects an address.
+ */
+ todo = (blockSize < datasize ? blockSize : datasize);
+ if (todo==0) {
+ u16_t overheadSizeI2cAddr = 0;
+ u16_t dataBlockSize = 0;
+
+ overheadSizeI2cAddr = (IS_I2C_10BIT (devAddr->i2cAddr)
+ ? 2 : 1);
+ dataBlockSize = (DRXDAP_MAX_WCHUNKSIZE -
+ overheadSizeI2cAddr) & ~1;
+
+ /* write device address */
+ st = DRXBSP_I2C_WriteRead(devAddr,
+ (u16_t) (bufx),
+ buf,
+ (pI2CDeviceAddr_t)(NULL),
+ 0,
+ (pu8_t)(NULL));
+
+ if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) {
+ /* at the end, return the first error encountered */
+ firstErr = st;
+ }
+ bufx = 0;
+ todo = (dataBlockSize < datasize ? dataBlockSize :
+ datasize);
+ }
+ DRXBSP_HST_Memcpy (&buf[bufx], data, todo);
+ /* write (address if can do and) data */
+ st = DRXBSP_I2C_WriteRead(devAddr,
+ (u16_t)(bufx + todo),
+ buf,
+ (pI2CDeviceAddr_t)(NULL),
+ 0,
+ (pu8_t)(NULL));
+
+ if ((st != DRX_STS_OK) && (firstErr == DRX_STS_OK)) {
+ /* at the end, return the first error encountered */
+ firstErr = st;
+ }
+ datasize -= todo;
+ data += todo;
+ addr += (todo >> 1);
+ } while (datasize);
+
+ return firstErr;
+}
+
+
+
+
+/******************************
+*
+* DRXStatus_t DRXDAP_FASI_WriteReg16 (
+* pI2CDeviceAddr_t devAddr, -- address of I2C device
+* DRXaddr_t addr, -- address of chip register/memory
+* u16_t data, -- data to send
+* DRXflags_t flags) -- special device flags
+*
+* Write one 16-bit register or memory location. The data being written is
+* converted from the target platform's endianness to little endian.
+*
+* Output:
+* - DRX_STS_OK if writing was successful
+* - DRX_STS_ERROR if anything went wrong
+*
+******************************/
+
+static DRXStatus_t DRXDAP_FASI_WriteReg16 (pI2CDeviceAddr_t devAddr,
+ DRXaddr_t addr,
+ u16_t data,
+ DRXflags_t flags)
+{
+ u8_t buf[sizeof (data)];
+
+ buf[0] = (u8_t) ((data >> 0) & 0xFF);
+ buf[1] = (u8_t) ((data >> 8) & 0xFF);
+
+ return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf,
+ flags);
+}
+
+
+
+
+/******************************
+*
+* DRXStatus_t DRXDAP_FASI_WriteReg32 (
+* pI2CDeviceAddr_t devAddr, -- address of I2C device
+* DRXaddr_t addr, -- address of chip register/memory
+* u32_t data, -- data to send
+* DRXflags_t flags) -- special device flags
+*
+* Write one 32-bit register or memory location. The data being written is
+* converted from the target platform's endianness to little endian.
+*
+* Output:
+* - DRX_STS_OK if writing was successful
+* - DRX_STS_ERROR if anything went wrong
+*
+******************************/
+
+static DRXStatus_t DRXDAP_FASI_WriteReg32 (pI2CDeviceAddr_t devAddr,
+ DRXaddr_t addr,
+ u32_t data,
+ DRXflags_t flags)
+{
+ u8_t buf[sizeof (data)];
+
+ buf[0] = (u8_t) ((data >> 0) & 0xFF);
+ buf[1] = (u8_t) ((data >> 8) & 0xFF);
+ buf[2] = (u8_t) ((data >> 16) & 0xFF);
+ buf[3] = (u8_t) ((data >> 24) & 0xFF);
+
+ return DRXDAP_FASI_WriteBlock (devAddr, addr, sizeof (data), buf,
+ flags);
+}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 10/25] added drx_dap_fasi header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (8 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 09/25] added drx_dap_fasi " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 11/25] added drx_driver " Patrick Dickey
` (12 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drx_dap_fasi.h | 268 ++++++++++++++++++++++++++++
1 files changed, 268 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drx_dap_fasi.h
diff --git a/drivers/media/dvb/frontends/drx_dap_fasi.h b/drivers/media/dvb/frontends/drx_dap_fasi.h
new file mode 100644
index 0000000..b1c0eb6
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx_dap_fasi.h
@@ -0,0 +1,268 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*******************************************************************************
+* FILENAME: $Id: drx_dap_fasi.h,v 1.5 2009/07/07 14:21:40 justin Exp $
+*
+* DESCRIPTION:
+* Part of DRX driver.
+* Data access protocol: Fast Access Sequential Interface (fasi)
+* Fast access, because of short addressing format (16 instead of 32 bits addr)
+* Sequential, because of I2C.
+*
+* USAGE:
+* Include.
+*
+* NOTES:
+*
+*
+*******************************************************************************/
+
+/*-------- compilation control switches --------------------------------------*/
+
+#ifndef __DRX_DAP_FASI_H__
+#define __DRX_DAP_FASI_H__
+
+/*-------- Required includes -------------------------------------------------*/
+
+#include "drx_driver.h"
+
+/*-------- Defines, configuring the API --------------------------------------*/
+
+/********************************************
+* Allowed address formats
+********************************************/
+
+/*
+* Comments about short/long addressing format:
+*
+* The DAP FASI offers long address format (4 bytes) and short address format
+* (2 bytes). The DAP can operate in 3 modes:
+* (1) only short
+* (2) only long
+* (3) both long and short but short preferred and long only when necesarry
+*
+* These modes must be selected compile time via compile switches.
+* Compile switch settings for the diffrent modes:
+* (1) DRXDAPFASI_LONG_ADDR_ALLOWED=0, DRXDAPFASI_SHORT_ADDR_ALLOWED=1
+* (2) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=0
+* (3) DRXDAPFASI_LONG_ADDR_ALLOWED=1, DRXDAPFASI_SHORT_ADDR_ALLOWED=1
+*
+* The default setting will be (3) both long and short.
+* The default setting will need no compile switches.
+* The default setting must be overridden if compile switches are already
+* defined.
+*
+*/
+
+/* set default */
+#if !defined(DRXDAPFASI_LONG_ADDR_ALLOWED)
+#define DRXDAPFASI_LONG_ADDR_ALLOWED 1
+#endif
+
+/* set default */
+#if !defined(DRXDAPFASI_SHORT_ADDR_ALLOWED)
+#define DRXDAPFASI_SHORT_ADDR_ALLOWED 1
+#endif
+
+/* check */
+#if ((DRXDAPFASI_LONG_ADDR_ALLOWED==0) && \
+ (DRXDAPFASI_SHORT_ADDR_ALLOWED==0))
+#error At least one of short- or long-addressing format must be allowed.
+*; /* illegal statement to force compiler error */
+#endif
+
+
+/********************************************
+* Single/master multi master setting
+********************************************/
+/*
+* Comments about SINGLE MASTER/MULTI MASTER modes:
+*
+* Consider the two sides:1) the master and 2)the slave.
+*
+* Master:
+* Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch
+* + single master mode means no use of repeated starts
+* + multi master mode means use of repeated starts
+* Default is single master.
+* Default can be overriden by setting the compile switch DRXDAP_SINGLE_MASTER.
+*
+* Slave:
+* Single/multi master selected via the flags in the FASI protocol.
+* + single master means remember memory address between i2c packets
+* + multimaster means flush memory address between i2c packets
+* Default is single master, DAP FASI changes multi-master setting silently
+* into single master setting. This cannot be overrriden.
+*
+*/
+/* set default */
+#ifndef DRXDAP_SINGLE_MASTER
+#define DRXDAP_SINGLE_MASTER 0
+#endif
+
+/********************************************
+* Chunk/mode checking
+********************************************/
+/*
+* Comments about DRXDAP_MAX_WCHUNKSIZE in single or multi master mode and
+* in combination with short and long addressing format. All text below
+* assumes long addressing format. The table also includes information
+* for short ADDRessing format.
+*
+* In single master mode, data can be written by sending the register address
+* first, then two or four bytes of data in the next packet.
+* Because the device address plus a register address equals five bytes,
+* the mimimum chunk size must be five.
+* If ten-bit I2C device addresses are used, the minimum chunk size must be six,
+* because the I2C device address will then occupy two bytes when writing.
+*
+* Data in single master mode is transferred as follows:
+* <S> <devW> a0 a1 a2 a3 <P>
+* <S> <devW> d0 d1 [d2 d3] <P>
+* ..
+* or
+* ..
+* <S> <devW> a0 a1 a2 a3 <P>
+* <S> <devR> --- <P>
+*
+* In multi-master mode, the data must immediately follow the address (an I2C
+* stop resets the internal address), and hence the minimum chunk size is
+* 1 <I2C address> + 4 (register address) + 2 (data to send) = 7 bytes (8 if
+* 10-bit I2C device addresses are used).
+*
+* The 7-bit or 10-bit i2c address parameters is a runtime parameter.
+* The other parameters can be limited via compile time switches.
+*
+*-------------------------------------------------------------------------------
+*
+* Minimum chunk size table (in bytes):
+*
+* +----------------+----------------+
+* | 7b i2c addr | 10b i2c addr |
+* +----------------+----------------+
+* | single | multi | single | multi |
+* ------+--------+-------+--------+-------+
+* short | 3 | 5 | 4 | 6 |
+* long | 5 | 7 | 6 | 8 |
+* ------+--------+-------+--------+-------+
+*
+*/
+
+/* set default */
+#if !defined(DRXDAP_MAX_WCHUNKSIZE)
+#define DRXDAP_MAX_WCHUNKSIZE 254
+#endif
+
+/* check */
+#if ((DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1))
+#if DRXDAP_SINGLE_MASTER
+#define DRXDAP_MAX_WCHUNKSIZE_MIN 3
+#else
+#define DRXDAP_MAX_WCHUNKSIZE_MIN 5
+#endif
+#else
+#if DRXDAP_SINGLE_MASTER
+#define DRXDAP_MAX_WCHUNKSIZE_MIN 5
+#else
+#define DRXDAP_MAX_WCHUNKSIZE_MIN 7
+#endif
+#endif
+
+#if DRXDAP_MAX_WCHUNKSIZE < DRXDAP_MAX_WCHUNKSIZE_MIN
+#if ((DRXDAPFASI_LONG_ADDR_ALLOWED==0)&&(DRXDAPFASI_SHORT_ADDR_ALLOWED==1))
+#if DRXDAP_SINGLE_MASTER
+#error DRXDAP_MAX_WCHUNKSIZE must be at least 3 in single master mode
+*; /* illegal statement to force compiler error */
+#else
+#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in multi master mode
+*; /* illegal statement to force compiler error */
+#endif
+#else
+#if DRXDAP_SINGLE_MASTER
+#error DRXDAP_MAX_WCHUNKSIZE must be at least 5 in single master mode
+*; /* illegal statement to force compiler error */
+#else
+#error DRXDAP_MAX_WCHUNKSIZE must be at least 7 in multi master mode
+*; /* illegal statement to force compiler error */
+#endif
+#endif
+#endif
+
+/* set default */
+#if !defined(DRXDAP_MAX_RCHUNKSIZE)
+#define DRXDAP_MAX_RCHUNKSIZE 254
+#endif
+
+/* check */
+#if DRXDAP_MAX_RCHUNKSIZE < 2
+#error DRXDAP_MAX_RCHUNKSIZE must be at least 2
+*; /* illegal statement to force compiler error */
+#endif
+
+/* check */
+#if DRXDAP_MAX_RCHUNKSIZE & 1
+#error DRXDAP_MAX_RCHUNKSIZE must be even
+*; /* illegal statement to force compiler error */
+#endif
+
+/*-------- Public API functions ----------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+extern DRXAccessFunc_t drxDapFASIFunct_g;
+
+#define DRXDAP_FASI_RMW 0x10000000
+#define DRXDAP_FASI_BROADCAST 0x20000000
+#define DRXDAP_FASI_CLEARCRC 0x80000000
+#define DRXDAP_FASI_SINGLE_MASTER 0xC0000000
+#define DRXDAP_FASI_MULTI_MASTER 0x40000000
+#define DRXDAP_FASI_SMM_SWITCH 0x40000000 /* single/multi master switch */
+#define DRXDAP_FASI_MODEFLAGS 0xC0000000
+#define DRXDAP_FASI_FLAGS 0xF0000000
+
+#define DRXDAP_FASI_ADDR2BLOCK(addr) (((addr)>>22)&0x3F)
+#define DRXDAP_FASI_ADDR2BANK(addr) (((addr)>>16)&0x3F)
+#define DRXDAP_FASI_ADDR2OFFSET(addr) ((addr)&0x7FFF)
+
+#define DRXDAP_FASI_SHORT_FORMAT(addr) (((addr)& 0xFC30FF80)==0)
+#define DRXDAP_FASI_LONG_FORMAT(addr) (((addr)& 0xFC30FF80)!=0)
+#define DRXDAP_FASI_OFFSET_TOO_LARGE(addr) (((addr)& 0x00008000)!=0)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __DRX_DAP_FASI_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 11/25] added drx_driver for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (9 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 10/25] added drx_dap_fasi header " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 12/25] added drx_driver header " Patrick Dickey
` (11 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drx_driver.c | 1504 ++++++++++++++++++++++++++++++
1 files changed, 1504 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drx_driver.c
diff --git a/drivers/media/dvb/frontends/drx_driver.c b/drivers/media/dvb/frontends/drx_driver.c
new file mode 100644
index 0000000..1f58de7
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx_driver.c
@@ -0,0 +1,1504 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/**
+* \file $Id: drx_driver.c,v 1.40 2010/01/12 01:24:56 lfeng Exp $
+*
+* \brief Generic DRX functionality, DRX driver core.
+*
+*/
+
+/*------------------------------------------------------------------------------
+INCLUDE FILES
+------------------------------------------------------------------------------*/
+#include "drx_driver.h"
+#include "bsp_host.h"
+
+#define VERSION_FIXED 0
+#if VERSION_FIXED
+#define VERSION_MAJOR 0
+#define VERSION_MINOR 0
+#define VERSION_PATCH 0
+#else
+#include "drx_driver_version.h"
+#endif
+
+/*------------------------------------------------------------------------------
+DEFINES
+------------------------------------------------------------------------------*/
+
+/*============================================================================*/
+/*=== MICROCODE RELATED DEFINES ==============================================*/
+/*============================================================================*/
+
+/** \brief Magic word for checking correct Endianess of microcode data. */
+#ifndef DRX_UCODE_MAGIC_WORD
+#define DRX_UCODE_MAGIC_WORD ((((u16_t)'H')<<8)+((u16_t)'L'))
+#endif
+
+/** \brief CRC flag in ucode header, flags field. */
+#ifndef DRX_UCODE_CRC_FLAG
+#define DRX_UCODE_CRC_FLAG (0x0001)
+#endif
+
+/** \brief Compression flag in ucode header, flags field. */
+#ifndef DRX_UCODE_COMPRESSION_FLAG
+#define DRX_UCODE_COMPRESSION_FLAG (0x0002)
+#endif
+
+/** \brief Maximum size of buffer used to verify the microcode.
+ Must be an even number. */
+#ifndef DRX_UCODE_MAX_BUF_SIZE
+#define DRX_UCODE_MAX_BUF_SIZE (DRXDAP_MAX_RCHUNKSIZE)
+#endif
+#if DRX_UCODE_MAX_BUF_SIZE & 1
+#error DRX_UCODE_MAX_BUF_SIZE must be an even number
+#endif
+
+/*============================================================================*/
+/*=== CHANNEL SCAN RELATED DEFINES ===========================================*/
+/*============================================================================*/
+
+/**
+* \brief Maximum progress indication.
+*
+* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan.
+*
+*/
+#ifndef DRX_SCAN_MAX_PROGRESS
+#define DRX_SCAN_MAX_PROGRESS 1000
+#endif
+
+/*============================================================================*/
+/*=== MACROS =================================================================*/
+/*============================================================================*/
+
+#define DRX_ISPOWERDOWNMODE(mode) ((mode == DRX_POWER_MODE_9) || \
+ (mode == DRX_POWER_MODE_10) || \
+ (mode == DRX_POWER_MODE_11) || \
+ (mode == DRX_POWER_MODE_12) || \
+ (mode == DRX_POWER_MODE_13) || \
+ (mode == DRX_POWER_MODE_14) || \
+ (mode == DRX_POWER_MODE_15) || \
+ (mode == DRX_POWER_MODE_16) || \
+ (mode == DRX_POWER_DOWN))
+
+/*------------------------------------------------------------------------------
+GLOBAL VARIABLES
+------------------------------------------------------------------------------*/
+
+/*------------------------------------------------------------------------------
+STRUCTURES
+------------------------------------------------------------------------------*/
+/** \brief Structure of the microcode block headers */
+typedef struct {
+ u32_t addr; /**< Destination address of the data in this block */
+ u16_t size; /**< Size of the block data following this header counted in
+ 16 bits words */
+ u16_t flags; /**< Flags for this data block:
+ - bit[0]= CRC on/off
+ - bit[1]= compression on/off
+ - bit[15..2]=reserved */
+ u16_t CRC; /**< CRC value of the data block, only valid if CRC flag is
+ set. */
+} DRXUCodeBlockHdr_t, *pDRXUCodeBlockHdr_t;
+
+/*------------------------------------------------------------------------------
+FUNCTIONS
+------------------------------------------------------------------------------*/
+
+/*============================================================================*/
+/*============================================================================*/
+/*== Channel Scan Functions ==================================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+#ifndef DRX_EXCLUDE_SCAN
+
+/* Prototype of default scanning function */
+static DRXStatus_t
+ScanFunctionDefault(void *scanContext,
+ DRXScanCommand_t scanCommand,
+ pDRXChannel_t scanChannel,
+ pBool_t getNextChannel);
+
+/**
+* \brief Get pointer to scanning function.
+* \param demod: Pointer to demodulator instance.
+* \return DRXScanFunc_t.
+*/
+static DRXScanFunc_t
+GetScanFunction(pDRXDemodInstance_t demod)
+{
+ pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
+ DRXScanFunc_t scanFunc = (DRXScanFunc_t)(NULL);
+
+ /* get scan function from common attributes */
+ commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
+ scanFunc = commonAttr->scanFunction;
+
+ if (scanFunc != NULL) {
+ /* return device-specific scan function if it's not NULL */
+ return scanFunc;
+ }
+ /* otherwise return default scan function in core driver */
+ return &ScanFunctionDefault;
+}
+
+/**
+* \brief Get Context pointer.
+* \param demod: Pointer to demodulator instance.
+* \param scanContext: Context Pointer.
+* \return DRXScanFunc_t.
+*/
+void *GetScanContext(pDRXDemodInstance_t demod,
+ void *scanContext)
+{
+ pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
+
+ /* get scan function from common attributes */
+ commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
+ scanContext = commonAttr->scanContext;
+
+ if (scanContext == NULL) {
+ scanContext = (void *) demod;
+ }
+
+ return scanContext;
+}
+
+/**
+* \brief Wait for lock while scanning.
+* \param demod: Pointer to demodulator instance.
+* \param lockStat: Pointer to bool indicating if end result is lock or not.
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Success
+* \retval DRX_STS_ERROR: I2C failure or bsp function failure.
+*
+* Wait until timeout, desired lock or NEVER_LOCK.
+* Assume:
+* - lock function returns : at least DRX_NOT_LOCKED and a lock state
+* higher than DRX_NOT_LOCKED.
+* - BSP has a clock function to retrieve a millisecond ticker value.
+* - BSP has a sleep function to enable sleep of n millisecond.
+*
+* In case DRX_NEVER_LOCK is returned the poll-wait will be aborted.
+*
+*/
+static DRXStatus_t
+ScanWaitForLock(pDRXDemodInstance_t demod,
+ pBool_t isLocked)
+{
+ Bool_t doneWaiting = FALSE;
+ DRXLockStatus_t lockState = DRX_NOT_LOCKED;
+ DRXLockStatus_t desiredLockState = DRX_NOT_LOCKED;
+ u32_t timeoutValue = 0;
+ u32_t startTimeLockStage = 0;
+ u32_t currentTime = 0;
+ u32_t timerValue = 0;
+
+ *isLocked = FALSE;
+ timeoutValue = (u32_t) demod->myCommonAttr->scanDemodLockTimeout;
+ desiredLockState = demod->myCommonAttr->scanDesiredLock;
+ startTimeLockStage = DRXBSP_HST_Clock();
+
+ /* Start polling loop, checking for lock & timeout */
+ while (doneWaiting == FALSE)
+ {
+
+ if (DRX_Ctrl(demod, DRX_CTRL_LOCK_STATUS, &lockState) !=
+ DRX_STS_OK) {
+ return DRX_STS_ERROR;
+ }
+ currentTime = DRXBSP_HST_Clock();
+
+ timerValue = currentTime - startTimeLockStage;
+ if (lockState >= desiredLockState) {
+ *isLocked = TRUE;
+ doneWaiting = TRUE;
+ } /* if (lockState >= desiredLockState) .. */
+ else if (lockState == DRX_NEVER_LOCK) {
+ doneWaiting = TRUE;
+ } /* if (lockState == DRX_NEVER_LOCK) .. */
+ else if (timerValue > timeoutValue) {
+ /* lockState == DRX_NOT_LOCKED and timeout */
+ doneWaiting = TRUE;
+ }
+ else {
+ if (DRXBSP_HST_Sleep(10) != DRX_STS_OK) {
+ return DRX_STS_ERROR;
+ }
+ } /* if (timerValue > timeoutValue) .. */
+
+ } /* while */
+
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Determine next frequency to scan.
+* \param demod: Pointer to demodulator instance.
+* \param skip : Minimum frequency step to take.
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Succes.
+* \retval DRX_STS_INVALID_ARG: Invalid frequency plan.
+*
+* Helper function for CtrlScanNext() function.
+* Compute next frequency & index in frequency plan.
+* Check if scan is ready.
+*
+*/
+static DRXStatus_t
+ScanPrepareNextScan (pDRXDemodInstance_t demod,
+ DRXFrequency_t skip)
+{
+ pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
+ u16_t tableIndex = 0;
+ u16_t frequencyPlanSize = 0;
+ pDRXFrequencyPlan_t frequencyPlan = (pDRXFrequencyPlan_t)(NULL);
+ DRXFrequency_t nextFrequency = 0;
+ DRXFrequency_t tunerMinFrequency = 0;
+ DRXFrequency_t tunerMaxFrequency = 0;
+
+ commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
+ tableIndex = commonAttr->scanFreqPlanIndex;
+ frequencyPlan = commonAttr->scanParam->frequencyPlan;
+ nextFrequency = commonAttr->scanNextFrequency;
+ tunerMinFrequency = commonAttr->tunerMinFreqRF;
+ tunerMaxFrequency = commonAttr->tunerMaxFreqRF;
+
+ do
+ {
+ /* Search next frequency to scan */
+
+ /* always take at least one step */
+ (commonAttr->scanChannelsScanned) ++;
+ nextFrequency += frequencyPlan[tableIndex].step;
+ skip -= frequencyPlan[tableIndex].step;
+
+ /* and then as many steps necessary to exceed 'skip'
+ without exceeding end of the band */
+ while ((skip > 0) &&
+ (nextFrequency <= frequencyPlan[tableIndex].last))
+ {
+ (commonAttr->scanChannelsScanned) ++;
+ nextFrequency += frequencyPlan[tableIndex].step;
+ skip -= frequencyPlan[tableIndex].step;
+ }
+ /* reset skip, in case we move to the next band later */
+ skip = 0;
+
+ if (nextFrequency > frequencyPlan[tableIndex].last) {
+ /* reached end of this band */
+ tableIndex++;
+ frequencyPlanSize = commonAttr->scanParam->frequencyPlanSize;
+ if (tableIndex >= frequencyPlanSize) {
+ /* reached end of frequency plan */
+ commonAttr->scanReady = TRUE;
+ }
+ else {
+ nextFrequency = frequencyPlan[tableIndex].first;
+ }
+ }
+ if (nextFrequency > (tunerMaxFrequency)) {
+ /* reached end of tuner range */
+ commonAttr->scanReady = TRUE;
+ }
+ } while((nextFrequency < tunerMinFrequency) &&
+ (commonAttr->scanReady == FALSE));
+
+ /* Store new values */
+ commonAttr->scanFreqPlanIndex = tableIndex;
+ commonAttr->scanNextFrequency = nextFrequency;
+
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Default DTV scanning function.
+*
+* \param demod: Pointer to demodulator instance.
+* \param scanCommand: Scanning command: INIT, NEXT or STOP.
+* \param scanChannel: Channel to check: frequency and bandwidth, others AUTO
+* \param getNextChannel: Return TRUE if next frequency is desired at next call
+*
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used
+* to retrieve channel parameters.
+* \retval DRX_STS_BUSY: Channel not found (yet).
+* \retval DRX_STS_ERROR: Something went wrong.
+*
+* scanChannel and getNextChannel will be NULL for INIT and STOP.
+*/
+static DRXStatus_t
+ScanFunctionDefault (void *scanContext,
+ DRXScanCommand_t scanCommand,
+ pDRXChannel_t scanChannel,
+ pBool_t getNextChannel)
+{
+ pDRXDemodInstance_t demod = NULL;
+ DRXStatus_t status = DRX_STS_ERROR;
+ Bool_t isLocked = FALSE;
+
+ demod = (pDRXDemodInstance_t) scanContext;
+
+ if (scanCommand != DRX_SCAN_COMMAND_NEXT) {
+ /* just return OK if not doing "scan next" */
+ return DRX_STS_OK;
+ }
+
+ *getNextChannel = FALSE;
+
+ status = DRX_Ctrl (demod, DRX_CTRL_SET_CHANNEL, scanChannel);
+ if (status != DRX_STS_OK) {
+ return (status);
+ }
+
+ status = ScanWaitForLock (demod, &isLocked);
+ if (status != DRX_STS_OK) {
+ return status;
+ }
+
+ /* done with this channel, move to next one */
+ *getNextChannel = TRUE;
+
+ if (isLocked == FALSE) {
+ /* no channel found */
+ return DRX_STS_BUSY;
+ }
+ /* channel found */
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Initialize for channel scan.
+* \param demod: Pointer to demodulator instance.
+* \param scanParam: Pointer to scan parameters.
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Initialized for scan.
+* \retval DRX_STS_ERROR: No overlap between frequency plan and tuner
+* range.
+* \retval DRX_STS_INVALID_ARG: Wrong parameters.
+*
+* This function should be called before starting a complete channel scan.
+* It will prepare everything for a complete channel scan.
+* After calling this function the DRX_CTRL_SCAN_NEXT control function can be
+* used to perform the actual scanning. Scanning will start at the first
+* center frequency of the frequency plan that is within the tuner range.
+*
+*/
+static DRXStatus_t
+CtrlScanInit(pDRXDemodInstance_t demod,
+ pDRXScanParam_t scanParam)
+{
+ DRXStatus_t status = DRX_STS_ERROR;
+ pDRXCommonAttr_t commonAttr =(pDRXCommonAttr_t)(NULL);
+ DRXFrequency_t maxTunerFreq = 0;
+ DRXFrequency_t minTunerFreq = 0;
+ u16_t nrChannelsInPlan = 0;
+ u16_t i = 0;
+ void *scanContext = NULL;
+
+ commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
+ commonAttr->scanActive = TRUE;
+
+ /* invalidate a previous SCAN_INIT */
+ commonAttr->scanParam = (pDRXScanParam_t)(NULL);
+ commonAttr->scanNextFrequency = 0;
+
+ /* Check parameters */
+ if (((demod->myTuner == NULL) &&
+ (scanParam->numTries !=1)) ||
+
+ (scanParam == NULL) ||
+ (scanParam->numTries == 0) ||
+ (scanParam->frequencyPlan == NULL) ||
+ (scanParam->frequencyPlanSize == 0)
+ ) {
+ commonAttr->scanActive = FALSE;
+ return DRX_STS_INVALID_ARG;
+ }
+
+ /* Check frequency plan contents */
+ maxTunerFreq = commonAttr->tunerMaxFreqRF;
+ minTunerFreq = commonAttr->tunerMinFreqRF;
+ for(i = 0; i < (scanParam->frequencyPlanSize); i++) {
+ DRXFrequency_t width = 0;
+ DRXFrequency_t step = scanParam->frequencyPlan[i].step;
+ DRXFrequency_t firstFreq = scanParam->frequencyPlan[i].first;
+ DRXFrequency_t lastFreq = scanParam->frequencyPlan[i].last;
+ DRXFrequency_t minFreq = 0;
+ DRXFrequency_t maxFreq = 0;
+
+ if (step <= 0) {
+ /* Step must be positive and non-zero */
+ commonAttr->scanActive = FALSE;
+ return DRX_STS_INVALID_ARG;
+ }
+
+ if (firstFreq > lastFreq) {
+ /* First center frequency is higher than last center frequency */
+ commonAttr->scanActive = FALSE;
+ return DRX_STS_INVALID_ARG;
+ }
+
+ width = lastFreq - firstFreq;
+
+ if ((width % step) != 0) {
+ /* Difference between last and first center frequency is not
+ an integer number of steps */
+ commonAttr->scanActive = FALSE;
+ return DRX_STS_INVALID_ARG;
+ }
+
+ /* Check if frequency plan entry intersects with tuner range */
+ if (lastFreq >= minTunerFreq) {
+ if (firstFreq <= maxTunerFreq) {
+ if (firstFreq >= minTunerFreq) {
+ minFreq = firstFreq;
+ }
+ else {
+ DRXFrequency_t n = 0;
+
+ n = (minTunerFreq - firstFreq) / step;
+ if (((minTunerFreq - firstFreq) % step) != 0) {
+ n++;
+ }
+ minFreq = firstFreq + n*step;
+ }
+
+ if (lastFreq <= maxTunerFreq) {
+ maxFreq = lastFreq;
+ }
+ else {
+ DRXFrequency_t n=0;
+
+ n=(lastFreq - maxTunerFreq)/step;
+ if (((lastFreq - maxTunerFreq)%step) !=0) {
+ n++;
+ }
+ maxFreq = lastFreq - n*step;
+ }
+ }
+ }
+
+ /* Keep track of total number of channels within tuner range
+ in this frequency plan. */
+ if ((minFreq !=0) && (maxFreq != 0)) {
+ nrChannelsInPlan += (u16_t)(((maxFreq-minFreq) / step) +1);
+
+ /* Determine first frequency (within tuner range) to scan */
+ if (commonAttr->scanNextFrequency == 0) {
+ commonAttr->scanNextFrequency = minFreq;
+ commonAttr->scanFreqPlanIndex = i;
+ }
+ }
+
+ }/* for (...) */
+
+ if (nrChannelsInPlan == 0) {
+ /* Tuner range and frequency plan ranges do not overlap */
+ commonAttr->scanActive = FALSE;
+ return DRX_STS_ERROR;
+ }
+
+ /* Store parameters */
+ commonAttr->scanReady = FALSE;
+ commonAttr->scanMaxChannels = nrChannelsInPlan;
+ commonAttr->scanChannelsScanned = 0;
+ commonAttr->scanParam = scanParam; /* SCAN_NEXT is now allowed */
+
+ scanContext = GetScanContext(demod, scanContext);
+
+ status = (*(GetScanFunction(demod)))
+ (scanContext, DRX_SCAN_COMMAND_INIT, NULL, NULL);
+
+ commonAttr->scanActive = FALSE;
+
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Stop scanning.
+* \param demod: Pointer to demodulator instance.
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Scan stopped.
+* \retval DRX_STS_ERROR: Something went wrong.
+* \retval DRX_STS_INVALID_ARG: Wrong parameters.
+*/
+static DRXStatus_t
+CtrlScanStop(pDRXDemodInstance_t demod)
+{
+ DRXStatus_t status = DRX_STS_ERROR;
+ pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t) (NULL);
+ void *scanContext = NULL;
+
+ commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
+ commonAttr->scanActive = TRUE;
+
+ if ((commonAttr->scanParam == NULL) ||
+ (commonAttr->scanMaxChannels == 0)) {
+ /* Scan was not running, just return OK */
+ commonAttr->scanActive = FALSE;
+ return DRX_STS_OK;
+ }
+
+ /* Call default or device-specific scanning stop function */
+ scanContext = GetScanContext(demod, scanContext);
+
+ status = (*(GetScanFunction(demod)))
+ (scanContext, DRX_SCAN_COMMAND_STOP, NULL, NULL);
+
+ /* All done, invalidate scan-init */
+ commonAttr->scanParam = NULL;
+ commonAttr->scanMaxChannels = 0;
+ commonAttr->scanActive = FALSE;
+
+ return status;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Scan for next channel.
+* \param demod: Pointer to demodulator instance.
+* \param scanProgress: Pointer to scan progress.
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Channel found, DRX_CTRL_GET_CHANNEL can be used
+* to retrieve channel parameters.
+* \retval DRX_STS_BUSY: Tried part of the channels, as specified in
+* numTries field of scan parameters. At least one
+* more call to DRX_CTRL_SCAN_NEXT is needed to
+* complete scanning.
+* \retval DRX_STS_READY: Reached end of scan range.
+* \retval DRX_STS_ERROR: Something went wrong.
+* \retval DRX_STS_INVALID_ARG: Wrong parameters. The scanProgress may be NULL.
+*
+* Progress indication will run from 0 upto DRX_SCAN_MAX_PROGRESS during scan.
+*
+*/
+static DRXStatus_t
+CtrlScanNext (pDRXDemodInstance_t demod,
+ pu16_t scanProgress)
+{
+ pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
+ pBool_t scanReady = (pBool_t)(NULL);
+ u16_t maxProgress = DRX_SCAN_MAX_PROGRESS;
+ u32_t numTries = 0;
+ u32_t i = 0;
+
+ commonAttr = (pDRXCommonAttr_t)demod->myCommonAttr;
+
+ /* Check scan parameters */
+ if (scanProgress == NULL) {
+ commonAttr->scanActive = FALSE;
+ return DRX_STS_INVALID_ARG;
+ }
+
+ *scanProgress = 0;
+ commonAttr->scanActive = TRUE;
+ if ((commonAttr->scanParam == NULL) ||
+ (commonAttr->scanMaxChannels == 0)) {
+ /* CtrlScanInit() was not called succesfully before CtrlScanNext() */
+ commonAttr->scanActive = FALSE;
+ return DRX_STS_ERROR;
+ }
+
+ *scanProgress = (u16_t)(((commonAttr->scanChannelsScanned)*
+ ((u32_t)(maxProgress))) /
+ (commonAttr->scanMaxChannels));
+
+ /* Scan */
+ numTries = commonAttr->scanParam->numTries;
+ scanReady = &(commonAttr->scanReady);
+
+ for (i = 0; ((i < numTries) && ((*scanReady) == FALSE)); i++) {
+ DRXChannel_t scanChannel = { 0 };
+ DRXStatus_t status = DRX_STS_ERROR;
+ pDRXFrequencyPlan_t freqPlan = (pDRXFrequencyPlan_t) (NULL);
+ Bool_t nextChannel = FALSE;
+ void *scanContext = NULL;
+
+ /* Next channel to scan */
+ freqPlan =
+ &(commonAttr->scanParam->frequencyPlan[commonAttr->scanFreqPlanIndex]);
+ scanChannel.frequency = commonAttr->scanNextFrequency;
+ scanChannel.bandwidth = freqPlan->bandwidth;
+ scanChannel.mirror = DRX_MIRROR_AUTO;
+ scanChannel.constellation = DRX_CONSTELLATION_AUTO;
+ scanChannel.hierarchy = DRX_HIERARCHY_AUTO;
+ scanChannel.priority = DRX_PRIORITY_HIGH;
+ scanChannel.coderate = DRX_CODERATE_AUTO;
+ scanChannel.guard = DRX_GUARD_AUTO;
+ scanChannel.fftmode = DRX_FFTMODE_AUTO;
+ scanChannel.classification = DRX_CLASSIFICATION_AUTO;
+ scanChannel.symbolrate = 0;
+ scanChannel.interleavemode = DRX_INTERLEAVEMODE_AUTO;
+ scanChannel.ldpc = DRX_LDPC_AUTO;
+ scanChannel.carrier = DRX_CARRIER_AUTO;
+ scanChannel.framemode = DRX_FRAMEMODE_AUTO;
+ scanChannel.pilot = DRX_PILOT_AUTO;
+
+ /* Call default or device-specific scanning function */
+ scanContext = GetScanContext(demod, scanContext);
+
+ status = (*(GetScanFunction(demod)))
+ (scanContext,DRX_SCAN_COMMAND_NEXT,&scanChannel,&nextChannel);
+
+ /* Proceed to next channel if requested */
+ if (nextChannel == TRUE) {
+ DRXStatus_t nextStatus = DRX_STS_ERROR;
+ DRXFrequency_t skip = 0;
+
+ if (status == DRX_STS_OK) {
+ /* a channel was found, so skip some frequency steps */
+ skip = commonAttr->scanParam->skip;
+ }
+ nextStatus = ScanPrepareNextScan(demod, skip);
+
+ /* keep track of progress */
+ *scanProgress = (u16_t)(((commonAttr->scanChannelsScanned)*
+ ((u32_t)(maxProgress)))/
+ (commonAttr->scanMaxChannels));
+
+ if (nextStatus != DRX_STS_OK) {
+ commonAttr->scanActive = FALSE;
+ return (nextStatus);
+ }
+ }
+ if (status != DRX_STS_BUSY) {
+ /* channel found or error */
+ commonAttr->scanActive = FALSE;
+ return status;
+ }
+ } /* for (i = 0; i < (... numTries); i++) */
+
+ if ((*scanReady) == TRUE) {
+ /* End of scan reached: call stop-scan, ignore any error */
+ CtrlScanStop(demod);
+ commonAttr->scanActive = FALSE;
+ return (DRX_STS_READY);
+ }
+
+ commonAttr->scanActive = FALSE;
+
+ return DRX_STS_BUSY;
+}
+
+#endif /* #ifndef DRX_EXCLUDE_SCAN */
+
+/*============================================================================*/
+
+/**
+* \brief Program tuner.
+* \param demod: Pointer to demodulator instance.
+* \param tunerChannel: Pointer to tuning parameters.
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Tuner programmed successfully.
+* \retval DRX_STS_ERROR: Something went wrong.
+* \retval DRX_STS_INVALID_ARG: Wrong parameters.
+*
+* tunerChannel passes parameters to program the tuner,
+* but also returns the actual RF and IF frequency from the tuner.
+*
+*/
+static DRXStatus_t
+CtrlProgramTuner(pDRXDemodInstance_t demod,
+ pDRXChannel_t channel)
+{
+ pDRXCommonAttr_t commonAttr = (pDRXCommonAttr_t)(NULL);
+ DRXStandard_t standard = DRX_STANDARD_UNKNOWN;
+ TUNERMode_t tunerMode = 0;
+ DRXStatus_t status = DRX_STS_ERROR;
+ DRXFrequency_t ifFrequency = 0;
+ Bool_t tunerSlowMode = FALSE;
+
+ /* can't tune without a tuner */
+ if (demod->myTuner == NULL) {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ commonAttr = (pDRXCommonAttr_t) demod->myCommonAttr;
+
+ /* select analog or digital tuner mode based on current standard */
+ if (DRX_Ctrl(demod, DRX_CTRL_GET_STANDARD, &standard) != DRX_STS_OK) {
+ return DRX_STS_ERROR;
+ }
+
+ if (DRX_ISATVSTD(standard)) {
+ tunerMode |= TUNER_MODE_ANALOG;
+ }
+ else /* note: also for unknown standard */ {
+ tunerMode |= TUNER_MODE_DIGITAL;
+ }
+
+ /* select tuner bandwidth */
+ switch (channel->bandwidth) {
+ case DRX_BANDWIDTH_6MHZ:
+ tunerMode |= TUNER_MODE_6MHZ;
+ break;
+ case DRX_BANDWIDTH_7MHZ:
+ tunerMode |= TUNER_MODE_7MHZ;
+ break;
+ case DRX_BANDWIDTH_8MHZ:
+ tunerMode |= TUNER_MODE_8MHZ;
+ break;
+ default: /* note: also for unknown bandwidth */
+ return DRX_STS_INVALID_ARG;
+ }
+
+ DRX_GET_TUNERSLOWMODE (demod, tunerSlowMode);
+
+ /* select fast (switch) or slow (lock) tuner mode */
+ if (tunerSlowMode) {
+ tunerMode |= TUNER_MODE_LOCK;
+ }
+ else {
+ tunerMode |= TUNER_MODE_SWITCH;
+ }
+
+ if (commonAttr->tunerPortNr == 1) {
+ Bool_t bridgeClosed = TRUE;
+ DRXStatus_t statusBridge = DRX_STS_ERROR;
+
+ statusBridge = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed);
+ if (statusBridge != DRX_STS_OK) {
+ return statusBridge;
+ }
+ }
+
+ status = DRXBSP_TUNER_SetFrequency(demod->myTuner,
+ tunerMode,
+ channel->frequency);
+
+ /* attempt restoring bridge before checking status of SetFrequency */
+ if (commonAttr->tunerPortNr == 1) {
+ Bool_t bridgeClosed = FALSE;
+ DRXStatus_t statusBridge = DRX_STS_ERROR;
+
+ statusBridge = DRX_Ctrl(demod, DRX_CTRL_I2C_BRIDGE, &bridgeClosed);
+ if (statusBridge != DRX_STS_OK) {
+ return statusBridge;
+ }
+ }
+
+ /* now check status of DRXBSP_TUNER_SetFrequency */
+ if (status != DRX_STS_OK) {
+ return status;
+ }
+
+ /* get actual RF and IF frequencies from tuner */
+ status = DRXBSP_TUNER_GetFrequency(demod->myTuner,
+ tunerMode,
+ &(channel->frequency),
+ &(ifFrequency));
+ if (status != DRX_STS_OK) {
+ return status;
+ }
+
+ /* update common attributes with information available from this function;
+ TODO: check if this is required and safe */
+ DRX_SET_INTERMEDIATEFREQ(demod, ifFrequency);
+
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+
+/**
+* \brief function to do a register dump.
+* \param demod: Pointer to demodulator instance.
+* \param registers: Registers to dump.
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Dump executed successfully.
+* \retval DRX_STS_ERROR: Something went wrong.
+* \retval DRX_STS_INVALID_ARG: Wrong parameters.
+*
+*/
+DRXStatus_t CtrlDumpRegisters(pDRXDemodInstance_t demod,
+ pDRXRegDump_t registers)
+{
+ u16_t i = 0;
+
+ if (registers == NULL) {
+ /* registers not supplied */
+ return DRX_STS_INVALID_ARG;
+ }
+
+ /* start dumping registers */
+ while (registers[i].address != 0) {
+ DRXStatus_t status = DRX_STS_ERROR;
+ u16_t value = 0;
+ u32_t data = 0;
+
+ status = demod->myAccessFunct->readReg16Func(
+ demod->myI2CDevAddr, registers[i].address, &value, 0);
+
+ data = (u32_t)value;
+
+ if (status != DRX_STS_OK) {
+ /* no breakouts;
+ depending on device ID, some HW blocks might not be available */
+ data |= ((u32_t)status) << 16;
+ }
+ registers[i].data = data;
+ i++;
+ }
+
+ /* all done, all OK (any errors are saved inside data) */
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+/*============================================================================*/
+/*===Microcode related functions==============================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+/**
+* \brief Read a 16 bits word, expects big endian data.
+* \param addr: Pointer to memory from which to read the 16 bits word.
+* \return u16_t The data read.
+*
+* This function takes care of the possible difference in endianness between the
+* host and the data contained in the microcode image file.
+*
+*/
+static u16_t
+UCodeRead16(pu8_t addr)
+{
+ /* Works fo any host processor */
+
+ u16_t word=0;
+
+ word = ((u16_t)addr[0]);
+ word <<= 8;
+ word |=((u16_t)addr[1]);
+
+ return word;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Read a 32 bits word, expects big endian data.
+* \param addr: Pointer to memory from which to read the 32 bits word.
+* \return u32_t The data read.
+*
+* This function takes care of the possible difference in endianness between the
+* host and the data contained in the microcode image file.
+*
+*/
+static u32_t
+UCodeRead32(pu8_t addr)
+{
+ /* Works fo any host processor */
+
+ u32_t word=0;
+
+ word = ((u16_t)addr[0]);
+ word <<= 8;
+ word |= ((u16_t)addr[1]);
+ word <<= 8;
+ word |= ((u16_t)addr[2]);
+ word <<= 8;
+ word |= ((u16_t)addr[3]);
+
+ return word ;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Compute CRC of block of microcode data.
+* \param blockData: Pointer to microcode data.
+* \param nrWords: Size of microcode block (number of 16 bits words).
+* \return u16_t The computed CRC residu.
+*/
+static u16_t
+UCodeComputeCRC (pu8_t blockData, u16_t nrWords)
+{
+ u16_t i = 0;
+ u16_t j = 0;
+ u32_t CRCWord = 0;
+ u32_t carry = 0;
+
+ while (i < nrWords) {
+ CRCWord |= (u32_t) UCodeRead16(blockData);
+ for (j = 0; j < 16; j++) {
+ CRCWord <<= 1;
+ if (carry != 0) {
+ CRCWord ^= 0x80050000UL;
+ }
+ carry = CRCWord & 0x80000000UL;
+ }
+ i++;
+ blockData+=(sizeof(u16_t));
+ }
+ return ((u16_t) (CRCWord >> 16));
+}
+
+/*============================================================================*/
+
+/**
+* \brief Handle microcode upload or verify.
+* \param devAddr: Address of device.
+* \param mcInfo: Pointer to information about microcode data.
+* \param action: Either UCODE_UPLOAD or UCODE_VERIFY
+* \return DRXStatus_t.
+* \retval DRX_STS_OK:
+* - In case of UCODE_UPLOAD: code is successfully uploaded.
+* - In case of UCODE_VERIFY: image on device is equal to
+* image provided to this control function.
+* \retval DRX_STS_ERROR:
+* - In case of UCODE_UPLOAD: I2C error.
+* - In case of UCODE_VERIFY: I2C error or image on device
+* is not equal to image provided to this control function.
+* \retval DRX_STS_INVALID_ARG:
+* - Invalid arguments.
+* - Provided image is corrupt
+*/
+static DRXStatus_t
+CtrlUCode(pDRXDemodInstance_t demod,
+ pDRXUCodeInfo_t mcInfo,
+ DRXUCodeAction_t action)
+{
+ DRXStatus_t rc;
+ u16_t i = 0;
+ u16_t mcNrOfBlks = 0;
+ u16_t mcMagicWord = 0;
+ pu8_t mcData = (pu8_t)(NULL);
+ pI2CDeviceAddr_t devAddr = (pI2CDeviceAddr_t)(NULL);
+
+ devAddr = demod -> myI2CDevAddr;
+
+ /* Check arguments */
+ if ((mcInfo == NULL) ||
+ (mcInfo->mcData == NULL)) {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ mcData = mcInfo->mcData;
+
+ /* Check data */
+ mcMagicWord = UCodeRead16(mcData);
+ mcData += sizeof(u16_t);
+ mcNrOfBlks = UCodeRead16(mcData);
+ mcData += sizeof(u16_t);
+
+ if ((mcMagicWord != DRX_UCODE_MAGIC_WORD) ||
+ (mcNrOfBlks == 0)) {
+ /* wrong endianess or wrong data ? */
+ return DRX_STS_INVALID_ARG;
+ }
+
+ /* Scan microcode blocks first for version info if uploading */
+ if (action == UCODE_UPLOAD) {
+ /* Clear version block */
+ DRX_SET_MCVERTYPE (demod, 0);
+ DRX_SET_MCDEV (demod, 0);
+ DRX_SET_MCVERSION (demod, 0);
+ DRX_SET_MCPATCH (demod, 0);
+ for (i = 0; i < mcNrOfBlks; i++) {
+ DRXUCodeBlockHdr_t blockHdr;
+
+ /* Process block header */
+ blockHdr.addr = UCodeRead32(mcData);
+ mcData += sizeof(u32_t);
+ blockHdr.size = UCodeRead16(mcData);
+ mcData += sizeof(u16_t);
+ blockHdr.flags = UCodeRead16(mcData);
+ mcData += sizeof(u16_t);
+ blockHdr.CRC = UCodeRead16(mcData);
+ mcData += sizeof(u16_t);
+
+ if (blockHdr.flags & 0x8) {
+ /* Aux block. Check type */
+ pu8_t auxblk = mcInfo->mcData + blockHdr.addr;
+ u16_t auxtype = UCodeRead16 (auxblk);
+ if (DRX_ISMCVERTYPE (auxtype)) {
+ DRX_SET_MCVERTYPE (demod, UCodeRead16 (auxblk));
+ auxblk += sizeof (u16_t);
+ DRX_SET_MCDEV (demod, UCodeRead32 (auxblk));
+ auxblk += sizeof (u32_t);
+ DRX_SET_MCVERSION (demod, UCodeRead32 (auxblk));
+ auxblk += sizeof (u32_t);
+ DRX_SET_MCPATCH (demod, UCodeRead32 (auxblk));
+ }
+ }
+
+ /* Next block */
+ mcData += blockHdr.size * sizeof (u16_t);
+ }
+ /* After scanning, validate the microcode.
+ It is also valid if no validation control exists.
+ */
+ rc = DRX_Ctrl (demod, DRX_CTRL_VALIDATE_UCODE, NULL);
+ if (rc != DRX_STS_OK && rc != DRX_STS_FUNC_NOT_AVAILABLE) {
+ return rc;
+ }
+
+ /* Restore data pointer */
+ mcData = mcInfo->mcData + 2 * sizeof(u16_t);
+ }
+
+ /* Process microcode blocks */
+ for(i = 0 ; i<mcNrOfBlks ; i++) {
+ DRXUCodeBlockHdr_t blockHdr;
+ u16_t mcBlockNrBytes = 0;
+
+ /* Process block header */
+ blockHdr.addr = UCodeRead32(mcData);
+ mcData += sizeof(u32_t);
+ blockHdr.size = UCodeRead16(mcData);
+ mcData += sizeof(u16_t);
+ blockHdr.flags = UCodeRead16(mcData);
+ mcData += sizeof(u16_t);
+ blockHdr.CRC = UCodeRead16(mcData);
+ mcData += sizeof(u16_t);
+
+ /* Check block header on:
+ - data larger than 64Kb
+ - if CRC enabled check CRC
+ */
+ if ((blockHdr.size > 0x7FFF) ||
+ (((blockHdr.flags & DRX_UCODE_CRC_FLAG) != 0) &&
+ (blockHdr.CRC != UCodeComputeCRC (mcData, blockHdr.size)))
+ ) {
+ /* Wrong data ! */
+ return DRX_STS_INVALID_ARG;
+ }
+
+ mcBlockNrBytes = blockHdr.size * ((u16_t)sizeof(u16_t));
+
+ if (blockHdr.size != 0) {
+ /* Perform the desired action */
+ switch (action) {
+ /*================================================================*/
+ case UCODE_UPLOAD : {
+ /* Upload microcode */
+ if (demod->myAccessFunct->writeBlockFunc(
+ devAddr,
+ (DRXaddr_t) blockHdr.addr,
+ mcBlockNrBytes,
+ mcData,
+ 0x0000) != DRX_STS_OK) {
+ return (DRX_STS_ERROR);
+ } /* if */
+ };
+ break;
+
+ /*================================================================*/
+ case UCODE_VERIFY : {
+ int result = 0;
+ u8_t mcDataBuffer[DRX_UCODE_MAX_BUF_SIZE];
+ u32_t bytesToCompare=0;
+ u32_t bytesLeftToCompare=0;
+ DRXaddr_t currAddr = (DRXaddr_t)0;
+ pu8_t currPtr =NULL;
+
+ bytesLeftToCompare = mcBlockNrBytes;
+ currAddr = blockHdr.addr;
+ currPtr = mcData;
+
+ while(bytesLeftToCompare != 0) {
+ if (bytesLeftToCompare > ((u32_t)DRX_UCODE_MAX_BUF_SIZE)) {
+ bytesToCompare = ((u32_t)DRX_UCODE_MAX_BUF_SIZE);
+ }
+ else {
+ bytesToCompare = bytesLeftToCompare;
+ }
+
+ if (demod->myAccessFunct->readBlockFunc(
+ devAddr,
+ currAddr,
+ (u16_t)bytesToCompare,
+ (pu8_t)mcDataBuffer,
+ 0x0000) != DRX_STS_OK) {
+ return (DRX_STS_ERROR);
+ }
+
+ result = DRXBSP_HST_Memcmp(currPtr,
+ mcDataBuffer,
+ bytesToCompare);
+
+ if (result != 0) {
+ return DRX_STS_ERROR;
+ }
+
+ currAddr += ((DRXaddr_t)(bytesToCompare/2));
+ currPtr = &(currPtr[bytesToCompare]);
+ bytesLeftToCompare -= ((u32_t)bytesToCompare);
+ } /* while(bytesToCompare > DRX_UCODE_MAX_BUF_SIZE) */
+ };
+ break;
+
+ /*================================================================*/
+ default:
+ return DRX_STS_INVALID_ARG;
+ break;
+
+ } /* switch (action) */
+ } /* if (blockHdr.size != 0) */
+
+ /* Next block */
+ mcData += mcBlockNrBytes;
+
+ } /* for(i = 0 ; i<mcNrOfBlks ; i++) */
+
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Build list of version information.
+* \param demod: A pointer to a demodulator instance.
+* \param versionList: Pointer to linked list of versions.
+* \return DRXStatus_t.
+* \retval DRX_STS_OK: Version information stored in versionList
+* \retval DRX_STS_INVALID_ARG: Invalid arguments.
+*/
+static DRXStatus_t
+CtrlVersion(pDRXDemodInstance_t demod,
+ pDRXVersionList_t *versionList)
+{
+ static char drxDriverCoreModuleName[] = "Core driver";
+ static char drxDriverCoreVersionText[] =
+ DRX_VERSIONSTRING(VERSION_MAJOR, VERSION_MINOR, VERSION_PATCH);
+
+ static DRXVersion_t drxDriverCoreVersion;
+ static DRXVersionList_t drxDriverCoreVersionList;
+
+ pDRXVersionList_t demodVersionList = (pDRXVersionList_t)(NULL);
+ DRXStatus_t returnStatus = DRX_STS_ERROR;
+
+ /* Check arguments */
+ if (versionList == NULL) {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ /* Get version info list from demod */
+ returnStatus = (*(demod->myDemodFunct->ctrlFunc))(
+ demod,
+ DRX_CTRL_VERSION,
+ (void *) &demodVersionList);
+
+ /* Always fill in the information of the driver SW . */
+ drxDriverCoreVersion.moduleType = DRX_MODULE_DRIVERCORE;
+ drxDriverCoreVersion.moduleName = drxDriverCoreModuleName;
+ drxDriverCoreVersion.vMajor = VERSION_MAJOR;
+ drxDriverCoreVersion.vMinor = VERSION_MINOR;
+ drxDriverCoreVersion.vPatch = VERSION_PATCH;
+ drxDriverCoreVersion.vString = drxDriverCoreVersionText;
+
+ drxDriverCoreVersionList.version = &drxDriverCoreVersion;
+ drxDriverCoreVersionList.next = (pDRXVersionList_t)(NULL);
+
+ if ((returnStatus == DRX_STS_OK) && (demodVersionList != NULL)) {
+ /* Append versioninfo from driver to versioninfo from demod */
+ /* Return version info in "bottom-up" order. This way, multiple
+ devices can be handled without using malloc. */
+ pDRXVersionList_t currentListElement = demodVersionList;
+ while (currentListElement->next != NULL) {
+ currentListElement = currentListElement->next;
+ }
+ currentListElement->next = &drxDriverCoreVersionList;
+
+ *versionList = demodVersionList;
+ }
+ else {
+ /* Just return versioninfo from driver */
+ *versionList = &drxDriverCoreVersionList;
+ }
+
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+/*============================================================================*/
+/*== Exported functions ======================================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+
+
+/**
+* \brief This function is obsolete.
+* \param demods: Don't care, parameter is ignored.
+* \return DRXStatus_t Return status.
+* \retval DRX_STS_OK: Initialization completed.
+*
+* This function is obsolete, prototype available for backward compatability.
+*
+*/
+
+DRXStatus_t
+DRX_Init(pDRXDemodInstance_t demods[])
+{
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+
+/**
+* \brief This function is obsolete.
+* \return DRXStatus_t Return status.
+* \retval DRX_STS_OK: Terminated driver successful.
+*
+* This function is obsolete, prototype available for backward compatability.
+*
+*/
+
+DRXStatus_t
+DRX_Term(void)
+{
+ return DRX_STS_OK;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Open a demodulator instance.
+* \param demod: A pointer to a demodulator instance.
+* \return DRXStatus_t Return status.
+* \retval DRX_STS_OK: Opened demod instance with succes.
+* \retval DRX_STS_ERROR: Driver not initialized or unable to initialize
+* demod.
+* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content.
+*
+*/
+
+DRXStatus_t
+DRX_Open(pDRXDemodInstance_t demod)
+{
+ DRXStatus_t status = DRX_STS_OK;
+
+ if ((demod == NULL) ||
+ (demod->myDemodFunct == NULL) ||
+ (demod->myCommonAttr == NULL) ||
+ (demod->myExtAttr == NULL) ||
+ (demod->myI2CDevAddr == NULL) ||
+ (demod->myCommonAttr->isOpened == TRUE)) {
+ return (DRX_STS_INVALID_ARG);
+ }
+
+ status = (*(demod->myDemodFunct->openFunc))(demod);
+
+ if (status == DRX_STS_OK) {
+ demod->myCommonAttr->isOpened = TRUE;
+ }
+
+ return status;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Close device.
+* \param demod: A pointer to a demodulator instance.
+* \return DRXStatus_t Return status.
+* \retval DRX_STS_OK: Closed demod instance with succes.
+* \retval DRX_STS_ERROR: Driver not initialized or error during close
+* demod.
+* \retval DRX_STS_INVALID_ARG: Demod instance has invalid content.
+*
+* Free resources occupied by device instance.
+* Put device into sleep mode.
+*/
+
+DRXStatus_t
+DRX_Close(pDRXDemodInstance_t demod)
+{
+ DRXStatus_t status = DRX_STS_OK;
+
+ if ((demod == NULL) ||
+ (demod->myDemodFunct == NULL) ||
+ (demod->myCommonAttr == NULL) ||
+ (demod->myExtAttr == NULL) ||
+ (demod->myI2CDevAddr == NULL) ||
+ (demod->myCommonAttr->isOpened == FALSE)) {
+ return DRX_STS_INVALID_ARG;
+ }
+
+ status = (*(demod->myDemodFunct->closeFunc))(demod);
+
+ DRX_SET_ISOPENED (demod, FALSE);
+
+ return status;
+}
+
+/*============================================================================*/
+
+/**
+* \brief Control the device.
+* \param demod: A pointer to a demodulator instance.
+* \param ctrl: Reference to desired control function.
+* \param ctrlData: Pointer to data structure for control function.
+* \return DRXStatus_t Return status.
+* \retval DRX_STS_OK: Control function completed successfully.
+* \retval DRX_STS_ERROR: Driver not initialized or error during
+* control demod.
+* \retval DRX_STS_INVALID_ARG: Demod instance or ctrlData has invalid
+* content.
+* \retval DRX_STS_FUNC_NOT_AVAILABLE: Specified control function is not
+* available.
+*
+* Data needed or returned by the control function is stored in ctrlData.
+*
+*/
+
+DRXStatus_t
+DRX_Ctrl(pDRXDemodInstance_t demod, DRXCtrlIndex_t ctrl, void *ctrlData)
+{
+ DRXStatus_t status = DRX_STS_ERROR;
+
+ if ((demod == NULL) ||
+ (demod->myDemodFunct == NULL) ||
+ (demod->myCommonAttr == NULL) ||
+ (demod->myExtAttr == NULL) ||
+ (demod->myI2CDevAddr == NULL)
+ ) {
+ return (DRX_STS_INVALID_ARG);
+ }
+
+ if (((demod->myCommonAttr->isOpened == FALSE) &&
+ (ctrl != DRX_CTRL_PROBE_DEVICE) &&
+ (ctrl != DRX_CTRL_VERSION))
+ ) {
+ return (DRX_STS_INVALID_ARG);
+ }
+
+ if ((DRX_ISPOWERDOWNMODE(demod->myCommonAttr->currentPowerMode) &&
+ (ctrl != DRX_CTRL_POWER_MODE) &&
+ (ctrl != DRX_CTRL_PROBE_DEVICE) &&
+ (ctrl != DRX_CTRL_NOP) &&
+ (ctrl != DRX_CTRL_VERSION)
+ )
+ ) {
+ return DRX_STS_FUNC_NOT_AVAILABLE;
+ }
+
+ /* Fixed control functions */
+ switch (ctrl) {
+ /*======================================================================*/
+ case DRX_CTRL_NOP:
+ /* No operation */
+ return DRX_STS_OK;
+ break;
+
+ /*======================================================================*/
+ case DRX_CTRL_VERSION:
+ return CtrlVersion(demod, (pDRXVersionList_t *) ctrlData);
+ break;
+
+ /*======================================================================*/
+ default :
+ /* Do nothing */
+ break;
+ }
+
+ /* Virtual functions */
+ /* First try calling function from derived class */
+ status = (*(demod->myDemodFunct->ctrlFunc))(demod, ctrl, ctrlData);
+ if (status == DRX_STS_FUNC_NOT_AVAILABLE) {
+ /* Now try calling a the base class function */
+ switch (ctrl) {
+ /*===================================================================*/
+ case DRX_CTRL_LOAD_UCODE:
+ return CtrlUCode (demod,
+ (pDRXUCodeInfo_t) ctrlData,
+ UCODE_UPLOAD);
+ break;
+
+ /*===================================================================*/
+ case DRX_CTRL_VERIFY_UCODE: {
+ return CtrlUCode (demod,
+ (pDRXUCodeInfo_t) ctrlData,
+ UCODE_VERIFY);
+ }
+ break;
+
+#ifndef DRX_EXCLUDE_SCAN
+ /*===================================================================*/
+ case DRX_CTRL_SCAN_INIT: {
+ return CtrlScanInit(demod, (pDRXScanParam_t) ctrlData);
+ }
+ break;
+
+ /*===================================================================*/
+ case DRX_CTRL_SCAN_NEXT: {
+ return CtrlScanNext(demod, (pu16_t) ctrlData);
+ }
+ break;
+
+ /*===================================================================*/
+ case DRX_CTRL_SCAN_STOP: {
+ return CtrlScanStop(demod);
+ }
+ break;
+#endif /* #ifndef DRX_EXCLUDE_SCAN */
+
+ /*===================================================================*/
+ case DRX_CTRL_PROGRAM_TUNER: {
+ return CtrlProgramTuner(demod, (pDRXChannel_t) ctrlData);
+ }
+ break;
+
+ /*===================================================================*/
+ case DRX_CTRL_DUMP_REGISTERS: {
+ return CtrlDumpRegisters(demod, (pDRXRegDump_t) ctrlData);
+ }
+ break;
+
+ /*===================================================================*/
+ default :
+ return DRX_STS_FUNC_NOT_AVAILABLE;
+ }
+ }
+ else {
+ return (status);
+ }
+
+ return DRX_STS_OK;
+}
+
+
+/*============================================================================*/
+
+/* END OF FILE */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 12/25] added drx_driver header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (10 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 11/25] added drx_driver " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 13/25] added drx_driver_version " Patrick Dickey
` (10 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drx_driver.h | 2588 ++++++++++++++++++++++++++++++
1 files changed, 2588 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drx_driver.h
diff --git a/drivers/media/dvb/frontends/drx_driver.h b/drivers/media/dvb/frontends/drx_driver.h
new file mode 100644
index 0000000..841932a
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx_driver.h
@@ -0,0 +1,2588 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/**
+* \file $Id: drx_driver.h,v 1.84 2010/01/14 22:47:50 dingtao Exp $
+*
+* \brief DRX driver API
+*
+*/
+#ifndef __DRXDRIVER_H__
+#define __DRXDRIVER_H__
+/*-------------------------------------------------------------------------
+INCLUDES
+-------------------------------------------------------------------------*/
+#include "bsp_types.h"
+#include "bsp_i2c.h"
+#include "bsp_tuner.h"
+#include "bsp_host.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*-------------------------------------------------------------------------
+TYPEDEFS
+-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------
+DEFINES
+-------------------------------------------------------------------------*/
+
+/**************
+*
+* This section configures the DRX Data Access Protocols (DAPs).
+*
+**************/
+
+/**
+* \def DRXDAP_SINGLE_MASTER
+* \brief Enable I2C single or I2C multimaster mode on host.
+*
+* Set to 1 to enable single master mode
+* Set to 0 to enable multi master mode
+*
+* The actual DAP implementation may be restricted to only one of the modes.
+* A compiler warning or error will be generated if the DAP implementation
+* overides or cannot handle the mode defined below.
+*
+*/
+#ifndef DRXDAP_SINGLE_MASTER
+#define DRXDAP_SINGLE_MASTER 0
+#endif
+
+/**
+* \def DRXDAP_MAX_WCHUNKSIZE
+* \brief Defines maximum chunksize of an i2c write action by host.
+*
+* This indicates the maximum size of data the I2C device driver is able to
+* write at a time. This includes I2C device address and register addressing.
+*
+* This maximum size may be restricted by the actual DAP implementation.
+* A compiler warning or error will be generated if the DAP implementation
+* overides or cannot handle the chunksize defined below.
+*
+* Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data
+* buffer. Do not undefine or choose too large, unless your system is able to
+* handle a stack buffer of that size.
+*
+*/
+#ifndef DRXDAP_MAX_WCHUNKSIZE
+#define DRXDAP_MAX_WCHUNKSIZE 60
+#endif
+
+/**
+* \def DRXDAP_MAX_RCHUNKSIZE
+* \brief Defines maximum chunksize of an i2c read action by host.
+*
+* This indicates the maximum size of data the I2C device driver is able to read
+* at a time. Minimum value is 2. Also, the read chunk size must be even.
+*
+* This maximum size may be restricted by the actual DAP implementation.
+* A compiler warning or error will be generated if the DAP implementation
+* overides or cannot handle the chunksize defined below.
+*
+*/
+#ifndef DRXDAP_MAX_RCHUNKSIZE
+#define DRXDAP_MAX_RCHUNKSIZE 60
+#endif
+
+/**************
+*
+* This section describes drxdriver defines.
+*
+**************/
+
+/**
+* \def DRX_UNKNOWN
+* \brief Generic UNKNOWN value for DRX enumerated types.
+*
+* Used to indicate that the parameter value is unknown or not yet initalized.
+*/
+#ifndef DRX_UNKNOWN
+#define DRX_UNKNOWN (254)
+#endif
+
+/**
+* \def DRX_AUTO
+* \brief Generic AUTO value for DRX enumerated types.
+*
+* Used to instruct the driver to automatically determine the value of the
+* parameter.
+*/
+#ifndef DRX_AUTO
+#define DRX_AUTO (255)
+#endif
+
+
+/**************
+*
+* This section describes flag definitions for the device capbilities.
+*
+**************/
+
+/**
+* \brief LNA capability flag
+*
+* Device has a Low Noise Amplifier
+*
+*/
+#define DRX_CAPABILITY_HAS_LNA (1UL << 0)
+/**
+* \brief OOB-RX capability flag
+*
+* Device has OOB-RX
+*
+*/
+#define DRX_CAPABILITY_HAS_OOBRX (1UL << 1)
+/**
+* \brief ATV capability flag
+*
+* Device has ATV
+*
+*/
+#define DRX_CAPABILITY_HAS_ATV (1UL << 2)
+/**
+* \brief DVB-T capability flag
+*
+* Device has DVB-T
+*
+*/
+#define DRX_CAPABILITY_HAS_DVBT (1UL << 3)
+/**
+* \brief ITU-B capability flag
+*
+* Device has ITU-B
+*
+*/
+#define DRX_CAPABILITY_HAS_ITUB (1UL << 4)
+/**
+* \brief Audio capability flag
+*
+* Device has Audio
+*
+*/
+#define DRX_CAPABILITY_HAS_AUD (1UL << 5)
+/**
+* \brief SAW switch capability flag
+*
+* Device has SAW switch
+*
+*/
+#define DRX_CAPABILITY_HAS_SAWSW (1UL << 6)
+/**
+* \brief GPIO1 capability flag
+*
+* Device has GPIO1
+*
+*/
+#define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7)
+/**
+* \brief GPIO2 capability flag
+*
+* Device has GPIO2
+*
+*/
+#define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8)
+/**
+* \brief IRQN capability flag
+*
+* Device has IRQN
+*
+*/
+#define DRX_CAPABILITY_HAS_IRQN (1UL << 9)
+/**
+* \brief 8VSB capability flag
+*
+* Device has 8VSB
+*
+*/
+#define DRX_CAPABILITY_HAS_8VSB (1UL << 10)
+/**
+* \brief SMA-TX capability flag
+*
+* Device has SMATX
+*
+*/
+#define DRX_CAPABILITY_HAS_SMATX (1UL << 11)
+/**
+* \brief SMA-RX capability flag
+*
+* Device has SMARX
+*
+*/
+#define DRX_CAPABILITY_HAS_SMARX (1UL << 12)
+/**
+* \brief ITU-A/C capability flag
+*
+* Device has ITU-A/C
+*
+*/
+#define DRX_CAPABILITY_HAS_ITUAC (1UL << 13)
+
+/*-------------------------------------------------------------------------
+MACROS
+-------------------------------------------------------------------------*/
+/* Macros to stringify the version number */
+#define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \
+ DRX_VERSIONSTRING_HELP(MAJOR)"." \
+ DRX_VERSIONSTRING_HELP(MINOR)"." \
+ DRX_VERSIONSTRING_HELP(PATCH)
+#define DRX_VERSIONSTRING_HELP(NUM) #NUM
+
+/**
+* \brief Macro to create byte array elements from 16 bit integers.
+* This macro is used to create byte arrays for block writes.
+* Block writes speed up I2C traffic between host and demod.
+* The macro takes care of the required byte order in a 16 bits word.
+* x->lowbyte(x), highbyte(x)
+*/
+#define DRX_16TO8(x) ((u8_t) (((u16_t)x) &0xFF)), \
+ ((u8_t)((((u16_t)x)>>8)&0xFF))
+
+/**
+* \brief Macro to sign extend signed 9 bit value to signed 16 bit value
+*/
+#define DRX_S9TOS16(x) ((((u16_t)x)&0x100)?((s16_t)((u16_t)(x)|0xFF00)):(x))
+
+/**
+* \brief Macro to sign extend signed 9 bit value to signed 16 bit value
+*/
+#define DRX_S24TODRXFREQ(x) ((((u32_t) x) & 0x00800000UL) ? \
+ ((DRXFrequency_t) \
+ (((u32_t) x) | 0xFF000000)) : \
+ ((DRXFrequency_t) x))
+
+/**
+* \brief Macro to convert 16 bit register value to a DRXFrequency_t
+*/
+#define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \
+ ((DRXFrequency_t) \
+ (((u32_t) x) | 0xFFFF0000)) : \
+ ((DRXFrequency_t) x))
+
+/*-------------------------------------------------------------------------
+ENUM
+-------------------------------------------------------------------------*/
+
+/**
+* \enum DRXStandard_t
+* \brief Modulation standards.
+*/
+typedef enum {
+ DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */
+ DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */
+ DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */
+ DRX_STANDARD_PAL_SECAM_BG, /**< Terrestrial analog PAL/SECAM B/G */
+ DRX_STANDARD_PAL_SECAM_DK, /**< Terrestrial analog PAL/SECAM D/K */
+ DRX_STANDARD_PAL_SECAM_I, /**< Terrestrial analog PAL/SECAM I */
+ DRX_STANDARD_PAL_SECAM_L, /**< Terrestrial analog PAL/SECAM L
+ with negative modulation */
+ DRX_STANDARD_PAL_SECAM_LP, /**< Terrestrial analog PAL/SECAM L
+ with positive modulation */
+ DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */
+ DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */
+ DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */
+ DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */
+ DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */
+ DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/
+ DRX_STANDARD_UNKNOWN = DRX_UNKNOWN, /**< Standard unknown. */
+ DRX_STANDARD_AUTO = DRX_AUTO /**< Autodetect standard. */
+} DRXStandard_t, *pDRXStandard_t;
+
+/**
+* \enum DRXStandard_t
+* \brief Modulation sub-standards.
+*/
+typedef enum {
+ DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */
+ DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
+ DRX_SUBSTANDARD_ATV_DK_POLAND,
+ DRX_SUBSTANDARD_ATV_DK_CHINA,
+ DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN, /**< Sub-standard unknown. */
+ DRX_SUBSTANDARD_AUTO = DRX_AUTO /**< Auto (default) sub-standard */
+} DRXSubstandard_t, *pDRXSubstandard_t;
+
+/**
+* \enum DRXBandwidth_t
+* \brief Channel bandwidth or channel spacing.
+*/
+typedef enum {
+ DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */
+ DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */
+ DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */
+ DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN, /**< Bandwidth unknown. */
+ DRX_BANDWIDTH_AUTO = DRX_AUTO /**< Auto Set Bandwidth */
+} DRXBandwidth_t, *pDRXBandwidth_t;
+
+/**
+* \enum DRXMirror_t
+* \brief Indicate if channel spectrum is mirrored or not.
+*/
+typedef enum {
+ DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */
+ DRX_MIRROR_YES, /**< Spectrum is mirrored. */
+ DRX_MIRROR_UNKNOWN = DRX_UNKNOWN, /**< Unknown if spectrum is mirrored. */
+ DRX_MIRROR_AUTO = DRX_AUTO /**< Autodetect if spectrum is mirrored. */
+} DRXMirror_t, *pDRXMirror_t;
+
+/**
+* \enum DRXConstellation_t
+* \brief Constellation type of the channel.
+*/
+typedef enum {
+ DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */
+ DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */
+ DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */
+ DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */
+ DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */
+ DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */
+ DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */
+ DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */
+ DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */
+ DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */
+ DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */
+ DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN, /**< Constellation unknown. */
+ DRX_CONSTELLATION_AUTO = DRX_AUTO /**< Autodetect constellation. */
+} DRXConstellation_t, *pDRXConstellation_t;
+
+/**
+* \enum DRXHierarchy_t
+* \brief Hierarchy of the channel.
+*/
+typedef enum {
+ DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */
+ DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */
+ DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */
+ DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */
+ DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN, /**< Hierarchy unknown. */
+ DRX_HIERARCHY_AUTO = DRX_AUTO /**< Autodetect hierarchy. */
+} DRXHierarchy_t, *pDRXHierarchy_t;
+
+/**
+* \enum DRXPriority_t
+* \brief Channel priority in case of hierarchical transmission.
+*/
+typedef enum {
+ DRX_PRIORITY_LOW = 0, /**< Low priority channel. */
+ DRX_PRIORITY_HIGH, /**< High priority channel. */
+ DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN /**< Priority unknown. */
+} DRXPriority_t, *pDRXPriority_t;
+
+/**
+* \enum DRXCoderate_t
+* \brief Channel priority in case of hierarchical transmission.
+*/
+typedef enum {
+ DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */
+ DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */
+ DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */
+ DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */
+ DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */
+ DRX_CODERATE_UNKNOWN = DRX_UNKNOWN, /**< Code rate unknown. */
+ DRX_CODERATE_AUTO = DRX_AUTO /**< Autodetect code rate. */
+} DRXCoderate_t, *pDRXCoderate_t;
+
+/**
+* \enum DRXGuard_t
+* \brief Guard interval of a channel.
+*/
+typedef enum {
+ DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */
+ DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */
+ DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */
+ DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */
+ DRX_GUARD_UNKNOWN = DRX_UNKNOWN, /**< Guard interval unknown. */
+ DRX_GUARD_AUTO = DRX_AUTO /**< Autodetect guard interval. */
+} DRXGuard_t, *pDRXGuard_t;
+
+/**
+* \enum DRXFftmode_t
+* \brief FFT mode.
+*/
+typedef enum {
+ DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */
+ DRX_FFTMODE_4K, /**< 4K FFT mode. */
+ DRX_FFTMODE_8K, /**< 8K FFT mode. */
+ DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN, /**< FFT mode unknown. */
+ DRX_FFTMODE_AUTO = DRX_AUTO /**< Autodetect FFT mode. */
+} DRXFftmode_t, *pDRXFftmode_t;
+
+/**
+* \enum DRXClassification_t
+* \brief Channel classification.
+*/
+typedef enum {
+ DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */
+ DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */
+ DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */
+ DRX_CLASSIFICATION_STATIC, /**< Static echo. */
+ DRX_CLASSIFICATION_MOVING, /**< Moving echo. */
+ DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */
+ DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN, /**< Unknown classification */
+ DRX_CLASSIFICATION_AUTO = DRX_AUTO /**< Autodetect classification. */
+} DRXClassification_t, *pDRXClassification_t;
+
+/**
+* /enum DRXInterleaveModes_t
+* /brief Interleave modes
+*/
+typedef enum {
+ DRX_INTERLEAVEMODE_I128_J1 = 0,
+ DRX_INTERLEAVEMODE_I128_J1_V2,
+ DRX_INTERLEAVEMODE_I128_J2,
+ DRX_INTERLEAVEMODE_I64_J2,
+ DRX_INTERLEAVEMODE_I128_J3,
+ DRX_INTERLEAVEMODE_I32_J4,
+ DRX_INTERLEAVEMODE_I128_J4,
+ DRX_INTERLEAVEMODE_I16_J8,
+ DRX_INTERLEAVEMODE_I128_J5,
+ DRX_INTERLEAVEMODE_I8_J16,
+ DRX_INTERLEAVEMODE_I128_J6,
+ DRX_INTERLEAVEMODE_RESERVED_11,
+ DRX_INTERLEAVEMODE_I128_J7,
+ DRX_INTERLEAVEMODE_RESERVED_13,
+ DRX_INTERLEAVEMODE_I128_J8,
+ DRX_INTERLEAVEMODE_RESERVED_15,
+ DRX_INTERLEAVEMODE_I12_J17,
+ DRX_INTERLEAVEMODE_I5_J4,
+ DRX_INTERLEAVEMODE_B52_M240,
+ DRX_INTERLEAVEMODE_B52_M720,
+ DRX_INTERLEAVEMODE_B52_M48,
+ DRX_INTERLEAVEMODE_B52_M0,
+ DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN, /**< Unknown interleave mode */
+ DRX_INTERLEAVEMODE_AUTO = DRX_AUTO /**< Autodetect interleave mode */
+} DRXInterleaveModes_t, *pDRXInterleaveModes_t;
+
+/**
+* \enum DRXCarrier_t
+* \brief Channel Carrier Mode.
+*/
+typedef enum {
+ DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */
+ DRX_CARRIER_SINGLE, /**< Single carrier mode */
+ DRX_CARRIER_UNKNOWN = DRX_UNKNOWN, /**< Carrier mode unknown. */
+ DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */
+} DRXCarrier_t, *pDRXCarrier_t;
+
+/**
+* \enum DRXFramemode_t
+* \brief Channel Frame Mode.
+*/
+typedef enum {
+ DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */
+ DRX_FRAMEMODE_595, /**< 595 */
+ DRX_FRAMEMODE_945, /**< 945 with variable PN */
+ DRX_FRAMEMODE_420_FIXED_PN, /**< 420 with fixed PN */
+ DRX_FRAMEMODE_945_FIXED_PN, /**< 945 with fixed PN */
+ DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN, /**< Frame mode unknown. */
+ DRX_FRAMEMODE_AUTO = DRX_AUTO /**< Autodetect frame mode */
+} DRXFramemode_t, *pDRXFramemode_t;
+
+/**
+* \enum DRXTPSFrame_t
+* \brief Frame number in current super-frame.
+*/
+typedef enum {
+ DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */
+ DRX_TPS_FRAME2, /**< TPS frame 2. */
+ DRX_TPS_FRAME3, /**< TPS frame 3. */
+ DRX_TPS_FRAME4, /**< TPS frame 4. */
+ DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN /**< TPS frame unknown. */
+} DRXTPSFrame_t, *pDRXTPSFrame_t;
+
+/**
+* \enum DRXLDPC_t
+* \brief TPS LDPC .
+*/
+typedef enum {
+ DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */
+ DRX_LDPC_0_6, /**< LDPC 0.6 */
+ DRX_LDPC_0_8, /**< LDPC 0.8 */
+ DRX_LDPC_UNKNOWN = DRX_UNKNOWN, /**< LDPC unknown. */
+ DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */
+} DRXLDPC_t, *pDRXLDPC_t;
+
+/**
+* \enum DRXPilotMode_t
+* \brief Pilot modes in DTMB.
+*/
+typedef enum {
+ DRX_PILOT_ON = 0, /**< Pilot On */
+ DRX_PILOT_OFF, /**< Pilot Off */
+ DRX_PILOT_UNKNOWN = DRX_UNKNOWN, /**< Pilot unknown. */
+ DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */
+} DRXPilotMode_t, *pDRXPilotMode_t;
+
+
+
+/**
+* \enum DRXCtrlIndex_t
+* \brief Indices of the control functions.
+*/
+typedef u32_t DRXCtrlIndex_t, *pDRXCtrlIndex_t;
+
+#ifndef DRX_CTRL_BASE
+#define DRX_CTRL_BASE ((DRXCtrlIndex_t)0)
+#endif
+
+#define DRX_CTRL_NOP (DRX_CTRL_BASE + 0)/**< No Operation */
+#define DRX_CTRL_PROBE_DEVICE (DRX_CTRL_BASE + 1)/**< Probe device */
+
+#define DRX_CTRL_LOAD_UCODE (DRX_CTRL_BASE + 2)/**< Load microcode */
+#define DRX_CTRL_VERIFY_UCODE (DRX_CTRL_BASE + 3)/**< Verify microcode */
+#define DRX_CTRL_SET_CHANNEL (DRX_CTRL_BASE + 4)/**< Set channel */
+#define DRX_CTRL_GET_CHANNEL (DRX_CTRL_BASE + 5)/**< Get channel */
+#define DRX_CTRL_LOCK_STATUS (DRX_CTRL_BASE + 6)/**< Get lock status */
+#define DRX_CTRL_SIG_QUALITY (DRX_CTRL_BASE + 7)/**< Get signal quality */
+#define DRX_CTRL_SIG_STRENGTH (DRX_CTRL_BASE + 8)/**< Get signal strength*/
+#define DRX_CTRL_RF_POWER (DRX_CTRL_BASE + 9)/**< Get RF power */
+#define DRX_CTRL_CONSTEL (DRX_CTRL_BASE + 10)/**< Get constel point */
+#define DRX_CTRL_SCAN_INIT (DRX_CTRL_BASE + 11)/**< Initialize scan */
+#define DRX_CTRL_SCAN_NEXT (DRX_CTRL_BASE + 12)/**< Scan for next */
+#define DRX_CTRL_SCAN_STOP (DRX_CTRL_BASE + 13)/**< Stop scan */
+#define DRX_CTRL_TPS_INFO (DRX_CTRL_BASE + 14)/**< Get TPS info */
+#define DRX_CTRL_SET_CFG (DRX_CTRL_BASE + 15)/**< Set configuration */
+#define DRX_CTRL_GET_CFG (DRX_CTRL_BASE + 16)/**< Get configuration */
+#define DRX_CTRL_VERSION (DRX_CTRL_BASE + 17)/**< Get version info */
+#define DRX_CTRL_I2C_BRIDGE (DRX_CTRL_BASE + 18)/**< Open/close bridge */
+#define DRX_CTRL_SET_STANDARD (DRX_CTRL_BASE + 19)/**< Set demod std */
+#define DRX_CTRL_GET_STANDARD (DRX_CTRL_BASE + 20)/**< Get demod std */
+#define DRX_CTRL_SET_OOB (DRX_CTRL_BASE + 21)/**< Set OOB param */
+#define DRX_CTRL_GET_OOB (DRX_CTRL_BASE + 22)/**< Get OOB param */
+#define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */
+#define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */
+#define DRX_CTRL_AUD_GET_STATUS (DRX_CTRL_BASE + 25)/**< Read RDS */
+#define DRX_CTRL_AUD_BEEP (DRX_CTRL_BASE + 26)/**< Read RDS */
+#define DRX_CTRL_I2C_READWRITE (DRX_CTRL_BASE + 27)/**< Read/write I2C */
+#define DRX_CTRL_PROGRAM_TUNER (DRX_CTRL_BASE + 28)/**< Program tuner */
+
+ /* Professional */
+#define DRX_CTRL_MB_CFG (DRX_CTRL_BASE + 29) /**< */
+#define DRX_CTRL_MB_READ (DRX_CTRL_BASE + 30) /**< */
+#define DRX_CTRL_MB_WRITE (DRX_CTRL_BASE + 31) /**< */
+#define DRX_CTRL_MB_CONSTEL (DRX_CTRL_BASE + 32) /**< */
+#define DRX_CTRL_MB_MER (DRX_CTRL_BASE + 33) /**< */
+
+ /* Misc */
+#define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */
+#define DRX_CTRL_SET_UIO_CFG (DRX_CTRL_BASE + 34) /**< Configure UIO */
+#define DRX_CTRL_GET_UIO_CFG (DRX_CTRL_BASE + 35) /**< Configure UIO */
+#define DRX_CTRL_UIO_READ (DRX_CTRL_BASE + 36) /**< Read from UIO */
+#define DRX_CTRL_UIO_WRITE (DRX_CTRL_BASE + 37) /**< Write to UIO */
+#define DRX_CTRL_READ_EVENTS (DRX_CTRL_BASE + 38) /**< Read events */
+#define DRX_CTRL_HDL_EVENTS (DRX_CTRL_BASE + 39) /**< Handle events */
+#define DRX_CTRL_POWER_MODE (DRX_CTRL_BASE + 40) /**< Set power mode */
+#define DRX_CTRL_LOAD_FILTER (DRX_CTRL_BASE + 41) /**< Load chan. filter */
+#define DRX_CTRL_VALIDATE_UCODE (DRX_CTRL_BASE + 42) /**< Validate ucode */
+#define DRX_CTRL_DUMP_REGISTERS (DRX_CTRL_BASE + 43) /**< Dump registers */
+
+#define DRX_CTRL_MAX (DRX_CTRL_BASE + 44) /* never to be used */
+
+/**
+* \enum DRXUCodeAction_t
+* \brief Used to indicate if firmware has to be uploaded or verified.
+*/
+
+typedef enum {
+ UCODE_UPLOAD, /**< Upload the microcode image to device */
+ UCODE_VERIFY /**< Compare microcode image with code on device */
+} DRXUCodeAction_t, *pDRXUCodeAction_t;
+
+
+/**
+* \enum DRXLockStatus_t
+* \brief Used to reflect current lock status of demodulator.
+*
+* The generic lock states have device dependent semantics.
+*/
+typedef enum{
+ DRX_NEVER_LOCK = 0, /**< Device will never lock on this signal */
+ DRX_NOT_LOCKED, /**< Device has no lock at all */
+ DRX_LOCK_STATE_1, /**< Generic lock state */
+ DRX_LOCK_STATE_2, /**< Generic lock state */
+ DRX_LOCK_STATE_3, /**< Generic lock state */
+ DRX_LOCK_STATE_4, /**< Generic lock state */
+ DRX_LOCK_STATE_5, /**< Generic lock state */
+ DRX_LOCK_STATE_6, /**< Generic lock state */
+ DRX_LOCK_STATE_7, /**< Generic lock state */
+ DRX_LOCK_STATE_8, /**< Generic lock state */
+ DRX_LOCK_STATE_9, /**< Generic lock state */
+ DRX_LOCKED /**< Device is in lock */
+} DRXLockStatus_t, *pDRXLockStatus_t;
+
+/**
+* \enum DRXUIO_t
+* \brief Used to address a User IO (UIO).
+*/
+typedef enum{
+ DRX_UIO1 ,
+ DRX_UIO2 ,
+ DRX_UIO3 ,
+ DRX_UIO4 ,
+ DRX_UIO5 ,
+ DRX_UIO6 ,
+ DRX_UIO7 ,
+ DRX_UIO8 ,
+ DRX_UIO9 ,
+ DRX_UIO10 ,
+ DRX_UIO11 ,
+ DRX_UIO12 ,
+ DRX_UIO13 ,
+ DRX_UIO14 ,
+ DRX_UIO15 ,
+ DRX_UIO16 ,
+ DRX_UIO17 ,
+ DRX_UIO18 ,
+ DRX_UIO19 ,
+ DRX_UIO20 ,
+ DRX_UIO21 ,
+ DRX_UIO22 ,
+ DRX_UIO23 ,
+ DRX_UIO24 ,
+ DRX_UIO25 ,
+ DRX_UIO26 ,
+ DRX_UIO27 ,
+ DRX_UIO28 ,
+ DRX_UIO29 ,
+ DRX_UIO30 ,
+ DRX_UIO31 ,
+ DRX_UIO32 ,
+ DRX_UIO_MAX = DRX_UIO32
+} DRXUIO_t, *pDRXUIO_t;
+
+/**
+* \enum DRXUIOMode_t
+* \brief Used to configure the modus oprandi of a UIO.
+*
+* DRX_UIO_MODE_FIRMWARE is an old uio mode.
+* It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9.
+* To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to
+* DRX_UIO_MODE_FIRMWARE0.
+*/
+typedef enum{
+ DRX_UIO_MODE_DISABLE = 0x01, /**< not used, pin is configured as input */
+ DRX_UIO_MODE_READWRITE = 0x02, /**< used for read/write by application */
+ DRX_UIO_MODE_FIRMWARE = 0x04, /**< controlled by firmware, function 0 */
+ DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE , /**< same as above */
+ DRX_UIO_MODE_FIRMWARE1 = 0x08, /**< controlled by firmware, function 1 */
+ DRX_UIO_MODE_FIRMWARE2 = 0x10, /**< controlled by firmware, function 2 */
+ DRX_UIO_MODE_FIRMWARE3 = 0x20, /**< controlled by firmware, function 3 */
+ DRX_UIO_MODE_FIRMWARE4 = 0x40, /**< controlled by firmware, function 4 */
+ DRX_UIO_MODE_FIRMWARE5 = 0x80 /**< controlled by firmware, function 5 */
+} DRXUIOMode_t, *pDRXUIOMode_t;
+
+/**
+* \enum DRXOOBDownstreamStandard_t
+* \brief Used to select OOB standard.
+*
+* Based on ANSI 55-1 and 55-2
+*/
+typedef enum {
+ DRX_OOB_MODE_A = 0, /**< ANSI 55-1 */
+ DRX_OOB_MODE_B_GRADE_A, /**< ANSI 55-2 A */
+ DRX_OOB_MODE_B_GRADE_B /**< ANSI 55-2 B */
+} DRXOOBDownstreamStandard_t, *pDRXOOBDownstreamStandard_t;
+
+
+/*-------------------------------------------------------------------------
+STRUCTS
+-------------------------------------------------------------------------*/
+
+/*============================================================================*/
+/*============================================================================*/
+/*== CTRL CFG related data structures ========================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+/**
+* \enum DRXCfgType_t
+* \brief Generic configuration function identifiers.
+*/
+typedef u32_t DRXCfgType_t, *pDRXCfgType_t;
+
+#ifndef DRX_CFG_BASE
+#define DRX_CFG_BASE ((DRXCfgType_t)0)
+#endif
+
+#define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */
+#define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */
+#define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */
+#define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */
+#define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */
+#define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */
+#define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */
+#define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */
+#define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */
+#define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */
+#define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */
+#define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */
+#define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */
+#define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */
+#define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */
+#define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */
+#define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */
+#define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */
+#define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */
+
+#define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE
+/*============================================================================*/
+/*============================================================================*/
+/*== CTRL related data structures ============================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+/**
+* \struct DRXUCodeInfo_t
+* \brief Parameters for microcode upload and verfiy.
+*
+* Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
+*/
+typedef struct {
+ pu8_t mcData; /**< Pointer to microcode image. */
+ u16_t mcSize; /**< Microcode image size. */
+} DRXUCodeInfo_t, *pDRXUCodeInfo_t;
+
+/**
+* \struct DRXMcVersionRec_t
+* \brief Microcode version record
+* Version numbers are stored in BCD format, as usual:
+* o major number = bits 31-20 (first three nibbles of MSW)
+* o minor number = bits 19-16 (fourth nibble of MSW)
+* o patch number = bits 15-0 (remaining nibbles in LSW)
+*
+* The device type indicates for which the device is meant. It is based on the
+* JTAG ID, using everything except the bond ID and the metal fix.
+*
+* Special values:
+* - mcDevType == 0 => any device allowed
+* - mcBaseVersion == 0.0.0 => full microcode (mcVersion is the version)
+* - mcBaseVersion != 0.0.0 => patch microcode, the base microcode version
+* (mcVersion is the version)
+*/
+#define AUX_VER_RECORD 0x8000
+
+typedef struct {
+ u16_t auxType; /* type of aux data - 0x8000 for version record */
+ u32_t mcDevType; /* device type, based on JTAG ID */
+ u32_t mcVersion; /* version of microcode */
+ u32_t mcBaseVersion; /* in case of patch: the original microcode version */
+} DRXMcVersionRec_t, *pDRXMcVersionRec_t;
+
+/*========================================*/
+
+/**
+* \struct DRXFilterInfo_t
+* \brief Parameters for loading filter coefficients
+*
+* Used by DRX_CTRL_LOAD_FILTER
+*/
+typedef struct {
+ pu8_t dataRe; /**< pointer to coefficients for RE */
+ pu8_t dataIm; /**< pointer to coefficients for IM */
+ u16_t sizeRe; /**< size of coefficients for RE */
+ u16_t sizeIm; /**< size of coefficients for IM */
+} DRXFilterInfo_t, *pDRXFilterInfo_t;
+
+
+
+/*========================================*/
+
+/**
+* \struct DRXChannel_t
+* \brief The set of parameters describing a single channel.
+*
+* Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL.
+* Only certain fields need to be used for a specfic standard.
+*
+*/
+typedef struct {
+ DRXFrequency_t frequency; /**< frequency in kHz */
+ DRXBandwidth_t bandwidth; /**< bandwidth */
+ DRXMirror_t mirror; /**< mirrored or not on RF */
+ DRXConstellation_t constellation; /**< constellation */
+ DRXHierarchy_t hierarchy; /**< hierarchy */
+ DRXPriority_t priority; /**< priority */
+ DRXCoderate_t coderate; /**< coderate */
+ DRXGuard_t guard; /**< guard interval */
+ DRXFftmode_t fftmode; /**< fftmode */
+ DRXClassification_t classification; /**< classification */
+ DRXSymbolrate_t symbolrate; /**< symbolrate in symbols/sec */
+ DRXInterleaveModes_t interleavemode; /**< interleaveMode QAM */
+ DRXLDPC_t ldpc; /**< ldpc */
+ DRXCarrier_t carrier; /**< carrier */
+ DRXFramemode_t framemode; /**< frame mode */
+ DRXPilotMode_t pilot; /**< pilot mode */
+} DRXChannel_t, *pDRXChannel_t;
+
+/*========================================*/
+
+/**
+* \struct DRXSigQuality_t
+* Signal quality metrics.
+*
+* Used by DRX_CTRL_SIG_QUALITY.
+*/
+typedef struct {
+ u16_t MER; /**< in steps of 0.1 dB */
+ u32_t preViterbiBER ; /**< in steps of 1/scaleFactorBER */
+ u32_t postViterbiBER ; /**< in steps of 1/scaleFactorBER */
+ u32_t scaleFactorBER; /**< scale factor for BER */
+ u16_t packetError ; /**< number of packet errors */
+ u32_t postReedSolomonBER ; /**< in steps of 1/scaleFactorBER */
+ u32_t preLdpcBER; /**< in steps of 1/scaleFactorBER */
+ u32_t averIter; /**< in steps of 0.01 */
+ u16_t indicator; /**< indicative signal quality low=0..100=high */
+}DRXSigQuality_t, *pDRXSigQuality_t;
+
+
+typedef enum {
+ DRX_SQI_SPEED_FAST = 0,
+ DRX_SQI_SPEED_MEDIUM,
+ DRX_SQI_SPEED_SLOW,
+ DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
+} DRXCfgSqiSpeed_t, *pDRXCfgSqiSpeed_t;
+
+/*========================================*/
+
+/**
+* \struct DRXComplex_t
+* A complex number.
+*
+* Used by DRX_CTRL_CONSTEL.
+*/
+typedef struct {
+ s16_t im; /**< Imaginary part. */
+ s16_t re; /**< Real part. */
+} DRXComplex_t, *pDRXComplex_t;
+
+
+/*========================================*/
+
+/**
+* \struct DRXFrequencyPlan_t
+* Array element of a frequency plan.
+*
+* Used by DRX_CTRL_SCAN_INIT.
+*/
+typedef struct {
+ DRXFrequency_t first; /**< First centre frequency in this band */
+ DRXFrequency_t last; /**< Last centre frequency in this band */
+ DRXFrequency_t step; /**< Stepping frequency in this band */
+ DRXBandwidth_t bandwidth; /**< Bandwidth within this frequency band */
+ u16_t chNumber; /**< First channel number in this band, or first
+ index in chNames */
+ char **chNames; /**< Optional list of channel names in this
+ band */
+} DRXFrequencyPlan_t, *pDRXFrequencyPlan_t;
+
+/*========================================*/
+
+/**
+* \struct DRXFrequencyPlanInfo_t
+* Array element of a list of frequency plans.
+*
+* Used by frequency_plan.h
+*/
+typedef struct{
+ pDRXFrequencyPlan_t freqPlan;
+ int freqPlanSize;
+ char *freqPlanName;
+}DRXFrequencyPlanInfo_t, *pDRXFrequencyPlanInfo_t;
+
+/*========================================*/
+
+/**
+* /struct DRXScanDataQam_t
+* QAM specific scanning variables
+*/
+typedef struct {
+ pu32_t symbolrate; /**< list of symbolrates to scan */
+ u16_t symbolrateSize; /**< size of symbolrate array */
+ pDRXConstellation_t constellation; /**< list of constellations */
+ u16_t constellationSize; /**< size of constellation array */
+ u16_t ifAgcThreshold; /**< thresholf for IF-AGC based
+ scanning filter */
+} DRXScanDataQam_t, *pDRXScanDataQam_t;
+
+/*========================================*/
+
+/**
+* /struct DRXScanDataAtv_t
+* ATV specific scanning variables
+*/
+typedef struct {
+ s16_t svrThreshold; /**< threshold of Sound/Video ratio in 0.1dB steps */
+} DRXScanDataAtv_t, *pDRXScanDataAtv_t;
+
+/*========================================*/
+
+/**
+* \struct DRXScanParam_t
+* Parameters for channel scan.
+*
+* Used by DRX_CTRL_SCAN_INIT.
+*/
+typedef struct {
+ pDRXFrequencyPlan_t frequencyPlan; /**< Frequency plan (array)*/
+ u16_t frequencyPlanSize; /**< Number of bands */
+ u32_t numTries; /**< Max channels tried */
+ DRXFrequency_t skip; /**< Minimum frequency step to take
+ after a channel is found */
+ void *extParams; /**< Standard specific params */
+} DRXScanParam_t, *pDRXScanParam_t;
+
+/*========================================*/
+
+/**
+* \brief Scan commands.
+* Used by scanning algorithms.
+*/
+typedef enum {
+ DRX_SCAN_COMMAND_INIT = 0, /**< Initialize scanning */
+ DRX_SCAN_COMMAND_NEXT, /**< Next scan */
+ DRX_SCAN_COMMAND_STOP /**< Stop scanning */
+}DRXScanCommand_t, *pDRXScanCommand_t;
+
+/*========================================*/
+
+/**
+* \brief Inner scan function prototype.
+*/
+typedef DRXStatus_t (*DRXScanFunc_t) (void* scanContext,
+ DRXScanCommand_t scanCommand,
+ pDRXChannel_t scanChannel,
+ pBool_t getNextChannel);
+
+/*========================================*/
+
+/**
+* \struct DRXTPSInfo_t
+* TPS information, DVB-T specific.
+*
+* Used by DRX_CTRL_TPS_INFO.
+*/
+typedef struct {
+ DRXFftmode_t fftmode; /**< Fft mode */
+ DRXGuard_t guard; /**< Guard interval */
+ DRXConstellation_t constellation; /**< Constellation */
+ DRXHierarchy_t hierarchy; /**< Hierarchy */
+ DRXCoderate_t highCoderate; /**< High code rate */
+ DRXCoderate_t lowCoderate; /**< Low cod rate */
+ DRXTPSFrame_t frame; /**< Tps frame */
+ u8_t length; /**< Length */
+ u16_t cellId; /**< Cell id */
+}DRXTPSInfo_t, *pDRXTPSInfo_t;
+
+/*========================================*/
+
+/**
+* \brief Power mode of device.
+*
+* Used by DRX_CTRL_SET_POWER_MODE.
+*/
+typedef enum {
+ DRX_POWER_UP = 0, /**< Generic , Power Up Mode */
+ DRX_POWER_MODE_1, /**< Device specific , Power Up Mode */
+ DRX_POWER_MODE_2, /**< Device specific , Power Up Mode */
+ DRX_POWER_MODE_3, /**< Device specific , Power Up Mode */
+ DRX_POWER_MODE_4, /**< Device specific , Power Up Mode */
+ DRX_POWER_MODE_5, /**< Device specific , Power Up Mode */
+ DRX_POWER_MODE_6, /**< Device specific , Power Up Mode */
+ DRX_POWER_MODE_7, /**< Device specific , Power Up Mode */
+ DRX_POWER_MODE_8, /**< Device specific , Power Up Mode */
+
+ DRX_POWER_MODE_9, /**< Device specific , Power Down Mode */
+ DRX_POWER_MODE_10, /**< Device specific , Power Down Mode */
+ DRX_POWER_MODE_11, /**< Device specific , Power Down Mode */
+ DRX_POWER_MODE_12, /**< Device specific , Power Down Mode */
+ DRX_POWER_MODE_13, /**< Device specific , Power Down Mode */
+ DRX_POWER_MODE_14, /**< Device specific , Power Down Mode */
+ DRX_POWER_MODE_15, /**< Device specific , Power Down Mode */
+ DRX_POWER_MODE_16, /**< Device specific , Power Down Mode */
+ DRX_POWER_DOWN = 255 /**< Generic , Power Down Mode */
+}DRXPowerMode_t, *pDRXPowerMode_t;
+
+/*========================================*/
+
+/**
+* \enum DRXModule_t
+* \brief Software module identification.
+*
+* Used by DRX_CTRL_VERSION.
+*/
+typedef enum {
+ DRX_MODULE_DEVICE,
+ DRX_MODULE_MICROCODE,
+ DRX_MODULE_DRIVERCORE,
+ DRX_MODULE_DEVICEDRIVER,
+ DRX_MODULE_DAP,
+ DRX_MODULE_BSP_I2C,
+ DRX_MODULE_BSP_TUNER,
+ DRX_MODULE_BSP_HOST,
+ DRX_MODULE_UNKNOWN
+} DRXModule_t, *pDRXModule_t;
+
+
+/**
+* \enum DRXVersion_t
+* \brief Version information of one software module.
+*
+* Used by DRX_CTRL_VERSION.
+*/
+typedef struct {
+ DRXModule_t moduleType; /**< Type identifier of the module */
+ char *moduleName; /**< Name or description of module */
+ u16_t vMajor; /**< Major version number */
+ u16_t vMinor; /**< Minor version number */
+ u16_t vPatch; /**< Patch version number */
+ char *vString; /**< Version as text string */
+} DRXVersion_t, *pDRXVersion_t;
+
+/**
+* \enum DRXVersionList_t
+* \brief List element of NULL terminated, linked list for version information.
+*
+* Used by DRX_CTRL_VERSION.
+*/
+typedef struct DRXVersionList_s {
+ pDRXVersion_t version; /**< Version information */
+ struct DRXVersionList_s *next; /**< Next list element */
+} DRXVersionList_t, *pDRXVersionList_t;
+
+/*========================================*/
+
+/**
+* \brief Parameters needed to confiugure a UIO.
+*
+* Used by DRX_CTRL_UIO_CFG.
+*/
+typedef struct {
+ DRXUIO_t uio; /**< UIO identifier */
+ DRXUIOMode_t mode; /**< UIO operational mode */
+} DRXUIOCfg_t, *pDRXUIOCfg_t;
+
+/*========================================*/
+
+/**
+* \brief Parameters needed to read from or write to a UIO.
+*
+* Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE.
+*/
+typedef struct {
+ DRXUIO_t uio; /**< UIO identifier */
+ Bool_t value; /**< UIO value (TRUE=1, FALSE=0) */
+} DRXUIOData_t, *pDRXUIOData_t;
+
+/*========================================*/
+
+/**
+* \brief Parameters needed to configure OOB.
+*
+* Used by DRX_CTRL_SET_OOB.
+*/
+typedef struct {
+ DRXFrequency_t frequency; /**< Frequency in kHz */
+ DRXOOBDownstreamStandard_t standard; /**< OOB standard */
+ Bool_t spectrumInverted; /**< If TRUE, then spectrum
+ is inverted */
+} DRXOOB_t, *pDRXOOB_t;
+
+
+/*========================================*/
+
+/**
+* \brief Metrics from OOB.
+*
+* Used by DRX_CTRL_GET_OOB.
+*/
+typedef struct {
+ DRXFrequency_t frequency; /**< Frequency in Khz */
+ DRXLockStatus_t lock; /**< Lock status */
+ u32_t mer; /**< MER */
+ s32_t symbolRateOffset; /**< Symbolrate offset in ppm */
+} DRXOOBStatus_t, *pDRXOOBStatus_t;
+
+
+/*========================================*/
+
+/**
+* \brief Device dependent configuration data.
+*
+* Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG.
+* A sort of nested DRX_Ctrl() functionality for device specific controls.
+*/
+typedef struct {
+ DRXCfgType_t cfgType ; /**< Function identifier */
+ void* cfgData ; /**< Function data */
+} DRXCfg_t, *pDRXCfg_t;
+
+/*========================================*/
+
+/**
+* /struct DRXMpegStartWidth_t
+* MStart width [nr MCLK cycles] for serial MPEG output.
+*/
+
+typedef enum {
+ DRX_MPEG_STR_WIDTH_1,
+ DRX_MPEG_STR_WIDTH_8
+} DRXMPEGStrWidth_t, *pDRXMPEGStrWidth_t;
+
+
+/* CTRL CFG MPEG ouput */
+/**
+* \struct DRXCfgMPEGOutput_t
+* \brief Configuartion parameters for MPEG output control.
+*
+* Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and
+* DRX_CTRL_GET_CFG.
+*/
+
+typedef struct {
+ Bool_t enableMPEGOutput; /**< If TRUE, enable MPEG output */
+ Bool_t insertRSByte; /**< If TRUE, insert RS byte */
+ Bool_t enableParallel; /**< If TRUE, parallel out otherwise
+ serial */
+ Bool_t invertDATA; /**< If TRUE, invert DATA signals */
+ Bool_t invertERR; /**< If TRUE, invert ERR signal */
+ Bool_t invertSTR; /**< If TRUE, invert STR signals */
+ Bool_t invertVAL; /**< If TRUE, invert VAL signals */
+ Bool_t invertCLK; /**< If TRUE, invert CLK signals */
+ Bool_t staticCLK; /**< If TRUE, static MPEG clockrate
+ will be used, otherwise clockrate
+ will adapt to the bitrate of the
+ TS */
+ u32_t bitrate; /**< Maximum bitrate in b/s in case
+ static clockrate is selected */
+ DRXMPEGStrWidth_t widthSTR; /**< MPEG start width */
+} DRXCfgMPEGOutput_t, *pDRXCfgMPEGOutput_t;
+
+/* CTRL CFG SMA */
+/**
+* /struct DRXCfgSMAIO_t
+* smart antenna i/o.
+*/
+typedef enum DRXCfgSMAIO_t {
+ DRX_SMA_OUTPUT = 0,
+ DRX_SMA_INPUT
+} DRXCfgSMAIO_t, *pDRXCfgSMAIO_t;
+
+/**
+* /struct DRXCfgSMA_t
+* Set smart antenna.
+*/
+typedef struct {
+ DRXCfgSMAIO_t io;
+ u16_t ctrlData;
+ Bool_t smartAntInverted;
+} DRXCfgSMA_t, *pDRXCfgSMA_t;
+
+/*========================================*/
+
+/**
+* \struct DRXI2CData_t
+* \brief Data for I2C via 2nd or 3rd or etc I2C port.
+*
+* Used by DRX_CTRL_I2C_READWRITE.
+* If portNr is equal to primairy portNr BSPI2C will be used.
+*
+*/
+typedef struct {
+ u16_t portNr; /**< I2C port number */
+ pI2CDeviceAddr_t wDevAddr; /**< Write device address */
+ u16_t wCount; /**< Size of write data in bytes */
+ pu8_t wData; /**< Pointer to write data */
+ pI2CDeviceAddr_t rDevAddr; /**< Read device address */
+ u16_t rCount; /**< Size of data to read in bytes */
+ pu8_t rData; /**< Pointer to read buffer */
+} DRXI2CData_t, *pDRXI2CData_t;
+
+/*========================================*/
+
+/**
+* \enum DRXAudStandard_t
+* \brief Audio standard identifier.
+*
+* Used by DRX_CTRL_SET_AUD.
+*/
+typedef enum {
+ DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */
+ DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */
+ DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */
+ DRX_AUD_STANDARD_FM_STEREO, /**< set to FM-Stereo Radio */
+ DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */
+ DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */
+ DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */
+ DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */
+ DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */
+ DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */
+ DRX_AUD_STANDARD_BG_NICAM_FM, /**< set BG_NICAM_FM standard */
+ DRX_AUD_STANDARD_L_NICAM_AM, /**< set L_NICAM_AM standard */
+ DRX_AUD_STANDARD_I_NICAM_FM, /**< set I_NICAM_FM standard */
+ DRX_AUD_STANDARD_D_K_NICAM_FM, /**< set D_K_NICAM_FM standard */
+ DRX_AUD_STANDARD_NOT_READY, /**< used to detect audio standard */
+ DRX_AUD_STANDARD_AUTO = DRX_AUTO, /**< Automatic Standard Detection */
+ DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN /**< used as auto and for readback */
+} DRXAudStandard_t, *pDRXAudStandard_t;
+
+/* CTRL_AUD_GET_STATUS - DRXAudStatus_t */
+/**
+* \enum DRXAudNICAMStatus_t
+* \brief Status of NICAM carrier.
+*/
+typedef enum {
+ DRX_AUD_NICAM_DETECTED = 0, /**< NICAM carrier detected */
+ DRX_AUD_NICAM_NOT_DETECTED, /**< NICAM carrier not detected */
+ DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */
+} DRXAudNICAMStatus_t, *pDRXAudNICAMStatus_t;
+
+/**
+* \struct DRXAudStatus_t
+* \brief Audio status characteristics.
+*/
+typedef struct {
+ Bool_t stereo; /**< stereo detection */
+ Bool_t carrierA; /**< carrier A detected */
+ Bool_t carrierB; /**< carrier B detected */
+ Bool_t sap; /**< sap / bilingual detection */
+ Bool_t rds; /**< RDS data array present */
+ DRXAudNICAMStatus_t nicamStatus; /**< status of NICAM carrier */
+ s8_t fmIdent; /**< FM Identification value */
+} DRXAudStatus_t, *pDRXAudStatus_t;
+
+/* CTRL_AUD_READ_RDS - DRXRDSdata_t */
+
+/**
+* \struct DRXRDSdata_t
+* \brief Raw RDS data array.
+*/
+typedef struct {
+ Bool_t valid; /**< RDS data validation */
+ u16_t data[18]; /**< data from one RDS data array */
+} DRXCfgAudRDS_t, *pDRXCfgAudRDS_t;
+
+/* DRX_CFG_AUD_VOLUME - DRXCfgAudVolume_t - set/get */
+/**
+* \enum DRXAudAVCDecayTime_t
+* \brief Automatic volume control configuration.
+*/
+typedef enum {
+ DRX_AUD_AVC_OFF, /**< Automatic volume control off */
+ DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */
+ DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */
+ DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */
+ DRX_AUD_AVC_DECAYTIME_20MS /**< level volume in 20 millisec */
+} DRXAudAVCMode_t, *pDRXAudAVCMode_t;
+
+/**
+* /enum DRXAudMaxAVCGain_t
+* /brief Automatic volume control max gain in audio baseband.
+*/
+typedef enum {
+ DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */
+ DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */
+ DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */
+} DRXAudAVCMaxGain_t, *pDRXAudAVCMaxGain_t;
+
+/**
+* /enum DRXAudMaxAVCAtten_t
+* /brief Automatic volume control max attenuation in audio baseband.
+*/
+typedef enum {
+ DRX_AUD_AVC_MAX_ATTEN_12DB, /**< maximum AVC attenuation 12 dB */
+ DRX_AUD_AVC_MAX_ATTEN_18DB, /**< maximum AVC attenuation 18 dB */
+ DRX_AUD_AVC_MAX_ATTEN_24DB /**< maximum AVC attenuation 24 dB */
+} DRXAudAVCMaxAtten_t, *pDRXAudAVCMaxAtten_t;
+/**
+* \struct DRXCfgAudVolume_t
+* \brief Audio volume configuration.
+*/
+typedef struct {
+ Bool_t mute; /**< mute overrides volume setting */
+ s16_t volume; /**< volume, range -114 to 12 dB */
+ DRXAudAVCMode_t avcMode; /**< AVC auto volume control mode */
+ u16_t avcRefLevel; /**< AVC reference level */
+ DRXAudAVCMaxGain_t avcMaxGain; /**< AVC max gain selection */
+ DRXAudAVCMaxAtten_t avcMaxAtten; /**< AVC max attenuation selection */
+ s16_t strengthLeft; /**< quasi-peak, left speaker */
+ s16_t strengthRight; /**< quasi-peak, right speaker */
+} DRXCfgAudVolume_t, *pDRXCfgAudVolume_t;
+
+/* DRX_CFG_I2S_OUTPUT - DRXCfgI2SOutput_t - set/get */
+/**
+* \enum DRXI2SMode_t
+* \brief I2S output mode.
+*/
+typedef enum {
+ DRX_I2S_MODE_MASTER, /**< I2S is in master mode */
+ DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */
+} DRXI2SMode_t, *pDRXI2SMode_t;
+
+/**
+* \enum DRXI2SWordLength_t
+* \brief Width of I2S data.
+*/
+typedef enum {
+ DRX_I2S_WORDLENGTH_32 = 0, /**< I2S data is 32 bit wide */
+ DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */
+} DRXI2SWordLength_t, *pDRXI2SWordLength_t;
+
+/**
+* \enum DRXI2SFormat_t
+* \brief Data wordstrobe alignment for I2S.
+*/
+typedef enum {
+ DRX_I2S_FORMAT_WS_WITH_DATA, /**< I2S data and wordstrobe are aligned */
+ DRX_I2S_FORMAT_WS_ADVANCED /**< I2S data one cycle after wordstrobe */
+} DRXI2SFormat_t, *pDRXI2SFormat_t;
+
+/**
+* \enum DRXI2SPolarity_t
+* \brief Polarity of I2S data.
+*/
+typedef enum {
+ DRX_I2S_POLARITY_RIGHT, /**< wordstrobe - right high, left low */
+ DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */
+} DRXI2SPolarity_t, *pDRXI2SPolarity_t;
+
+
+
+/**
+* \struct DRXCfgI2SOutput_t
+* \brief I2S output configuration.
+*/
+typedef struct {
+ Bool_t outputEnable; /**< I2S output enable */
+ u32_t frequency; /**< range from 8000-48000 Hz */
+ DRXI2SMode_t mode; /**< I2S mode, master or slave */
+ DRXI2SWordLength_t wordLength; /**< I2S wordlength, 16 or 32 bits */
+ DRXI2SPolarity_t polarity; /**< I2S wordstrobe polarity */
+ DRXI2SFormat_t format; /**< I2S wordstrobe delay to data */
+} DRXCfgI2SOutput_t, *pDRXCfgI2SOutput_t;
+
+
+/* ------------------------------expert interface-----------------------------*/
+/**
+* /enum DRXAudFMDeemphasis_t
+* setting for FM-Deemphasis in audio demodulator.
+*
+*/
+typedef enum {
+ DRX_AUD_FM_DEEMPH_50US,
+ DRX_AUD_FM_DEEMPH_75US,
+ DRX_AUD_FM_DEEMPH_OFF
+} DRXAudFMDeemphasis_t, *pDRXAudFMDeemphasis_t;
+
+/**
+* /enum DRXAudDeviation_t
+* setting for deviation mode in audio demodulator.
+*
+*/
+typedef enum {
+ DRX_AUD_DEVIATION_NORMAL,
+ DRX_AUD_DEVIATION_HIGH
+} DRXCfgAudDeviation_t, *pDRXCfgAudDeviation_t;
+
+/**
+* /enum DRXNoCarrierOption_t
+* setting for carrier, mute/noise.
+*
+*/
+typedef enum {
+ DRX_NO_CARRIER_MUTE,
+ DRX_NO_CARRIER_NOISE
+} DRXNoCarrierOption_t, *pDRXNoCarrierOption_t;
+
+
+/**
+* \enum DRXAudAutoSound_t
+* \brief Automatic Sound
+*/
+typedef enum {
+ DRX_AUD_AUTO_SOUND_OFF = 0,
+ DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
+ DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
+} DRXCfgAudAutoSound_t, *pDRXCfgAudAutoSound_t;
+
+/**
+* \enum DRXAudASSThres_t
+* \brief Automatic Sound Select Thresholds
+*/
+typedef struct {
+ u16_t a2; /* A2 Threshold for ASS configuration */
+ u16_t btsc; /* BTSC Threshold for ASS configuration */
+ u16_t nicam; /* Nicam Threshold for ASS configuration */
+} DRXCfgAudASSThres_t, *pDRXCfgAudASSThres_t;
+
+/**
+* \struct DRXAudCarrier_t
+* \brief Carrier detection related parameters
+*/
+typedef struct {
+ u16_t thres; /* carrier detetcion threshold for primary carrier (A) */
+ DRXNoCarrierOption_t opt; /* Mute or noise at no carrier detection (A) */
+ DRXFrequency_t shift; /* DC level of incoming signal (A) */
+ DRXFrequency_t dco; /* frequency adjustment (A) */
+} DRXAudCarrier_t, *pDRXCfgAudCarrier_t;
+
+/**
+* \struct DRXCfgAudCarriers_t
+* \brief combining carrier A & B to one struct
+*/
+typedef struct {
+ DRXAudCarrier_t a;
+ DRXAudCarrier_t b;
+} DRXCfgAudCarriers_t, *pDRXCfgAudCarriers_t;
+
+/**
+* /enum DRXAudI2SSrc_t
+* Selection of audio source
+*/
+typedef enum {
+ DRX_AUD_SRC_MONO,
+ DRX_AUD_SRC_STEREO_OR_AB,
+ DRX_AUD_SRC_STEREO_OR_A,
+ DRX_AUD_SRC_STEREO_OR_B
+} DRXAudI2SSrc_t, *pDRXAudI2SSrc_t;
+
+
+/**
+* \enum DRXAudI2SMatrix_t
+* \brief Used for selecting I2S output.
+*/
+typedef enum {
+ DRX_AUD_I2S_MATRIX_A_MONO, /**< A sound only, stereo or mono */
+ DRX_AUD_I2S_MATRIX_B_MONO, /**< B sound only, stereo or mono */
+ DRX_AUD_I2S_MATRIX_STEREO, /**< A+B sound, transparant */
+ DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */
+} DRXAudI2SMatrix_t, *pDRXAudI2SMatrix_t;
+
+
+/**
+* /enum DRXAudFMMatrix_t
+* setting for FM-Matrix in audio demodulator.
+*
+*/
+typedef enum {
+ DRX_AUD_FM_MATRIX_NO_MATRIX,
+ DRX_AUD_FM_MATRIX_GERMAN,
+ DRX_AUD_FM_MATRIX_KOREAN,
+ DRX_AUD_FM_MATRIX_SOUND_A,
+ DRX_AUD_FM_MATRIX_SOUND_B
+} DRXAudFMMatrix_t, *pDRXAudFMMatrix_t;
+
+/**
+* \struct DRXAudMatrices_t
+* \brief Mixer settings
+*/
+typedef struct {
+ DRXAudI2SSrc_t sourceI2S;
+ DRXAudI2SMatrix_t matrixI2S;
+ DRXAudFMMatrix_t matrixFm;
+} DRXCfgAudMixer_t, *pDRXCfgAudMixer_t;
+
+/**
+* \enum DRXI2SVidSync_t
+* \brief Audio/video synchronization, interacts with I2S mode.
+* AUTO_1 and AUTO_2 are for automatic video standard detection with preference
+* for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz)
+*/
+typedef enum {
+ DRX_AUD_AVSYNC_OFF, /**< audio/video synchronization is off */
+ DRX_AUD_AVSYNC_NTSC, /**< it is an NTSC system */
+ DRX_AUD_AVSYNC_MONOCHROME, /**< it is a MONOCHROME system */
+ DRX_AUD_AVSYNC_PAL_SECAM /**< it is a PAL/SECAM system */
+} DRXCfgAudAVSync_t, *pDRXCfgAudAVSync_t;
+
+/**
+* \struct DRXCfgAudPrescale_t
+* \brief Prescalers
+*/
+typedef struct {
+ u16_t fmDeviation;
+ s16_t nicamGain;
+} DRXCfgAudPrescale_t, *pDRXCfgAudPrescale_t;
+
+/**
+* \struct DRXAudBeep_t
+* \brief Beep
+*/
+typedef struct {
+ s16_t volume; /* dB */
+ u16_t frequency; /* Hz */
+ Bool_t mute;
+} DRXAudBeep_t, *pDRXAudBeep_t;
+
+
+/**
+* \enum DRXAudBtscDetect_t
+* \brief BTSC detetcion mode
+*/
+typedef enum {
+ DRX_BTSC_STEREO,
+ DRX_BTSC_MONO_AND_SAP
+} DRXAudBtscDetect_t, *pDRXAudBtscDetect_t;
+
+/**
+* \struct DRXAudData_t
+* \brief Audio data structure
+*/
+typedef struct
+{
+ /* audio storage */
+ Bool_t audioIsActive;
+ DRXAudStandard_t audioStandard;
+ DRXCfgI2SOutput_t i2sdata;
+ DRXCfgAudVolume_t volume;
+ DRXCfgAudAutoSound_t autoSound;
+ DRXCfgAudASSThres_t assThresholds;
+ DRXCfgAudCarriers_t carriers;
+ DRXCfgAudMixer_t mixer;
+ DRXCfgAudDeviation_t deviation;
+ DRXCfgAudAVSync_t avSync;
+ DRXCfgAudPrescale_t prescale;
+ DRXAudFMDeemphasis_t deemph;
+ DRXAudBtscDetect_t btscDetect;
+ /* rds */
+ u16_t rdsDataCounter;
+ Bool_t rdsDataPresent;
+} DRXAudData_t, *pDRXAudData_t;
+
+
+/**
+* \enum DRXQamLockRange_t
+* \brief QAM lock range mode
+*/
+typedef enum
+{
+ DRX_QAM_LOCKRANGE_NORMAL,
+ DRX_QAM_LOCKRANGE_EXTENDED
+}DRXQamLockRange_t, *pDRXQamLockRange_t;
+
+/*============================================================================*/
+/*============================================================================*/
+/*== Data access structures ==================================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+/* Address on device */
+typedef u32_t DRXaddr_t, *pDRXaddr_t;
+
+/* Protocol specific flags */
+typedef u32_t DRXflags_t, *pDRXflags_t;
+
+/* Write block of data to device */
+typedef DRXStatus_t (*DRXWriteBlockFunc_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ u16_t datasize, /* size of data in bytes */
+ pu8_t data, /* data to send */
+ DRXflags_t flags);
+
+/* Read block of data from device */
+typedef DRXStatus_t (*DRXReadBlockFunc_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ u16_t datasize, /* size of data in bytes */
+ pu8_t data, /* receive buffer */
+ DRXflags_t flags);
+
+/* Write 8-bits value to device */
+typedef DRXStatus_t (*DRXWriteReg8Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ u8_t data, /* data to send */
+ DRXflags_t flags);
+
+/* Read 8-bits value to device */
+typedef DRXStatus_t (*DRXReadReg8Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ pu8_t data, /* receive buffer */
+ DRXflags_t flags);
+
+/* Read modify write 8-bits value to device */
+typedef DRXStatus_t (*DRXReadModifyWriteReg8Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t waddr, /* write address of register */
+ DRXaddr_t raddr, /* read address of register */
+ u8_t wdata, /* data to write */
+ pu8_t rdata); /* data to read */
+
+/* Write 16-bits value to device */
+typedef DRXStatus_t (*DRXWriteReg16Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ u16_t data, /* data to send */
+ DRXflags_t flags);
+
+/* Read 16-bits value to device */
+typedef DRXStatus_t (*DRXReadReg16Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ pu16_t data, /* receive buffer */
+ DRXflags_t flags);
+
+/* Read modify write 16-bits value to device */
+typedef DRXStatus_t (*DRXReadModifyWriteReg16Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t waddr, /* write address of register */
+ DRXaddr_t raddr, /* read address of register */
+ u16_t wdata, /* data to write */
+ pu16_t rdata); /* data to read */
+
+/* Write 32-bits value to device */
+typedef DRXStatus_t (*DRXWriteReg32Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ u32_t data, /* data to send */
+ DRXflags_t flags);
+
+/* Read 32-bits value to device */
+typedef DRXStatus_t (*DRXReadReg32Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t addr, /* address of register/memory */
+ pu32_t data, /* receive buffer */
+ DRXflags_t flags);
+
+/* Read modify write 32-bits value to device */
+typedef DRXStatus_t (*DRXReadModifyWriteReg32Func_t) (
+ pI2CDeviceAddr_t devAddr, /* address of I2C device */
+ DRXaddr_t waddr, /* write address of register */
+ DRXaddr_t raddr, /* read address of register */
+ u32_t wdata, /* data to write */
+ pu32_t rdata); /* data to read */
+
+/**
+* \struct DRXAccessFunc_t
+* \brief Interface to an access protocol.
+*/
+typedef struct {
+ pDRXVersion_t protocolVersion;
+ DRXWriteBlockFunc_t writeBlockFunc;
+ DRXReadBlockFunc_t readBlockFunc;
+ DRXWriteReg8Func_t writeReg8Func;
+ DRXReadReg8Func_t readReg8Func;
+ DRXReadModifyWriteReg8Func_t readModifyWriteReg8Func;
+ DRXWriteReg16Func_t writeReg16Func;
+ DRXReadReg16Func_t readReg16Func;
+ DRXReadModifyWriteReg16Func_t readModifyWriteReg16Func;
+ DRXWriteReg32Func_t writeReg32Func;
+ DRXReadReg32Func_t readReg32Func;
+ DRXReadModifyWriteReg32Func_t readModifyWriteReg32Func;
+} DRXAccessFunc_t, *pDRXAccessFunc_t;
+
+/* Register address and data for register dump function */
+typedef struct {
+
+ DRXaddr_t address;
+ u32_t data;
+
+} DRXRegDump_t, *pDRXRegDump_t ;
+
+/*============================================================================*/
+/*============================================================================*/
+/*== Demod instance data structures ==========================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+/**
+* \struct DRXCommonAttr_t
+* \brief Set of common attributes, shared by all DRX devices.
+*/
+typedef struct {
+ /* Microcode (firmware) attributes */
+ pu8_t microcode; /**< Pointer to microcode image. */
+ u16_t microcodeSize; /**< Size of microcode image in bytes. */
+ Bool_t verifyMicrocode; /**< Use microcode verify or not. */
+ DRXMcVersionRec_t mcversion; /**< Version record of microcode from file */
+
+ /* Clocks and tuner attributes */
+ DRXFrequency_t intermediateFreq; /**< IF,if tuner instance not used. (kHz)*/
+ DRXFrequency_t sysClockFreq; /**< Systemclock frequency. (kHz) */
+ DRXFrequency_t oscClockFreq; /**< Oscillator clock frequency. (kHz) */
+ s16_t oscClockDeviation; /**< Oscillator clock deviation. (ppm) */
+ Bool_t mirrorFreqSpect; /**< Mirror IF frequency spectrum or not.*/
+
+ /* Initial MPEG output attributes */
+ DRXCfgMPEGOutput_t mpegCfg; /**< MPEG configuration */
+
+ Bool_t isOpened; /**< if TRUE instance is already opened. */
+
+ /* Channel scan */
+ pDRXScanParam_t scanParam; /**< scan parameters */
+ u16_t scanFreqPlanIndex; /**< next index in freq plan */
+ DRXFrequency_t scanNextFrequency; /**< next freq to scan */
+ Bool_t scanReady; /**< scan ready flag */
+ u32_t scanMaxChannels; /**< number of channels in freqplan */
+ u32_t scanChannelsScanned; /**< number of channels scanned */
+ /* Channel scan - inner loop: demod related */
+ DRXScanFunc_t scanFunction; /**< function to check channel */
+ /* Channel scan - inner loop: SYSObj related */
+ void* scanContext; /**< Context Pointer of SYSObj */
+ /* Channel scan - parameters for default DTV scan function in core driver */
+ u16_t scanDemodLockTimeout; /**< millisecs to wait for lock */
+ DRXLockStatus_t scanDesiredLock; /**< lock requirement for channel found */
+ /* scanActive can be used by SetChannel to decide how to program the tuner,
+ fast or slow (but stable). Usually fast during scan. */
+ Bool_t scanActive; /**< TRUE when scan routines are active */
+
+ /* Power management */
+ DRXPowerMode_t currentPowerMode; /**< current power management mode */
+
+ /* Tuner */
+ u8_t tunerPortNr; /**< nr of I2C port to wich tuner is */
+ DRXFrequency_t tunerMinFreqRF; /**< minimum RF input frequency, in kHz */
+ DRXFrequency_t tunerMaxFreqRF; /**< maximum RF input frequency, in kHz */
+ Bool_t tunerRfAgcPol; /**< if TRUE invert RF AGC polarity */
+ Bool_t tunerIfAgcPol; /**< if TRUE invert IF AGC polarity */
+ Bool_t tunerSlowMode; /**< if TRUE invert IF AGC polarity */
+
+ DRXChannel_t currentChannel; /**< current channel parameters */
+ DRXStandard_t currentStandard; /**< current standard selection */
+ DRXStandard_t prevStandard; /**< previous standard selection */
+ DRXStandard_t diCacheStandard; /**< standard in DI cache if available */
+ Bool_t useBootloader; /**< use bootloader in open */
+ u32_t capabilities; /**< capabilities flags */
+ u32_t productId; /**< product ID inc. metal fix number */
+
+} DRXCommonAttr_t, *pDRXCommonAttr_t;
+
+
+/*
+* Generic functions for DRX devices.
+*/
+typedef struct DRXDemodInstance_s *pDRXDemodInstance_t;
+
+typedef DRXStatus_t (*DRXOpenFunc_t) (pDRXDemodInstance_t demod);
+typedef DRXStatus_t (*DRXCloseFunc_t) (pDRXDemodInstance_t demod);
+typedef DRXStatus_t (*DRXCtrlFunc_t) (pDRXDemodInstance_t demod,
+ DRXCtrlIndex_t ctrl,
+ void *ctrlData);
+
+/**
+* \struct DRXDemodFunc_t
+* \brief A stucture containing all functions of a demodulator.
+*/
+typedef struct {
+ u32_t typeId; /**< Device type identifier. */
+ DRXOpenFunc_t openFunc; /**< Pointer to Open() function. */
+ DRXCloseFunc_t closeFunc; /**< Pointer to Close() function. */
+ DRXCtrlFunc_t ctrlFunc; /**< Pointer to Ctrl() function. */
+} DRXDemodFunc_t, *pDRXDemodFunc_t;
+
+/**
+* \struct DRXDemodInstance_t
+* \brief Top structure of demodulator instance.
+*/
+typedef struct DRXDemodInstance_s {
+ /* type specific demodulator data */
+ pDRXDemodFunc_t myDemodFunct; /**< demodulator functions */
+ pDRXAccessFunc_t myAccessFunct; /**< data access protocol functions */
+ pTUNERInstance_t myTuner; /**< tuner instance,if NULL then baseband */
+ pI2CDeviceAddr_t myI2CDevAddr; /**< i2c address and device identifier */
+ pDRXCommonAttr_t myCommonAttr; /**< common DRX attributes */
+ void* myExtAttr; /**< device specific attributes */
+ /* generic demodulator data */
+} DRXDemodInstance_t;
+
+
+
+/*-------------------------------------------------------------------------
+MACROS
+Conversion from enum values to human readable form.
+-------------------------------------------------------------------------*/
+
+/* standard */
+
+#define DRX_STR_STANDARD(x) (\
+ (x == DRX_STANDARD_DVBT) ? "DVB-T" : \
+ (x == DRX_STANDARD_8VSB) ? "8VSB" : \
+ (x == DRX_STANDARD_NTSC) ? "NTSC" : \
+ (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \
+ (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \
+ (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \
+ (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \
+ (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \
+ (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \
+ (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \
+ (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \
+ (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \
+ (x == DRX_STANDARD_FM) ? "FM" : \
+ (x == DRX_STANDARD_DTMB) ? "DTMB" : \
+ (x == DRX_STANDARD_AUTO) ? "Auto" : \
+ (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+
+/* channel */
+
+#define DRX_STR_BANDWIDTH(x) (\
+ (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \
+ (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \
+ (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \
+ (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \
+ (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_FFTMODE(x) (\
+ (x == DRX_FFTMODE_2K) ? "2k" : \
+ (x == DRX_FFTMODE_4K) ? "4k" : \
+ (x == DRX_FFTMODE_8K) ? "8k" : \
+ (x == DRX_FFTMODE_AUTO) ? "Auto" : \
+ (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_GUARD(x) (\
+ (x == DRX_GUARD_1DIV32) ? "1/32nd" : \
+ (x == DRX_GUARD_1DIV16) ? "1/16th" : \
+ (x == DRX_GUARD_1DIV8) ? "1/8th" : \
+ (x == DRX_GUARD_1DIV4) ? "1/4th" : \
+ (x == DRX_GUARD_AUTO) ? "Auto" : \
+ (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_CONSTELLATION(x) (\
+ (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \
+ (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \
+ (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \
+ (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \
+ (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \
+ (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \
+ (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \
+ (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \
+ (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \
+ (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \
+ (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \
+ (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \
+ (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_CODERATE(x) (\
+ (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \
+ (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \
+ (x == DRX_CODERATE_3DIV4) ? "3/4th" : \
+ (x == DRX_CODERATE_5DIV6) ? "5/6th" : \
+ (x == DRX_CODERATE_7DIV8) ? "7/8th" : \
+ (x == DRX_CODERATE_AUTO) ? "Auto" : \
+ (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_HIERARCHY(x) (\
+ (x == DRX_HIERARCHY_NONE) ? "None" : \
+ (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \
+ (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \
+ (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \
+ (x == DRX_HIERARCHY_AUTO) ? "Auto" : \
+ (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_PRIORITY(x) (\
+ (x == DRX_PRIORITY_LOW) ? "Low" : \
+ (x == DRX_PRIORITY_HIGH) ? "High" : \
+ (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_MIRROR(x) (\
+ (x == DRX_MIRROR_NO) ? "Normal" : \
+ (x == DRX_MIRROR_YES) ? "Mirrored" : \
+ (x == DRX_MIRROR_AUTO) ? "Auto" : \
+ (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_CLASSIFICATION(x) (\
+ (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \
+ (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \
+ (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \
+ (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \
+ (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \
+ (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \
+ (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \
+ (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \
+ "(Invalid)")
+
+#define DRX_STR_INTERLEAVEMODE(x) (\
+ (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \
+ (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \
+ (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \
+ (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \
+ (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \
+ (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \
+ (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \
+ (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \
+ (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \
+ (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \
+ (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \
+ (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \
+ (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \
+ (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \
+ (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \
+ (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \
+ (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \
+ (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \
+ (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \
+ (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \
+ (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \
+ (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \
+ (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \
+ (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \
+ "(Invalid)")
+
+#define DRX_STR_LDPC(x) (\
+ (x == DRX_LDPC_0_4) ? "0.4" : \
+ (x == DRX_LDPC_0_6) ? "0.6" : \
+ (x == DRX_LDPC_0_8) ? "0.8" : \
+ (x == DRX_LDPC_AUTO) ? "Auto" : \
+ (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+
+#define DRX_STR_CARRIER(x) (\
+ (x == DRX_CARRIER_MULTI) ? "Multi" : \
+ (x == DRX_CARRIER_SINGLE) ? "Single" : \
+ (x == DRX_CARRIER_AUTO) ? "Auto" : \
+ (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+
+#define DRX_STR_FRAMEMODE(x) (\
+ (x == DRX_FRAMEMODE_420) ? "420" : \
+ (x == DRX_FRAMEMODE_595) ? "595" : \
+ (x == DRX_FRAMEMODE_945) ? "945" : \
+ (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \
+ (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \
+ (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \
+ (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+
+#define DRX_STR_PILOT(x) (\
+ (x == DRX_PILOT_ON) ? "On" : \
+ (x == DRX_PILOT_OFF) ? "Off" : \
+ (x == DRX_PILOT_AUTO) ? "Auto" : \
+ (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+/* TPS */
+
+#define DRX_STR_TPS_FRAME(x) (\
+ (x == DRX_TPS_FRAME1) ? "Frame1" : \
+ (x == DRX_TPS_FRAME2) ? "Frame2" : \
+ (x == DRX_TPS_FRAME3) ? "Frame3" : \
+ (x == DRX_TPS_FRAME4) ? "Frame4" : \
+ (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+
+/* lock status */
+
+#define DRX_STR_LOCKSTATUS(x) (\
+ (x == DRX_NEVER_LOCK) ? "Never" : \
+ (x == DRX_NOT_LOCKED) ? "No" : \
+ (x == DRX_LOCKED) ? "Locked" : \
+ (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \
+ (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \
+ (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \
+ (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \
+ (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \
+ (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \
+ (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \
+ (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \
+ (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \
+ "(Invalid)")
+
+/* version information , modules */
+#define DRX_STR_MODULE(x) (\
+ (x == DRX_MODULE_DEVICE) ? "Device" : \
+ (x == DRX_MODULE_MICROCODE) ? "Microcode" : \
+ (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \
+ (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \
+ (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \
+ (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \
+ (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \
+ (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \
+ (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+
+#define DRX_STR_POWER_MODE(x) (\
+ (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \
+ (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \
+ (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \
+ (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \
+ (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \
+ (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \
+ (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \
+ (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \
+ (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \
+ (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \
+ (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \
+ (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \
+ (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \
+ (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \
+ (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \
+ (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \
+ (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \
+ (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \
+ "(Invalid)")
+
+#define DRX_STR_OOB_STANDARD(x) (\
+ (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \
+ (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \
+ (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \
+ "(Invalid)")
+
+#define DRX_STR_AUD_STANDARD(x) (\
+ (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \
+ (x == DRX_AUD_STANDARD_A2) ? "A2" : \
+ (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \
+ (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \
+ (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \
+ (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \
+ (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \
+ (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \
+ (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \
+ (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \
+ (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \
+ (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \
+ (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \
+ (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \
+ (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \
+ (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \
+ "(Invalid)")
+#define DRX_STR_AUD_STEREO(x) (\
+ (x == TRUE) ? "Stereo" : \
+ (x == FALSE) ? "Mono" : \
+ "(Invalid)")
+
+#define DRX_STR_AUD_SAP(x) (\
+ (x == TRUE) ? "Present" : \
+ (x == FALSE) ? "Not present" : \
+ "(Invalid)")
+
+#define DRX_STR_AUD_CARRIER(x) (\
+ (x == TRUE) ? "Present" : \
+ (x == FALSE) ? "Not present" : \
+ "(Invalid)")
+
+#define DRX_STR_AUD_RDS(x) (\
+ (x == TRUE) ? "Available" : \
+ (x == FALSE) ? "Not Available" : \
+ "(Invalid)")
+
+#define DRX_STR_AUD_NICAM_STATUS(x) (\
+ (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \
+ (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \
+ (x == DRX_AUD_NICAM_BAD) ? "Bad" : \
+ "(Invalid)")
+
+#define DRX_STR_RDS_VALID(x) (\
+ (x == TRUE) ? "Valid" : \
+ (x == FALSE) ? "Not Valid" : \
+ "(Invalid)")
+
+/*-------------------------------------------------------------------------
+Access macros
+-------------------------------------------------------------------------*/
+
+
+/**
+* \brief Create a compilable reference to the microcode attribute
+* \param d pointer to demod instance
+*
+* Used as main reference to an attribute field.
+* Used by both macro implementation and function implementation.
+* These macros are defined to avoid duplication of code in macro and function
+* definitions that handle access of demod common or extended attributes.
+*
+*/
+
+#define DRX_ATTR_MCRECORD(d) ((d)->myCommonAttr->mcversion)
+#define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->myCommonAttr->mirrorFreqSpect)
+#define DRX_ATTR_CURRENTPOWERMODE(d)((d)->myCommonAttr->currentPowerMode)
+#define DRX_ATTR_ISOPENED(d) ((d)->myCommonAttr->isOpened)
+#define DRX_ATTR_USEBOOTLOADER(d) ((d)->myCommonAttr->useBootloader)
+#define DRX_ATTR_CURRENTSTANDARD(d) ((d)->myCommonAttr->currentStandard)
+#define DRX_ATTR_PREVSTANDARD(d) ((d)->myCommonAttr->prevStandard)
+#define DRX_ATTR_CACHESTANDARD(d) ((d)->myCommonAttr->diCacheStandard)
+#define DRX_ATTR_CURRENTCHANNEL(d) ((d)->myCommonAttr->currentChannel)
+#define DRX_ATTR_MICROCODE(d) ((d)->myCommonAttr->microcode)
+#define DRX_ATTR_MICROCODESIZE(d) ((d)->myCommonAttr->microcodeSize)
+#define DRX_ATTR_VERIFYMICROCODE(d) ((d)->myCommonAttr->verifyMicrocode)
+#define DRX_ATTR_CAPABILITIES(d) ((d)->myCommonAttr->capabilities)
+#define DRX_ATTR_PRODUCTID(d) ((d)->myCommonAttr->productId)
+#define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->myCommonAttr->intermediateFreq)
+#define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->myCommonAttr->sysClockFreq)
+#define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->myCommonAttr->tunerRfAgcPol)
+#define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->myCommonAttr->tunerIfAgcPol)
+#define DRX_ATTR_TUNERSLOWMODE(d) ((d)->myCommonAttr->tunerSlowMode)
+#define DRX_ATTR_TUNERSPORTNR(d) ((d)->myCommonAttr->tunerPortNr)
+#define DRX_ATTR_TUNER(d) ((d)->myTuner)
+#define DRX_ATTR_I2CADDR(d) ((d)->myI2CDevAddr->i2cAddr)
+#define DRX_ATTR_I2CDEVID(d) ((d)->myI2CDevAddr->i2cDevId)
+
+/**
+* \brief Actual access macro's
+* \param d pointer to demod instance
+* \param x value to set ar to get
+*
+* SET macro's must be used to set the value of an attribute.
+* GET macro's must be used to retrieve the value of an attribute.
+*
+*/
+
+/**************************/
+
+#define DRX_SET_MIRRORFREQSPECT(d, x) \
+ do { \
+ DRX_ATTR_MIRRORFREQSPECT(d) = (x); \
+ } while(0)
+
+#define DRX_GET_MIRRORFREQSPECT(d, x) \
+ do { \
+ (x)=DRX_ATTR_MIRRORFREQSPECT(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_CURRENTPOWERMODE(d, x) \
+ do { \
+ DRX_ATTR_CURRENTPOWERMODE(d) = (x); \
+ } while(0)
+
+#define DRX_GET_CURRENTPOWERMODE(d, x) \
+ do { \
+ (x)=DRX_ATTR_CURRENTPOWERMODE(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_MICROCODE(d, x) \
+ do { \
+ DRX_ATTR_MICROCODE(d) = (x); \
+ } while(0)
+
+#define DRX_GET_MICROCODE(d, x) \
+ do { \
+ (x)=DRX_ATTR_MICROCODE(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_MICROCODESIZE(d, x) \
+ do { \
+ DRX_ATTR_MICROCODESIZE(d) = (x); \
+ } while(0)
+
+#define DRX_GET_MICROCODESIZE(d, x) \
+ do { \
+ (x)=DRX_ATTR_MICROCODESIZE(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_VERIFYMICROCODE(d, x) \
+ do { \
+ DRX_ATTR_VERIFYMICROCODE(d) = (x); \
+ } while(0)
+
+#define DRX_GET_VERIFYMICROCODE(d, x) \
+ do { \
+ (x)=DRX_ATTR_VERIFYMICROCODE(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_MCVERTYPE(d, x) \
+ do { \
+ DRX_ATTR_MCRECORD(d).auxType = (x); \
+ } while (0)
+
+#define DRX_GET_MCVERTYPE(d, x) \
+ do { \
+ (x) = DRX_ATTR_MCRECORD(d).auxType; \
+ } while (0)
+
+/**************************/
+
+#define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD)
+
+/**************************/
+
+#define DRX_SET_MCDEV(d, x) \
+ do { \
+ DRX_ATTR_MCRECORD(d).mcDevType = (x); \
+ } while (0)
+
+#define DRX_GET_MCDEV(d, x) \
+ do { \
+ (x) = DRX_ATTR_MCRECORD(d).mcDevType; \
+ } while (0)
+
+/**************************/
+
+#define DRX_SET_MCVERSION(d, x) \
+ do { \
+ DRX_ATTR_MCRECORD(d).mcVersion = (x); \
+ } while (0)
+
+#define DRX_GET_MCVERSION(d, x) \
+ do { \
+ (x) = DRX_ATTR_MCRECORD(d).mcVersion; \
+ } while (0)
+
+/**************************/
+#define DRX_SET_MCPATCH(d, x) \
+ do { \
+ DRX_ATTR_MCRECORD(d).mcBaseVersion = (x); \
+ } while (0)
+
+#define DRX_GET_MCPATCH(d, x) \
+ do { \
+ (x) = DRX_ATTR_MCRECORD(d).mcBaseVersion; \
+ } while (0)
+
+/**************************/
+
+#define DRX_SET_I2CADDR(d, x) \
+ do { \
+ DRX_ATTR_I2CADDR(d) = (x); \
+ } while(0)
+
+#define DRX_GET_I2CADDR(d, x) \
+ do { \
+ (x)=DRX_ATTR_I2CADDR(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_I2CDEVID(d, x) \
+ do { \
+ DRX_ATTR_I2CDEVID(d) = (x); \
+ } while(0)
+
+#define DRX_GET_I2CDEVID(d, x) \
+ do { \
+ (x)=DRX_ATTR_I2CDEVID(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_USEBOOTLOADER(d, x) \
+ do { \
+ DRX_ATTR_USEBOOTLOADER(d) = (x); \
+ } while(0)
+
+#define DRX_GET_USEBOOTLOADER(d, x) \
+ do { \
+ (x)=DRX_ATTR_USEBOOTLOADER(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_CURRENTSTANDARD(d, x) \
+ do { \
+ DRX_ATTR_CURRENTSTANDARD(d) = (x); \
+ } while(0)
+
+#define DRX_GET_CURRENTSTANDARD(d, x) \
+ do { \
+ (x)=DRX_ATTR_CURRENTSTANDARD(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_PREVSTANDARD(d, x) \
+ do { \
+ DRX_ATTR_PREVSTANDARD(d) = (x); \
+ } while(0)
+
+#define DRX_GET_PREVSTANDARD(d, x) \
+ do { \
+ (x)=DRX_ATTR_PREVSTANDARD(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_CACHESTANDARD(d, x) \
+ do { \
+ DRX_ATTR_CACHESTANDARD(d) = (x); \
+ } while(0)
+
+#define DRX_GET_CACHESTANDARD(d, x) \
+ do { \
+ (x)=DRX_ATTR_CACHESTANDARD(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_CURRENTCHANNEL(d, x) \
+ do { \
+ DRX_ATTR_CURRENTCHANNEL(d) = (x); \
+ } while(0)
+
+#define DRX_GET_CURRENTCHANNEL(d, x) \
+ do { \
+ (x)=DRX_ATTR_CURRENTCHANNEL(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_ISOPENED(d, x) \
+ do { \
+ DRX_ATTR_ISOPENED(d) = (x); \
+ } while(0)
+
+#define DRX_GET_ISOPENED(d, x) \
+ do { \
+ (x) = DRX_ATTR_ISOPENED(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_TUNER(d, x) \
+ do { \
+ DRX_ATTR_TUNER(d) = (x); \
+ } while(0)
+
+#define DRX_GET_TUNER(d, x) \
+ do { \
+ (x) = DRX_ATTR_TUNER(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_CAPABILITIES(d, x) \
+ do { \
+ DRX_ATTR_CAPABILITIES(d) = (x); \
+ } while(0)
+
+#define DRX_GET_CAPABILITIES(d, x) \
+ do { \
+ (x) = DRX_ATTR_CAPABILITIES(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_PRODUCTID(d, x) \
+ do { \
+ DRX_ATTR_PRODUCTID(d) |= (x << 4); \
+ } while(0)
+
+#define DRX_GET_PRODUCTID(d, x) \
+ do { \
+ (x) = (DRX_ATTR_PRODUCTID(d) >> 4); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_MFX(d, x) \
+ do { \
+ DRX_ATTR_PRODUCTID(d) |= (x); \
+ } while(0)
+
+#define DRX_GET_MFX(d, x) \
+ do { \
+ (x) = (DRX_ATTR_PRODUCTID(d) & 0xF); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_INTERMEDIATEFREQ(d, x) \
+ do { \
+ DRX_ATTR_INTERMEDIATEFREQ(d) = (x); \
+ } while(0)
+
+#define DRX_GET_INTERMEDIATEFREQ(d, x) \
+ do { \
+ (x) = DRX_ATTR_INTERMEDIATEFREQ(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_SYSCLOCKFREQ(d, x) \
+ do { \
+ DRX_ATTR_SYSCLOCKFREQ(d) = (x); \
+ } while(0)
+
+#define DRX_GET_SYSCLOCKFREQ(d, x) \
+ do { \
+ (x) = DRX_ATTR_SYSCLOCKFREQ(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_TUNERRFAGCPOL(d, x) \
+ do { \
+ DRX_ATTR_TUNERRFAGCPOL(d) = (x); \
+ } while(0)
+
+#define DRX_GET_TUNERRFAGCPOL(d, x) \
+ do { \
+ (x) = DRX_ATTR_TUNERRFAGCPOL(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_TUNERIFAGCPOL(d, x) \
+ do { \
+ DRX_ATTR_TUNERIFAGCPOL(d) = (x); \
+ } while(0)
+
+#define DRX_GET_TUNERIFAGCPOL(d, x) \
+ do { \
+ (x) = DRX_ATTR_TUNERIFAGCPOL(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_TUNERSLOWMODE(d, x) \
+ do { \
+ DRX_ATTR_TUNERSLOWMODE(d) = (x); \
+ } while(0)
+
+#define DRX_GET_TUNERSLOWMODE(d, x) \
+ do { \
+ (x) = DRX_ATTR_TUNERSLOWMODE(d); \
+ } while(0)
+
+/**************************/
+
+#define DRX_SET_TUNERPORTNR(d, x) \
+ do { \
+ DRX_ATTR_TUNERSPORTNR(d) = (x); \
+ } while(0)
+
+/**************************/
+
+/* Macros with device-specific handling are converted to CFG functions */
+
+#define DRX_ACCESSMACRO_SET(demod, value, cfgName, dataType) \
+ do { \
+ DRXCfg_t config; \
+ dataType cfgData; \
+ config.cfgType = cfgName; \
+ config.cfgData = &cfgData; \
+ cfgData = value; \
+ DRX_Ctrl(demod, DRX_CTRL_SET_CFG, &config); \
+ } while (0)
+
+#define DRX_ACCESSMACRO_GET(demod, value, cfgName, dataType, errorValue) \
+ do { \
+ DRXStatus_t cfgStatus; \
+ DRXCfg_t config; \
+ dataType cfgData; \
+ config.cfgType = cfgName; \
+ config.cfgData = &cfgData; \
+ cfgStatus = DRX_Ctrl(demod, DRX_CTRL_GET_CFG, &config); \
+ if (cfgStatus == DRX_STS_OK) { \
+ value = cfgData; \
+ } else { \
+ value = (dataType)errorValue; \
+ } \
+ } while (0)
+
+
+/* Configuration functions for usage by Access (XS) Macros */
+
+#ifndef DRX_XS_CFG_BASE
+#define DRX_XS_CFG_BASE (500)
+#endif
+
+#define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0)
+#define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1)
+#define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2)
+
+/* Access Macros with device-specific handling */
+
+#define DRX_SET_PRESET(d, x) \
+ DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*)
+#define DRX_GET_PRESET(d, x) \
+ DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR")
+
+#define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \
+ DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t)
+#define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \
+ DRX_XS_CFG_AUD_BTSC_DETECT, DRXAudBtscDetect_t, DRX_UNKNOWN)
+
+#define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \
+ DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t)
+#define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \
+ DRX_XS_CFG_QAM_LOCKRANGE, DRXQamLockRange_t, DRX_UNKNOWN)
+
+
+/**
+* \brief Macro to check if std is an ATV standard
+* \retval TRUE std is an ATV standard
+* \retval FALSE std is an ATV standard
+*/
+#define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \
+ ((std) == DRX_STANDARD_PAL_SECAM_DK) || \
+ ((std) == DRX_STANDARD_PAL_SECAM_I) || \
+ ((std) == DRX_STANDARD_PAL_SECAM_L) || \
+ ((std) == DRX_STANDARD_PAL_SECAM_LP) || \
+ ((std) == DRX_STANDARD_NTSC) || \
+ ((std) == DRX_STANDARD_FM))
+
+/**
+* \brief Macro to check if std is an QAM standard
+* \retval TRUE std is an QAM standards
+* \retval FALSE std is an QAM standards
+*/
+#define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \
+ ((std) == DRX_STANDARD_ITU_B) || \
+ ((std) == DRX_STANDARD_ITU_C) || \
+ ((std) == DRX_STANDARD_ITU_D))
+
+/**
+* \brief Macro to check if std is VSB standard
+* \retval TRUE std is VSB standard
+* \retval FALSE std is not VSB standard
+*/
+#define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB)
+
+/**
+* \brief Macro to check if std is DVBT standard
+* \retval TRUE std is DVBT standard
+* \retval FALSE std is not DVBT standard
+*/
+#define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT)
+
+
+
+
+/*-------------------------------------------------------------------------
+Exported FUNCTIONS
+-------------------------------------------------------------------------*/
+
+DRXStatus_t DRX_Init(pDRXDemodInstance_t demods[]);
+
+DRXStatus_t DRX_Term(void);
+
+DRXStatus_t DRX_Open(pDRXDemodInstance_t demod);
+
+DRXStatus_t DRX_Close(pDRXDemodInstance_t demod);
+
+DRXStatus_t DRX_Ctrl(pDRXDemodInstance_t demod,
+ DRXCtrlIndex_t ctrl,
+ void *ctrlData);
+
+/*-------------------------------------------------------------------------
+THE END
+-------------------------------------------------------------------------*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* __DRXDRIVER_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 13/25] added drx_driver_version header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (11 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 12/25] added drx_driver header " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 15/25] added drxj " Patrick Dickey
` (9 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drx_driver_version.h | 82 ++++++++++++++++++++++
1 files changed, 82 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drx_driver_version.h
diff --git a/drivers/media/dvb/frontends/drx_driver_version.h b/drivers/media/dvb/frontends/drx_driver_version.h
new file mode 100644
index 0000000..b6a37d8
--- /dev/null
+++ b/drivers/media/dvb/frontends/drx_driver_version.h
@@ -0,0 +1,82 @@
+/*
+ *******************************************************************************
+ * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE
+ *
+ * Filename: drx_driver_version.h
+ * Generated on: Mon Jan 18 12:09:23 2010
+ * Generated by: IDF:x 1.3.0
+ * Generated from: ../../../device/drxj/version
+ * Output start: [entry point]
+ *
+ * filename last modified re-use
+ *
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* -----------------------------------------------------
+ * version.idf Mon Jan 18 11:56:10 2010 -
+ *
+ */
+
+#ifndef __DRX_DRIVER_VERSION__H__
+#define __DRX_DRIVER_VERSION__H__ INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef _REGISTERTABLE_
+#include <registertable.h>
+extern RegisterTable_t drx_driver_version[];
+extern RegisterTableInfo_t drx_driver_version_info[];
+#endif /* _REGISTERTABLE_ */
+
+
+/*
+ *==============================================================================
+ * VERSION
+ * version@/var/cvs/projects/drxj.cvsroot/hostcode/drxdriver/device/drxj
+ *==============================================================================
+ */
+
+#define VERSION__A 0x0
+#define VERSION_MAJOR 1
+#define VERSION_MINOR 0
+#define VERSION_PATCH 56
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRX_DRIVER_VERSION__H__ */
+
+/*
+ * End of file (drx_driver_version.h)
+ *******************************************************************************
+ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 15/25] added drxj header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (12 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 13/25] added drx_driver_version " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 18/25] added drxj_mc_vsb " Patrick Dickey
` (8 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drxj.h | 990 ++++++++++++++++++++++++++++++++++++
1 files changed, 990 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drxj.h
diff --git a/drivers/media/dvb/frontends/drxj.h b/drivers/media/dvb/frontends/drxj.h
new file mode 100644
index 0000000..5899537
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxj.h
@@ -0,0 +1,990 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/**
+* \file $Id: drxj.h,v 1.132 2009/12/22 12:13:48 danielg Exp $
+*
+* \brief DRXJ specific header file
+*
+* \author Dragan Savic, Milos Nikolic, Mihajlo Katona, Tao Ding, Paul Janssen
+*/
+
+#ifndef __DRXJ_H__
+#define __DRXJ_H__
+/*-------------------------------------------------------------------------
+INCLUDES
+-------------------------------------------------------------------------*/
+
+#include "drx_driver.h"
+#include "drx_dap_fasi.h"
+
+#ifdef __cplusplus
+extern "C" {
+
+#endif /*
+ */
+
+/* Check DRX-J specific dap condition */
+/* Multi master mode and short addr format only will not work.
+ RMW, CRC reset, broadcast and switching back to single master mode
+ cannot be done with short addr only in multi master mode. */
+#if ((DRXDAP_SINGLE_MASTER==0)&&(DRXDAPFASI_LONG_ADDR_ALLOWED==0))
+#error "Multi master mode and short addressing only is an illegal combination"
+ *; /* Generate a fatal compiler error to make sure it stops here,
+ this is necesarry because not all compilers stop after a #error. */
+
+#endif /*
+ */
+
+/*-------------------------------------------------------------------------
+TYPEDEFS
+-------------------------------------------------------------------------*/
+/*============================================================================*/
+/*============================================================================*/
+/*== code support ============================================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+/*============================================================================*/
+/*============================================================================*/
+/*== SCU cmd if =============================================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+typedef struct {
+
+u16_t command;
+ /**< Command number */
+
+u16_t parameterLen;
+ /**< Data length in byte */
+
+u16_t resultLen;
+ /**< result length in byte */
+
+u16_t * parameter;
+ /**< General purpous param */
+
+u16_t * result;
+ /**< General purpous param */
+
+} DRXJSCUCmd_t, *pDRXJSCUCmd_t;
+
+
+
+/*============================================================================*/
+/*============================================================================*/
+/*== CTRL CFG related data structures ========================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+/* extra intermediate lock state for VSB,QAM,NTSC */
+#define DRXJ_DEMOD_LOCK (DRX_LOCK_STATE_1)
+
+/* OOB lock states */
+#define DRXJ_OOB_AGC_LOCK (DRX_LOCK_STATE_1) /* analog gain control lock */
+#define DRXJ_OOB_SYNC_LOCK (DRX_LOCK_STATE_2) /* digital gain control lock */
+
+/* Intermediate powermodes for DRXJ */
+#define DRXJ_POWER_DOWN_MAIN_PATH DRX_POWER_MODE_8
+#define DRXJ_POWER_DOWN_CORE DRX_POWER_MODE_9
+#define DRXJ_POWER_DOWN_PLL DRX_POWER_MODE_10
+
+/* supstition for GPIO FNC mux */
+#define APP_O (0x0000)
+
+/*#define DRX_CTRL_BASE (0x0000)*/
+
+#define DRXJ_CTRL_CFG_BASE (0x1000)
+ typedef enum {
+DRXJ_CFG_AGC_RF =
+ DRXJ_CTRL_CFG_BASE,
+DRXJ_CFG_AGC_IF,
+
+DRXJ_CFG_AGC_INTERNAL,
+DRXJ_CFG_PRE_SAW,
+
+DRXJ_CFG_AFE_GAIN,
+DRXJ_CFG_SYMBOL_CLK_OFFSET,
+
+DRXJ_CFG_ACCUM_CR_RS_CW_ERR,
+DRXJ_CFG_FEC_MERS_SEQ_COUNT,
+
+DRXJ_CFG_OOB_MISC,
+DRXJ_CFG_SMART_ANT,
+
+DRXJ_CFG_OOB_PRE_SAW,
+DRXJ_CFG_VSB_MISC,
+
+DRXJ_CFG_RESET_PACKET_ERR,
+
+ /* ATV (FM) */
+ DRXJ_CFG_ATV_OUTPUT, /* also for FM (SIF control) but not likely */
+ DRXJ_CFG_ATV_MISC,
+DRXJ_CFG_ATV_EQU_COEF,
+
+DRXJ_CFG_ATV_AGC_STATUS,
+ /* also for FM (IF,RF, audioAGC) */
+
+DRXJ_CFG_MPEG_OUTPUT_MISC,
+DRXJ_CFG_HW_CFG,
+
+DRXJ_CFG_OOB_LO_POW,
+
+
+DRXJ_CFG_MAX /* dummy, never to be used */
+
+ } DRXJCfgType_t, *pDRXJCfgType_t;
+
+
+/**
+* /struct DRXJCfgSmartAntIO_t
+* smart antenna i/o.
+*/
+ typedef enum DRXJCfgSmartAntIO_t {
+DRXJ_SMT_ANT_OUTPUT =
+ 0,
+DRXJ_SMT_ANT_INPUT
+ } DRXJCfgSmartAntIO_t, *pDRXJCfgSmartAntIO_t;
+
+
+/**
+* /struct DRXJCfgSmartAnt_t
+* Set smart antenna.
+*/
+ typedef struct {
+
+DRXJCfgSmartAntIO_t io;
+
+u16_t ctrlData;
+
+} DRXJCfgSmartAnt_t, *pDRXJCfgSmartAnt_t;
+
+
+/**
+* /struct DRXJAGCSTATUS_t
+* AGC status information from the DRXJ-IQM-AF.
+*/
+ typedef struct {
+
+u16_t IFAGC;
+
+u16_t RFAGC;
+
+u16_t DigitalAGC;
+
+} DRXJAgcStatus_t, *pDRXJAgcStatus_t;
+
+
+/* DRXJ_CFG_AGC_RF, DRXJ_CFG_AGC_IF */
+
+/**
+* /struct DRXJAgcCtrlMode_t
+* Available AGCs modes in the DRXJ.
+*/
+ typedef enum {
+DRX_AGC_CTRL_AUTO =
+ 0,
+DRX_AGC_CTRL_USER,
+DRX_AGC_CTRL_OFF
+ } DRXJAgcCtrlMode_t, *pDRXJAgcCtrlMode_t;
+
+
+/**
+* /struct DRXJCfgAgc_t
+* Generic interface for all AGCs present on the DRXJ.
+*/
+ typedef struct {
+
+DRXStandard_t standard; /* standard for which these settings
+ apply */
+
+DRXJAgcCtrlMode_t ctrlMode; /* off, user, auto */
+
+u16_t outputLevel; /* range dependent on AGC */
+
+u16_t minOutputLevel; /* range dependent on AGC */
+
+u16_t maxOutputLevel; /* range dependent on AGC */
+
+u16_t speed; /* range dependent on AGC */
+
+u16_t top; /* rf-agc take over point */
+
+u16_t cutOffCurrent; /* rf-agc is accelerated if output
+ current
+ is below cut-off current */
+
+} DRXJCfgAgc_t, *pDRXJCfgAgc_t;
+
+
+/* DRXJ_CFG_PRE_SAW */
+
+/**
+* /struct DRXJCfgPreSaw_t
+* Interface to configure pre SAW sense.
+*/
+ typedef struct {
+
+DRXStandard_t standard; /* standard to which
+ these settings apply */
+
+u16_t reference; /* pre SAW reference
+ value, range 0 .. 31 */
+
+Bool_t usePreSaw; /* TRUE algorithms must use
+ pre SAW sense */
+
+} DRXJCfgPreSaw_t, *pDRXJCfgPreSaw_t;
+
+
+/* DRXJ_CFG_AFE_GAIN */
+
+/**
+* /struct DRXJCfgAfeGain_t
+* Interface to configure gain of AFE (LNA + PGA).
+*/
+ typedef struct {
+
+DRXStandard_t standard; /* standard to which these
+ settings apply */
+
+u16_t gain; /* gain in 0.1 dB steps,
+ DRXJ range 140 .. 335 */
+
+} DRXJCfgAfeGain_t, *pDRXJCfgAfeGain_t;
+
+
+/**
+* /struct DRXJRSErrors_t
+* Available failure information in DRXJ_FEC_RS.
+*
+* Container for errors that are received in the most recently finished
+* measurment period
+*
+*/
+ typedef struct {
+
+u16_t nrBitErrors; /**< no of pre RS bit errors */
+
+u16_t nrSymbolErrors;
+ /**< no of pre RS symbol errors */
+
+u16_t nrPacketErrors;
+ /**< no of pre RS packet errors */
+
+u16_t nrFailures; /**< no of post RS failures to decode */
+
+u16_t nrSncParFailCount;
+ /**< no of post RS bit erros */
+
+} DRXJRSErrors_t, *pDRXJRSErrors_t;
+
+
+/**
+* /struct DRXJCfgVSBMisc_t
+* symbol error rate
+*/
+ typedef struct {
+
+u32_t symbError; /**< symbol error rate sps */
+
+} DRXJCfgVSBMisc_t, *pDRXJCfgVSBMisc_t;
+
+
+/**
+* /enum DRXJMpegOutputClockRate_t
+* Mpeg output clock rate.
+*
+*/
+ typedef enum {
+DRXJ_MPEG_START_WIDTH_1CLKCYC,
+
+DRXJ_MPEG_START_WIDTH_8CLKCYC
+ } DRXJMpegStartWidth_t, *pDRXJMpegStartWidth_t;
+
+
+/**
+* /enum DRXJMpegOutputClockRate_t
+* Mpeg output clock rate.
+*
+*/
+ typedef enum {
+DRXJ_MPEGOUTPUT_CLOCK_RATE_AUTO,
+
+DRXJ_MPEGOUTPUT_CLOCK_RATE_75973K,
+
+DRXJ_MPEGOUTPUT_CLOCK_RATE_50625K,
+
+DRXJ_MPEGOUTPUT_CLOCK_RATE_37968K,
+
+DRXJ_MPEGOUTPUT_CLOCK_RATE_30375K,
+
+DRXJ_MPEGOUTPUT_CLOCK_RATE_25313K,
+
+DRXJ_MPEGOUTPUT_CLOCK_RATE_21696K
+ } DRXJMpegOutputClockRate_t, *pDRXJMpegOutputClockRate_t;
+
+
+/**
+* /struct DRXJCfgMisc_t
+* Change TEI bit of MPEG output
+* reverse MPEG output bit order
+* set MPEG output clock rate
+*/
+ typedef struct {
+
+Bool_t disableTEIHandling; /**< if TRUE pass
+ (not change) TEI bit */
+
+Bool_t bitReverseMpegOutout; /**< if TRUE, parallel:
+ msb on MD0; serial:
+ lsb out first */
+
+DRXJMpegOutputClockRate_t mpegOutputClockRate;
+ /**< set MPEG output
+ clock rate that
+ overwrites the
+ derived one from
+ symbol rate */
+
+DRXJMpegStartWidth_t mpegStartWidth; /**< set MPEG output
+ start width */
+
+} DRXJCfgMpegOutputMisc_t, *pDRXJCfgMpegOutputMisc_t;
+
+
+/**
+* /enum DRXJXtalFreq_t
+* Supported external crystal reference frequency.
+*/
+ typedef enum {
+DRXJ_XTAL_FREQ_RSVD,
+DRXJ_XTAL_FREQ_27MHZ,
+
+DRXJ_XTAL_FREQ_20P25MHZ,
+DRXJ_XTAL_FREQ_4MHZ
+ } DRXJXtalFreq_t, *pDRXJXtalFreq_t;
+
+
+/**
+* /enum DRXJXtalFreq_t
+* Supported external crystal reference frequency.
+*/
+ typedef enum {
+DRXJ_I2C_SPEED_400KBPS,
+DRXJ_I2C_SPEED_100KBPS
+ } DRXJI2CSpeed_t, *pDRXJI2CSpeed_t;
+
+
+/**
+* /struct DRXJCfgHwCfg_t
+* Get hw configuration, such as crystal reference frequency, I2C speed, etc...
+*/
+ typedef struct {
+
+DRXJXtalFreq_t xtalFreq;
+ /**< crystal reference frequency */
+
+DRXJI2CSpeed_t i2cSpeed;
+ /**< 100 or 400 kbps */
+
+} DRXJCfgHwCfg_t, *pDRXJCfgHwCfg_t;
+
+
+/*
+ * DRXJ_CFG_ATV_MISC
+ */
+ typedef struct {
+
+s16_t peakFilter; /* -8 .. 15 */
+
+u16_t noiseFilter; /* 0 .. 15 */
+
+} DRXJCfgAtvMisc_t, *pDRXJCfgAtvMisc_t;
+
+
+/*
+ * DRXJCfgOOBMisc_t
+ */
+#define DRXJ_OOB_STATE_RESET 0x0
+#define DRXJ_OOB_STATE_AGN_HUNT 0x1
+#define DRXJ_OOB_STATE_DGN_HUNT 0x2
+#define DRXJ_OOB_STATE_AGC_HUNT 0x3
+#define DRXJ_OOB_STATE_FRQ_HUNT 0x4
+#define DRXJ_OOB_STATE_PHA_HUNT 0x8
+#define DRXJ_OOB_STATE_TIM_HUNT 0x10
+#define DRXJ_OOB_STATE_EQU_HUNT 0x20
+#define DRXJ_OOB_STATE_EQT_HUNT 0x30
+#define DRXJ_OOB_STATE_SYNC 0x40
+
+typedef struct {
+
+DRXJAgcStatus_t agc;
+
+Bool_t eqLock;
+
+Bool_t symTimingLock;
+
+Bool_t phaseLock;
+
+Bool_t freqLock;
+
+Bool_t digGainLock;
+
+Bool_t anaGainLock;
+
+u8_t state;
+
+} DRXJCfgOOBMisc_t, *pDRXJCfgOOBMisc_t;
+
+
+/*
+ * Index of in array of coef
+ */
+ typedef enum {
+DRXJ_OOB_LO_POW_MINUS0DB =
+ 0,
+DRXJ_OOB_LO_POW_MINUS5DB,
+
+DRXJ_OOB_LO_POW_MINUS10DB,
+DRXJ_OOB_LO_POW_MINUS15DB,
+
+DRXJ_OOB_LO_POW_MAX
+ } DRXJCfgOobLoPower_t, *pDRXJCfgOobLoPower_t;
+
+
+/*
+ * DRXJ_CFG_ATV_EQU_COEF
+ */
+ typedef struct {
+
+s16_t coef0; /* -256 .. 255 */
+
+s16_t coef1; /* -256 .. 255 */
+
+s16_t coef2; /* -256 .. 255 */
+
+s16_t coef3; /* -256 .. 255 */
+
+} DRXJCfgAtvEquCoef_t, *pDRXJCfgAtvEquCoef_t;
+
+
+/*
+ * Index of in array of coef
+ */
+ typedef enum {
+DRXJ_COEF_IDX_MN =
+ 0,
+DRXJ_COEF_IDX_FM,
+DRXJ_COEF_IDX_L,
+
+DRXJ_COEF_IDX_LP,
+DRXJ_COEF_IDX_BG,
+DRXJ_COEF_IDX_DK,
+
+DRXJ_COEF_IDX_I,
+DRXJ_COEF_IDX_MAX
+ } DRXJCoefArrayIndex_t, *pDRXJCoefArrayIndex_t;
+
+
+/*
+ * DRXJ_CFG_ATV_OUTPUT
+ */
+
+/**
+* /enum DRXJAttenuation_t
+* Attenuation setting for SIF AGC.
+*
+*/
+ typedef enum {
+DRXJ_SIF_ATTENUATION_0DB,
+DRXJ_SIF_ATTENUATION_3DB,
+
+DRXJ_SIF_ATTENUATION_6DB,
+DRXJ_SIF_ATTENUATION_9DB
+ } DRXJSIFAttenuation_t, *pDRXJSIFAttenuation_t;
+
+
+/**
+* /struct DRXJCfgAtvOutput_t
+* SIF attenuation setting.
+*
+*/
+ typedef struct {
+
+Bool_t enableCVBSOutput; /* TRUE= enabled */
+
+Bool_t enableSIFOutput; /* TRUE= enabled */
+
+DRXJSIFAttenuation_t sifAttenuation;
+
+} DRXJCfgAtvOutput_t, *pDRXJCfgAtvOutput_t;
+
+
+/*
+ DRXJ_CFG_ATV_AGC_STATUS (get only)
+*/
+/* TODO : AFE interface not yet finished, subject to change */
+ typedef struct {
+
+u16_t rfAgcGain; /* 0 .. 877 uA */
+
+u16_t ifAgcGain; /* 0 .. 877 uA */
+
+s16_t videoAgcGain; /* -75 .. 1972 in 0.1 dB steps */
+
+s16_t audioAgcGain; /* -4 .. 1020 in 0.1 dB steps */
+
+u16_t rfAgcLoopGain; /* 0 .. 7 */
+
+u16_t ifAgcLoopGain; /* 0 .. 7 */
+
+u16_t videoAgcLoopGain; /* 0 .. 7 */
+
+} DRXJCfgAtvAgcStatus_t, *pDRXJCfgAtvAgcStatus_t;
+
+
+/*============================================================================*/
+/*============================================================================*/
+/*== CTRL related data structures ============================================*/
+/*============================================================================*/
+/*============================================================================*/
+
+/* NONE */
+
+/*============================================================================*/
+/*============================================================================*/
+
+/*========================================*/
+/**
+* /struct DRXJData_t
+* DRXJ specific attributes.
+*
+* Global data container for DRXJ specific data.
+*
+*/
+ typedef struct {
+
+ /* device capabilties (determined during DRX_Open()) */
+ Bool_t hasLNA; /**< TRUE if LNA (aka PGA) present */
+
+Bool_t hasOOB; /**< TRUE if OOB supported */
+
+Bool_t hasNTSC; /**< TRUE if NTSC supported */
+
+Bool_t hasBTSC; /**< TRUE if BTSC supported */
+
+Bool_t hasSMATX; /**< TRUE if mat_tx is available */
+
+Bool_t hasSMARX; /**< TRUE if mat_rx is available */
+
+Bool_t hasGPIO; /**< TRUE if GPIO is available */
+
+Bool_t hasIRQN; /**< TRUE if IRQN is available */
+
+ /* A1/A2/A... */
+ u8_t mfx; /**< metal fix */
+
+
+ /* tuner settings */
+ Bool_t mirrorFreqSpectOOB; /**< tuner inversion (TRUE = tuner mirrors the signal */
+
+
+ /* standard/channel settings */
+ DRXStandard_t standard; /**< current standard information */
+
+DRXConstellation_t constellation;
+ /**< current constellation */
+
+DRXFrequency_t frequency; /**< center signal frequency in KHz */
+
+DRXBandwidth_t currBandwidth; /**< current channel bandwidth */
+
+DRXMirror_t mirror; /**< current channel mirror */
+
+
+ /* signal quality information */
+ u32_t fecBitsDesired; /**< BER accounting period */
+
+u16_t fecVdPlen; /**< no of trellis symbols: VD SER measurement period */
+
+u16_t qamVdPrescale; /**< Viterbi Measurement Prescale */
+
+u16_t qamVdPeriod; /**< Viterbi Measurement period */
+
+u16_t fecRsPlen; /**< defines RS BER measurement period */
+
+u16_t fecRsPrescale; /**< ReedSolomon Measurement Prescale */
+
+u16_t fecRsPeriod; /**< ReedSolomon Measurement period */
+
+Bool_t resetPktErrAcc; /**< Set a flag to reset accumulated packet error */
+
+u16_t pktErrAccStart; /**< Set a flag to reset accumulated packet error */
+
+
+ /* HI configuration */
+ u16_t HICfgTimingDiv; /**< HI Configure() parameter 2 */
+
+u16_t HICfgBridgeDelay; /**< HI Configure() parameter 3 */
+
+u16_t HICfgWakeUpKey; /**< HI Configure() parameter 4 */
+
+u16_t HICfgCtrl; /**< HI Configure() parameter 5 */
+
+u16_t HICfgTransmit; /**< HI Configure() parameter 6 */
+
+
+ /* UIO configuartion */
+ DRXUIOMode_t uioSmaRxMode; /**< current mode of SmaRx pin */
+
+DRXUIOMode_t uioSmaTxMode; /**< current mode of SmaTx pin */
+
+DRXUIOMode_t uioGPIOMode; /**< current mode of ASEL pin */
+
+DRXUIOMode_t uioIRQNMode; /**< current mode of IRQN pin */
+
+
+ /* IQM fs frequecy shift and inversion */
+ u32_t iqmFsRateOfs; /**< frequency shifter setting after setchannel */
+
+Bool_t posImage; /**< Ture: positive image */
+
+ /* IQM RC frequecy shift */
+ u32_t iqmRcRateOfs; /**< frequency shifter setting after setchannel */
+
+
+ /* ATV configuartion */
+ u32_t atvCfgChangedFlags; /**< flag: flags cfg changes */
+
+s16_t atvTopEqu0[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU0__A */
+
+s16_t atvTopEqu1[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU1__A */
+
+s16_t atvTopEqu2[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU2__A */
+
+s16_t atvTopEqu3[DRXJ_COEF_IDX_MAX]; /**< shadow of ATV_TOP_EQU3__A */
+
+Bool_t phaseCorrectionBypass; /**< flag: TRUE=bypass */
+
+s16_t atvTopVidPeak; /**< shadow of ATV_TOP_VID_PEAK__A */
+
+u16_t atvTopNoiseTh; /**< shadow of ATV_TOP_NOISE_TH__A */
+
+Bool_t enableCVBSOutput; /**< flag CVBS ouput enable */
+
+Bool_t enableSIFOutput; /**< flag SIF ouput enable */
+
+DRXJSIFAttenuation_t
+ sifAttenuation;
+ /**< current SIF att setting */
+
+ /* Agc configuration for QAM and VSB */
+ DRXJCfgAgc_t qamRfAgcCfg; /**< qam RF AGC config */
+
+DRXJCfgAgc_t qamIfAgcCfg; /**< qam IF AGC config */
+
+DRXJCfgAgc_t vsbRfAgcCfg; /**< vsb RF AGC config */
+
+DRXJCfgAgc_t vsbIfAgcCfg; /**< vsb IF AGC config */
+
+
+ /* PGA gain configuration for QAM and VSB */
+ u16_t qamPgaCfg; /**< qam PGA config */
+
+u16_t vsbPgaCfg; /**< vsb PGA config */
+
+
+ /* Pre SAW configuration for QAM and VSB */
+ DRXJCfgPreSaw_t qamPreSawCfg; /**< qam pre SAW config */
+
+DRXJCfgPreSaw_t vsbPreSawCfg; /**< qam pre SAW config */
+
+
+ /* Version information */
+ char vText[2][12]; /**< allocated text versions */
+
+DRXVersion_t vVersion[2]; /**< allocated versions structs */
+
+DRXVersionList_t vListElements[2];
+ /**< allocated version list */
+
+
+ /* smart antenna configuration */
+ Bool_t smartAntInverted;
+
+
+ /* Tracking filter setting for OOB */
+ u16_t oobTrkFilterCfg[8];
+
+Bool_t oobPowerOn;
+
+
+ /* MPEG static bitrate setting */
+ u32_t mpegTsStaticBitrate; /**< bitrate static MPEG output */
+
+Bool_t disableTEIhandling; /**< MPEG TS TEI handling */
+
+Bool_t bitReverseMpegOutout; /**< MPEG output bit order */
+
+DRXJMpegOutputClockRate_t
+ mpegOutputClockRate;
+ /**< MPEG output clock rate */
+
+DRXJMpegStartWidth_t
+ mpegStartWidth;
+ /**< MPEG Start width */
+
+
+ /* Pre SAW & Agc configuration for ATV */
+ DRXJCfgPreSaw_t atvPreSawCfg; /**< atv pre SAW config */
+
+DRXJCfgAgc_t atvRfAgcCfg; /**< atv RF AGC config */
+
+DRXJCfgAgc_t atvIfAgcCfg; /**< atv IF AGC config */
+
+u16_t atvPgaCfg; /**< atv pga config */
+
+
+u32_t currSymbolRate;
+
+
+ /* pin-safe mode */
+ Bool_t pdrSafeMode; /**< PDR safe mode activated */
+
+u16_t pdrSafeRestoreValGpio;
+
+u16_t pdrSafeRestoreValVSync;
+
+u16_t pdrSafeRestoreValSmaRx;
+
+u16_t pdrSafeRestoreValSmaTx;
+
+
+ /* OOB pre-saw value */
+ u16_t oobPreSaw;
+
+DRXJCfgOobLoPower_t oobLoPow;
+
+
+DRXAudData_t audData; /**< audio storage */
+
+
+} DRXJData_t, *pDRXJData_t;
+
+
+/*-------------------------------------------------------------------------
+Access MACROS
+-------------------------------------------------------------------------*/
+/**
+* \brief Compilable references to attributes
+* \param d pointer to demod instance
+*
+* Used as main reference to an attribute field.
+* Can be used by both macro implementation and function implementation.
+* These macros are defined to avoid duplication of code in macro and function
+* definitions that handle access of demod common or extended attributes.
+*
+*/
+
+#define DRXJ_ATTR_BTSC_DETECT(d) \
+ (((pDRXJData_t) (d)->myExtAttr)->audData.btscDetect)
+
+/**
+* \brief Actual access macros
+* \param d pointer to demod instance
+* \param x value to set or to get
+*
+* SET macros must be used to set the value of an attribute.
+* GET macros must be used to retrieve the value of an attribute.
+* Depending on the value of DRX_USE_ACCESS_FUNCTIONS the macro's will be
+* substituted by "direct-access-inline-code" or a function call.
+*
+*/
+#define DRXJ_GET_BTSC_DETECT(d, x) \
+ do { \
+(x) = DRXJ_ATTR_BTSC_DETECT((d)); \
+} while (0)
+
+#define DRXJ_SET_BTSC_DETECT(d, x) \
+ do { \
+DRXJ_ATTR_BTSC_DETECT(d) = (x); \
+} while (0)
+
+
+/*-------------------------------------------------------------------------
+DEFINES
+-------------------------------------------------------------------------*/
+
+/**
+* \def DRXJ_NTSC_CARRIER_FREQ_OFFSET
+* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
+*
+* For NTSC standard.
+* NTSC channels are listed by their picture carrier frequency (Fpc).
+* The function DRX_CTRL_SET_CHANNEL requires the centre frequency as input.
+* In case the tuner module is not used the DRX-J requires that the tuner is
+* tuned to the centre frequency of the channel:
+*
+* Fcentre = Fpc + DRXJ_NTSC_CARRIER_FREQ_OFFSET
+*
+*/
+#define DRXJ_NTSC_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(1750))
+
+/**
+* \def DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
+* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
+*
+* For PAL/SECAM - BG standard. This define is needed in case the tuner module
+* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency
+* (Fpc).
+* The DRX-J requires that the tuner is tuned to:
+* Fpc + DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET
+*
+* In case the tuner module is used the drxdriver takes care of this.
+* In case the tuner module is NOT used the application programmer must take
+* care of this.
+*
+*/
+#define DRXJ_PAL_SECAM_BG_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2375))
+
+/**
+* \def DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
+* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
+*
+* For PAL/SECAM - DK, I, L standards. This define is needed in case the tuner
+* module
+* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency
+* (Fpc).
+* The DRX-J requires that the tuner is tuned to:
+* Fpc + DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET
+*
+* In case the tuner module is used the drxdriver takes care of this.
+* In case the tuner module is NOT used the application programmer must take
+* care of this.
+*
+*/
+#define DRXJ_PAL_SECAM_DKIL_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(2775))
+
+/**
+* \def DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
+* \brief Offset from picture carrier to centre frequency in kHz, in RF domain
+*
+* For PAL/SECAM - LP standard. This define is needed in case the tuner module
+* is NOT used. PAL/SECAM channels are listed by their picture carrier frequency
+* (Fpc).
+* The DRX-J requires that the tuner is tuned to:
+* Fpc + DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET
+*
+* In case the tuner module is used the drxdriver takes care of this.
+* In case the tuner module is NOT used the application programmer must take
+* care of this.
+*/
+#define DRXJ_PAL_SECAM_LP_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3255))
+
+/**
+* \def DRXJ_FM_CARRIER_FREQ_OFFSET
+* \brief Offset from sound carrier to centre frequency in kHz, in RF domain
+*
+* For FM standard.
+* FM channels are listed by their sound carrier frequency (Fsc).
+* The function DRX_CTRL_SET_CHANNEL requires the Ffm frequency (see below) as
+* input.
+* In case the tuner module is not used the DRX-J requires that the tuner is
+* tuned to the Ffm frequency of the channel.
+*
+* Ffm = Fsc + DRXJ_FM_CARRIER_FREQ_OFFSET
+*
+*/
+#define DRXJ_FM_CARRIER_FREQ_OFFSET ((DRXFrequency_t)(-3000))
+
+/* Revision types -------------------------------------------------------*/
+
+#define DRXJ_TYPE_ID (0x3946000DUL)
+
+/* Macros ---------------------------------------------------------------*/
+
+/* Convert OOB lock status to string */
+#define DRXJ_STR_OOB_LOCKSTATUS(x) (\
+ (x == DRX_NEVER_LOCK) ? "Never" : \
+(x == DRX_NOT_LOCKED) ? "No" : \
+(x == DRX_LOCKED) ? "Locked" : \
+(x == DRX_LOCK_STATE_1) "AGC lock" : \
+(x == DRX_LOCK_STATE_2) ? "sync lock" : \
+"(Invalid)")
+
+
+/*-------------------------------------------------------------------------
+ENUM
+-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------
+STRUCTS
+-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------
+Exported FUNCTIONS
+-------------------------------------------------------------------------*/
+
+extern DRXStatus_t DRXJ_Open(pDRXDemodInstance_t demod);
+
+extern DRXStatus_t DRXJ_Close(pDRXDemodInstance_t demod);
+
+extern DRXStatus_t DRXJ_Ctrl(pDRXDemodInstance_t demod,
+
+DRXCtrlIndex_t ctrl,
+void *ctrlData);
+
+
+/*-------------------------------------------------------------------------
+Exported GLOBAL VARIABLES
+-------------------------------------------------------------------------*/
+ extern DRXAccessFunc_t drxDapDRXJFunct_g;
+
+extern DRXDemodFunc_t DRXJFunctions_g;
+
+extern DRXJData_t DRXJData_g;
+
+extern I2CDeviceAddr_t DRXJDefaultAddr_g;
+
+extern DRXCommonAttr_t DRXJDefaultCommAttr_g;
+
+extern DRXDemodInstance_t DRXJDefaultDemod_g;
+
+
+/*-------------------------------------------------------------------------
+THE END
+-------------------------------------------------------------------------*/
+#ifdef __cplusplus
+ }
+#endif /*
+ */
+#endif /* __DRXJ_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 18/25] added drxj_mc_vsb header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (13 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 15/25] added drxj " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 19/25] added drxj_mc_vsbqam " Patrick Dickey
` (7 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drxj_mc_vsb.h | 744 +++++++++++++++++++++++++++++
1 files changed, 744 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drxj_mc_vsb.h
diff --git a/drivers/media/dvb/frontends/drxj_mc_vsb.h b/drivers/media/dvb/frontends/drxj_mc_vsb.h
new file mode 100644
index 0000000..3a9ee2b
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxj_mc_vsb.h
@@ -0,0 +1,744 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*-----------------------------------------------------------------------------
+* DESCRIPTION:
+* Contains firmware version: 1.0.8
+*
+* USAGE:
+* Include.
+*
+* NOTES:
+----------------------------------------------------------------------------*/
+
+#ifndef __DRXJ_MC_VSB_H__
+#define __DRXJ_MC_VSB_H__
+
+#define DRXJ_MC_VSB ((pu8_t) drxj_mc_vsb_g)
+
+const u8_t drxj_mc_vsb_g[] = {
+0x48, 0x4c, 0x00, 0x03, 0x00, 0x00, 0x2b, 0x62, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82,
+0x00, 0x00, 0x15, 0x9e, 0x00, 0x01, 0x92, 0x3b, 0x2a, 0x02, 0xe4, 0xf8, 0x7f, 0x90, 0xf0, 0xf8,
+0xf0, 0xa3, 0x02, 0x22, 0xa6, 0x15, 0x23, 0x7f, 0x71, 0x7e, 0x29, 0x12, 0x90, 0x61, 0x19, 0x7b,
+0xf0, 0xef, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92, 0xaf, 0xc2, 0x28, 0x12, 0x90, 0xb6, 0x19, 0x7b,
+0xfd, 0xe0, 0x4d, 0xef, 0x90, 0xff, 0xf6, 0x7f, 0xf0, 0xee, 0xef, 0xa3, 0xa2, 0xf0, 0x92, 0xd1,
+0xd0, 0xaf, 0xe4, 0xd0, 0x7f, 0x90, 0xf0, 0xf8, 0xf0, 0xa3, 0xe4, 0x22, 0x7f, 0x90, 0xf0, 0xf8,
+0xf0, 0xa3, 0x02, 0x22, 0x70, 0x09, 0x00, 0x22, 0x00, 0x00, 0x02, 0x00, 0x00, 0x28, 0x7a, 0x90,
+0xe0, 0xfa, 0xa3, 0xfe, 0xff, 0xe0, 0x30, 0x7d, 0x94, 0x7c, 0x29, 0x12, 0x90, 0xa5, 0xfc, 0x7a,
+0xfe, 0xe0, 0xe0, 0xa3, 0x7d, 0xff, 0x7c, 0x31, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, 0xe0, 0x01,
+0x7e, 0xff, 0x7d, 0x00, 0x7c, 0x2e, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, 0xe0, 0x02, 0x7e, 0xff,
+0x7d, 0x00, 0x7c, 0x22, 0x12, 0x94, 0xa5, 0x29, 0x7b, 0x90, 0xe0, 0x03, 0x7e, 0xff, 0x7d, 0x00,
+0x7c, 0x23, 0x02, 0x94, 0xa5, 0x29, 0x62, 0x30, 0x12, 0x06, 0xb5, 0x2a, 0x04, 0x7f, 0x7f, 0x22,
+0x22, 0x00, 0x02, 0x00, 0x41, 0x28, 0x40, 0x30, 0xc2, 0xfd, 0x8e, 0x40, 0x8f, 0xd3, 0xed, 0xd2,
+0xff, 0x24, 0xec, 0xff, 0xff, 0x34, 0xda, 0xf5, 0xd9, 0x8f, 0x02, 0x22, 0x82, 0x28, 0x7d, 0x90,
+0xe0, 0x3b, 0xf0, 0x54, 0x03, 0x70, 0x80, 0xd3, 0xc3, 0x01, 0x92, 0xb3, 0x90, 0x05, 0x3a, 0x7d,
+0xa3, 0xe0, 0xe4, 0xa2, 0x92, 0xb3, 0xe0, 0x02, 0x0f, 0x54, 0x03, 0x70, 0x80, 0xd3, 0xc3, 0x01,
+0x92, 0xb3, 0x90, 0x06, 0x91, 0x7d, 0x30, 0xe0, 0x03, 0xe1, 0x02, 0x02, 0x90, 0x65, 0x5a, 0x7d,
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+0x65, 0x7d, 0x64, 0xe0, 0x94, 0x80, 0x40, 0x7f, 0x74, 0x03, 0xf0, 0xff, 0x5b, 0x20, 0xd2, 0x09,
+0xe4, 0x5b, 0x7d, 0x90, 0xf0, 0x60, 0xf0, 0xa3, 0x7d, 0x90, 0xe0, 0x4a, 0x02, 0x70, 0xe0, 0xa3,
+0x03, 0x70, 0x02, 0x20, 0x90, 0x17, 0x4a, 0x7d, 0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x90, 0x3c,
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+0xa3, 0xfe, 0xff, 0xe0, 0x90, 0xd3, 0x6b, 0x7d, 0x9f, 0xe0, 0x7d, 0x90, 0xe0, 0x6a, 0x40, 0x9e,
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+0xa3, 0xff, 0x90, 0xe0, 0xae, 0x7f, 0xf0, 0xcf, 0xef, 0xa3, 0x12, 0xf0, 0xdb, 0x2a, 0x90, 0xe4,
+0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x6d, 0xef, 0x02, 0x70, 0x6c, 0xee, 0x10, 0x60, 0xef, 0x0f,
+0x06, 0xaa, 0x01, 0x70, 0x14, 0x0e, 0x82, 0xf5, 0x83, 0x8a, 0xf0, 0xe4, 0xe8, 0x80, 0x00, 0x22,
+0x0a, 0x00, 0x00, 0xf4, 0x3f, 0x00, 0x00, 0xaf, 0xb5, 0x00, 0xff, 0x05, 0xf5, 0xff, 0x00, 0x4a,
+0x3f, 0x00, 0xff, 0x5b, 0xca, 0xff, 0x7d, 0xe0, 0x7c, 0x16, 0x7f, 0x71, 0x7e, 0x04, 0x12, 0x00,
+0xa5, 0x29, 0x18, 0x7d, 0x71, 0x7c, 0x03, 0x7f, 0x00, 0x7e, 0x29, 0x02, 0x53, 0xa5, 0xe7, 0xa9,
+0xab, 0x53, 0x7f, 0xf7, 0x12, 0x04, 0x5c, 0x17, 0x62, 0xc2, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0,
+0x22, 0xf0, 0x40, 0x30, 0xc2, 0xfd, 0xef, 0x40, 0xfe, 0x54, 0xc2, 0x8e, 0xc1, 0xf5, 0xc3, 0x8c,
+0xc5, 0x8d, 0x12, 0x22, 0x4e, 0x00, 0x2a, 0x12, 0x12, 0x9f, 0x04, 0x2b, 0x24, 0x12, 0x02, 0xd8,
+0x50, 0x24, 0x40, 0xc2, 0x54, 0xef, 0x8e, 0xfe, 0xf5, 0xc2, 0x8c, 0xc1, 0x8d, 0xc3, 0x22, 0xc4,
+0x7f, 0x78, 0xf6, 0xe4, 0xfd, 0xd8, 0x81, 0x75, 0x02, 0x3b, 0x99, 0x16, 0x06, 0x7d, 0x90, 0x7c,
+0x02, 0x7f, 0x00, 0x7e, 0x29, 0x02, 0x8e, 0xa5, 0x8f, 0x82, 0xa3, 0x83, 0x82, 0xae, 0x83, 0xaf,
+0x12, 0x22, 0x00, 0xb2, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x74, 0x38, 0x90, 0xff, 0xf8, 0x7f,
+0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f,
+0xa3, 0xf0, 0x22, 0xf0, 0x00, 0x83, 0x1f, 0xfe, 0x00, 0x02, 0x00, 0x01, 0xe8, 0x03, 0x10, 0x00,
+0x08, 0x00, 0x80, 0x00, 0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00
+};
+
+#endif /* __DRXJ_MC_VSB_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 19/25] added drxj_mc_vsbqam header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (14 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 18/25] added drxj_mc_vsb " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 20/25] added drxj_options " Patrick Dickey
` (6 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drxj_mc_vsbqam.h | 1437 ++++++++++++++++++++++++++
1 files changed, 1437 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drxj_mc_vsbqam.h
diff --git a/drivers/media/dvb/frontends/drxj_mc_vsbqam.h b/drivers/media/dvb/frontends/drxj_mc_vsbqam.h
new file mode 100644
index 0000000..6907f2e
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxj_mc_vsbqam.h
@@ -0,0 +1,1437 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*-----------------------------------------------------------------------------
+* DESCRIPTION:
+* Contains firmware version: 1.0.8
+*
+* USAGE:
+* Include.
+*
+* NOTES:
+*
+----------------------------------------------------------------------------*/
+
+#ifndef __DRXJ_MC_VSBQAM_H__
+#define __DRXJ_MC_VSBQAM_H__
+
+#define DRXJ_MC_VSBQAM ((pu8_t) drxj_mc_vsbqam_g)
+
+const u8_t drxj_mc_vsbqam_g[] = {
+0x48, 0x4c, 0x00, 0x04, 0x00, 0x00, 0x56, 0xa0, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82,
+0x00, 0x00, 0x20, 0x00, 0x00, 0x01, 0xc4, 0x4d, 0x55, 0x02, 0xe4, 0xee, 0x7f, 0x90, 0xf0, 0xf8,
+0xf0, 0xa3, 0x02, 0x22, 0x4b, 0x23, 0xd0, 0xc0, 0xaf, 0xa2, 0xd1, 0x92, 0xaf, 0xc2, 0xa8, 0x53,
+0x53, 0xfb, 0xef, 0xa9, 0xaa, 0x53, 0x53, 0xf7, 0xf7, 0xab, 0xd1, 0xa2, 0xaf, 0x92, 0xd0, 0xd0,
+0x04, 0x7f, 0x25, 0x12, 0x12, 0x01, 0xd2, 0x55, 0x61, 0xc2, 0x13, 0xc2, 0x90, 0xe4, 0x95, 0x7f,
+0x90, 0xf0, 0x8c, 0x7a, 0x90, 0xf0, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x3b, 0x12, 0xc2, 0xe0,
+0x22, 0x58, 0x02, 0x22, 0x70, 0x09, 0x00, 0x02, 0x22, 0x4a, 0x02, 0x22, 0x7f, 0x50, 0xa8, 0xc0,
+0xaf, 0xc2, 0x40, 0x10, 0xd0, 0x04, 0x80, 0xa8, 0x75, 0xf5, 0x7d, 0xc2, 0xc1, 0x75, 0x8e, 0xa0,
+0x8f, 0xc3, 0x30, 0xc5, 0xfd, 0x40, 0x7d, 0x90, 0xe0, 0xa0, 0xa3, 0xfe, 0xff, 0xe0, 0xa8, 0xd0,
+0x22, 0x22, 0x02, 0x00, 0xf3, 0x4c, 0x7e, 0x90, 0xe0, 0xeb, 0x7a, 0x90, 0xf0, 0xa8, 0x7e, 0x90,
+0xe0, 0xe9, 0x7a, 0x90, 0xf0, 0xa9, 0xb4, 0xe0, 0x11, 0x01, 0x7a, 0x90, 0xe0, 0xa8, 0x05, 0xb4,
+0x12, 0x05, 0x4e, 0x00, 0x08, 0x80, 0x56, 0x12, 0x80, 0x6a, 0x12, 0x03, 0x51, 0x00, 0x3b, 0x02,
+0x00, 0xe0, 0x02, 0x00, 0xc0, 0x50, 0x62, 0x30, 0x12, 0x06, 0x6c, 0x55, 0x04, 0x7f, 0x30, 0x22,
+0x06, 0x61, 0x00, 0x12, 0x7f, 0x0e, 0x22, 0x02, 0x00, 0x7f, 0x02, 0x22, 0xa0, 0x51, 0x7d, 0x90,
+0xe0, 0x3b, 0xf0, 0x54, 0x03, 0x70, 0x80, 0xd3, 0xc3, 0x01, 0x92, 0xb3, 0x90, 0x05, 0x3a, 0x7d,
+0xa3, 0xe0, 0xe4, 0xa2, 0x92, 0xb3, 0xe0, 0x02, 0x0f, 0x54, 0x03, 0x70, 0x80, 0xd3, 0xc3, 0x01,
+0x92, 0xb3, 0x90, 0x06, 0x91, 0x7d, 0x30, 0xe0, 0x03, 0xe1, 0x02, 0x02, 0x90, 0x65, 0x5a, 0x7d,
+0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x30, 0x31, 0x2e, 0x02, 0x7d, 0x90, 0xe0, 0x78, 0xa3, 0xfe,
+0xff, 0xe0, 0x90, 0xc3, 0x75, 0x7d, 0x9f, 0xe0, 0x7d, 0x90, 0xe0, 0x74, 0x50, 0x9e, 0x90, 0x19,
+0x65, 0x7d, 0x64, 0xe0, 0x94, 0x80, 0x40, 0x7f, 0x74, 0x03, 0xf0, 0xff, 0x5b, 0x20, 0xd2, 0x09,
+0xe4, 0x5b, 0x7d, 0x90, 0xf0, 0x60, 0xf0, 0xa3, 0x7d, 0x90, 0xe0, 0x4a, 0x02, 0x70, 0xe0, 0xa3,
+0x03, 0x70, 0x02, 0x20, 0x90, 0x17, 0x4a, 0x7d, 0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x90, 0x3c,
+0x5a, 0x7d, 0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x20, 0x32, 0x2f, 0x02, 0x7d, 0x90, 0xe0, 0x6c,
+0xa3, 0xfe, 0xff, 0xe0, 0x90, 0xd3, 0x6b, 0x7d, 0x9f, 0xe0, 0x7d, 0x90, 0xe0, 0x6a, 0x40, 0x9e,
+0x90, 0x1a, 0x57, 0x7d, 0xd3, 0xe0, 0x80, 0x64, 0x7f, 0x94, 0x03, 0x40, 0xff, 0x74, 0x20, 0xf0,
+0x09, 0x07, 0x07, 0xd2, 0x90, 0xe4, 0x52, 0x7d, 0xa3, 0xf0, 0x7f, 0xf0, 0x7e, 0x22, 0x12, 0x67,
+0x56, 0x00, 0x14, 0x8e, 0x15, 0x8f, 0x27, 0x7f, 0x67, 0x7e, 0x00, 0x12, 0x8e, 0x56, 0x8f, 0x16,
+0x90, 0x17, 0x5e, 0x7d, 0xfe, 0xe0, 0xe0, 0xa3, 0x03, 0x78, 0x33, 0xc3, 0x33, 0xce, 0xd8, 0xce,
+0xff, 0xf9, 0xe5, 0xd3, 0x9f, 0x17, 0x16, 0xe5, 0x40, 0x9e, 0x20, 0x54, 0x0c, 0x02, 0x7d, 0x90,
+0xe0, 0x57, 0x80, 0x64, 0x81, 0x94, 0x10, 0x50, 0x0b, 0x80, 0x7d, 0x90, 0xe0, 0x65, 0x64, 0xc3,
+0x94, 0x80, 0x50, 0x81, 0x74, 0x03, 0xf0, 0x01, 0x5b, 0x20, 0xd2, 0x34, 0xe4, 0x5b, 0x7d, 0x90,
+0xf0, 0x60, 0xf0, 0xa3, 0x7d, 0x90, 0xe0, 0x68, 0xa3, 0xfe, 0xff, 0xe0, 0x90, 0xc3, 0x6b, 0x7d,
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+0xe5, 0xd3, 0x9f, 0x15, 0x14, 0xe5, 0x40, 0x9e, 0x90, 0x44, 0x57, 0x7d, 0x64, 0xe0, 0x94, 0x80,
+0x50, 0x81, 0x74, 0x03, 0xf0, 0x01, 0x07, 0x20, 0xd2, 0x34, 0xe4, 0x07, 0x7d, 0x90, 0xf0, 0x52,
+0xf0, 0xa3, 0x7d, 0x90, 0xe0, 0x68, 0xa3, 0xfe, 0xff, 0xe0, 0x90, 0xc3, 0x6b, 0x7d, 0x9f, 0xe0,
+0x7d, 0x90, 0xe0, 0x6a, 0x50, 0x9e, 0x90, 0x16, 0x91, 0x7d, 0x30, 0xe0, 0x0f, 0xe0, 0x7d, 0x90,
+0xe0, 0x68, 0xa3, 0xff, 0x90, 0xe0, 0x6a, 0x7d, 0xf0, 0xcf, 0xef, 0xa3, 0x90, 0xf0, 0x34, 0x7d,
+0xf5, 0xe0, 0xa3, 0x16, 0xf5, 0xe0, 0x90, 0x17, 0x60, 0x7d, 0xf5, 0xe0, 0xa3, 0x1c, 0xf5, 0xe0,
+0x05, 0x1d, 0xe5, 0x1d, 0x70, 0x1d, 0x05, 0x02, 0x90, 0x1c, 0x60, 0x7d, 0x1c, 0xe5, 0xa3, 0xf0,
+0x1d, 0xe5, 0x30, 0xf0, 0x2f, 0x5b, 0x7d, 0x90, 0xe0, 0x7e, 0xa3, 0xfe, 0xff, 0xe0, 0x74, 0xc3,
+0x9f, 0xf8, 0x74, 0xff, 0x9e, 0x2a, 0xd3, 0xfe, 0x7d, 0x90, 0xe0, 0x7b, 0x90, 0x9f, 0x7a, 0x7d,
+0x9e, 0xe0, 0x07, 0x50, 0x70, 0xe0, 0xa3, 0x02, 0x70, 0xe0, 0x90, 0x0a, 0x2e, 0x7d, 0xf5, 0xe0,
+0xa3, 0x16, 0xf5, 0xe0, 0xc3, 0x17, 0x1d, 0xe5, 0x17, 0x95, 0x1c, 0xe5, 0x16, 0x95, 0x03, 0x40,
+0x80, 0xd3, 0xc3, 0x01, 0x04, 0x92, 0x7d, 0x90, 0xe0, 0x50, 0x16, 0xf5, 0xe0, 0xa3, 0x17, 0xf5,
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+0x22, 0xf0, 0xf0, 0x8f, 0xf7, 0x30, 0x63, 0x03, 0xff, 0x07, 0xd4, 0x8f, 0xd5, 0x8d, 0xd7, 0x8a,
+0xd6, 0x8b, 0xf7, 0x30, 0x7f, 0x04, 0x80, 0x06, 0x7f, 0x02, 0x8f, 0x02, 0x22, 0xdb, 0xf0, 0x8f,
+0xf7, 0x30, 0x63, 0x03, 0xff, 0x07, 0xd4, 0x8f, 0xd5, 0x8d, 0xd7, 0x8a, 0xd6, 0x8b, 0xf7, 0x30,
+0x7f, 0x04, 0x80, 0x05, 0x7f, 0x02, 0x8f, 0x01, 0x22, 0xdb, 0xf0, 0x8f, 0xf7, 0x30, 0x63, 0x03,
+0xff, 0x07, 0xd4, 0x8f, 0xd5, 0x8d, 0xd7, 0x8a, 0xd6, 0x8b, 0xf7, 0x30, 0x7f, 0x04, 0x80, 0x07,
+0x7f, 0x02, 0x8f, 0x03, 0x22, 0xdb, 0x7a, 0x90, 0x12, 0x98, 0x98, 0x27, 0x00, 0x00, 0x00, 0x00,
+0x7a, 0x90, 0x12, 0x9c, 0x98, 0x27, 0x00, 0x00, 0x00, 0x00, 0x90, 0xe4, 0x96, 0x7a, 0xa3, 0xf0,
+0x22, 0xf0, 0x7f, 0x90, 0xe0, 0xf8, 0xa3, 0xff, 0x90, 0xe0, 0xae, 0x7f, 0xf0, 0xcf, 0xef, 0xa3,
+0x12, 0xf0, 0xb5, 0x55, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x6d, 0xef, 0x02, 0x70,
+0x6c, 0xee, 0x10, 0x60, 0xef, 0x0f, 0x06, 0xaa, 0x01, 0x70, 0x14, 0x0e, 0x82, 0xf5, 0x83, 0x8a,
+0xf0, 0xe4, 0xe8, 0x80, 0x00, 0x22, 0x0a, 0x00, 0x00, 0xf4, 0x3f, 0x00, 0x00, 0xaf, 0xb5, 0x00,
+0xff, 0x05, 0xf5, 0xff, 0x00, 0x4a, 0x3f, 0x00, 0xff, 0x5b, 0xca, 0xff, 0x90, 0xe0, 0x4b, 0x7b,
+0x2f, 0x74, 0x90, 0xf0, 0xf2, 0x7e, 0xa3, 0xe0, 0x25, 0xe0, 0x04, 0xe0, 0x7b, 0x90, 0xf0, 0x58,
+0x3a, 0x02, 0x7d, 0x9a, 0x7c, 0x16, 0x7f, 0x71, 0x7e, 0x04, 0x12, 0x00, 0xf5, 0x53, 0x18, 0x7d,
+0x71, 0x7c, 0x03, 0x7f, 0x00, 0x7e, 0x53, 0x02, 0x30, 0xf5, 0xfd, 0x40, 0x40, 0xc2, 0xd3, 0x8e,
+0xd2, 0x8f, 0x24, 0xed, 0xff, 0xff, 0x34, 0xec, 0xf5, 0xff, 0x8f, 0xda, 0x22, 0xd9, 0xa9, 0x53,
+0x53, 0xe7, 0xf7, 0xab, 0x04, 0x7f, 0x25, 0x12, 0xc2, 0x01, 0xe4, 0x62, 0x7f, 0x90, 0xf0, 0xf8,
+0xf0, 0xa3, 0x90, 0x22, 0x66, 0x7f, 0x1f, 0x74, 0xa3, 0xf0, 0x7f, 0x74, 0xe4, 0xf0, 0x7f, 0x90,
+0xf0, 0xf8, 0xf0, 0xa3, 0x30, 0x22, 0xfd, 0x40, 0x40, 0xc2, 0x54, 0xef, 0x8e, 0xfe, 0xf5, 0xc2,
+0x8c, 0xc1, 0x8d, 0xc3, 0x22, 0xc5, 0x7a, 0x90, 0xe0, 0xbd, 0x90, 0x04, 0xe9, 0x7b, 0x60, 0xf0,
+0xe0, 0x05, 0x7a, 0x90, 0xf0, 0xbd, 0x12, 0x22, 0x79, 0x00, 0x55, 0x12, 0x12, 0x41, 0xfa, 0x55,
+0x4a, 0x12, 0x02, 0x63, 0x5b, 0x48, 0x40, 0xc2, 0x54, 0xef, 0x8e, 0xfe, 0xf5, 0xc2, 0x8c, 0xc1,
+0x8d, 0xc3, 0x22, 0xc4, 0x90, 0xe4, 0x66, 0x7f, 0xa3, 0xf0, 0x90, 0xf0, 0xf8, 0x7f, 0xa3, 0xf0,
+0x22, 0xf0, 0x7a, 0x90, 0xe0, 0xbd, 0x7a, 0x90, 0xf0, 0xbe, 0x90, 0xe4, 0xbd, 0x7a, 0x22, 0xf0,
+0x7f, 0x78, 0xf6, 0xe4, 0xfd, 0xd8, 0x81, 0x75, 0x02, 0x3f, 0x3e, 0x24, 0x06, 0x7d, 0x90, 0x7c,
+0x02, 0x7f, 0x00, 0x7e, 0x53, 0x02, 0x8e, 0xf5, 0x8f, 0x82, 0xa3, 0x83, 0x82, 0xae, 0x83, 0xaf,
+0x20, 0x22, 0x00, 0x59, 0x00, 0x00, 0x00, 0x00, 0x33, 0x00, 0x74, 0x92, 0x90, 0xff, 0xf8, 0x7f,
+0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f,
+0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f,
+0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f,
+0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f,
+0xa3, 0xf0, 0x22, 0xf0, 0x90, 0xe4, 0xf8, 0x7f, 0xa3, 0xf0, 0x22, 0xf0, 0x00, 0x02, 0x02, 0x4a,
+0xef, 0x52, 0x00, 0x83, 0x1f, 0xfe, 0x00, 0x02, 0x00, 0x01, 0xe8, 0x03, 0x10, 0x00, 0x08, 0x00,
+0x80, 0x00, 0x03, 0x94, 0x00, 0xd9, 0x00, 0x10, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00
+};
+
+#endif /* __DRXJ_MC_VSBQAM_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 20/25] added drxj_options header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (15 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 19/25] added drxj_mc_vsbqam " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 21/25] modified Kconfig to include " Patrick Dickey
` (5 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/drxj_options.h | 65 ++++++++++++++++++++++++++++
1 files changed, 65 insertions(+), 0 deletions(-)
create mode 100644 drivers/media/dvb/frontends/drxj_options.h
diff --git a/drivers/media/dvb/frontends/drxj_options.h b/drivers/media/dvb/frontends/drxj_options.h
new file mode 100644
index 0000000..962bd61
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxj_options.h
@@ -0,0 +1,65 @@
+/*
+ Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+ * Neither the name of Trident Microsystems nor Hauppauge Computer Works
+ nor the names of its contributors may be used to endorse or promote
+ products derived from this software without specific prior written
+ permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/**
+* \file $Id: drxj_options.h,v 1.5 2009/10/05 21:32:49 dingtao Exp $
+*
+* \brief DRXJ optional settings
+*
+* \author Tao Ding
+*/
+
+/* Note: Please add preprocessor DRXJ_OPTIONS_H for drxj.c to include this file */
+#ifndef __DRXJ_OPTIONS_H__
+#define __DRXJ_OPTIONS_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* #define DRXJ_DIGITAL_ONLY */
+/* #define DRXJ_VSB_ONLY */
+/* #define DRXJ_SIGNAL_ACCUM_ERR */
+/* #define MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH 0x03 */
+/* #define MPEG_PARALLEL_OUTPUT_PIN_DRIVE_STRENGTH 0x04 */
+/* #define MPEG_OUTPUT_CLK_DRIVE_STRENGTH 0x05 */
+/* #define OOB_CRX_DRIVE_STRENGTH 0x04 */
+/* #define OOB_DRX_DRIVE_STRENGTH 0x05 */
+/* #define DRXJ_QAM_MAX_WAITTIME 1000 */
+/* #define DRXJ_QAM_FEC_LOCK_WAITTIME 200 */
+/* #define DRXJ_QAM_DEMOD_LOCK_EXT_WAITTIME 250 */
+
+/*-------------------------------------------------------------------------
+THE END
+-------------------------------------------------------------------------*/
+#ifdef __cplusplus
+}
+#endif
+#endif /* __DRXJ_OPTIONS_H__ */
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 21/25] modified Kconfig to include pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (16 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 20/25] added drxj_options " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 22/25] modified Makefile for " Patrick Dickey
` (4 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/Kconfig | 8 ++++++++
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 4a2d2e6..352815e 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -683,6 +683,14 @@ config DVB_IX2505V
help
A DVB-S tuner module. Say Y when you want to support this frontend.
+config DVB_DRX39XYJ
+ tristate "Micronas DRX-J demodulator"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ An ATSC 8VSB and QAM64/256 tuner module. Say Y when you want
+ to support this frontend.
+
config DVB_IT913X_FE
tristate "it913x frontend and it9137 tuner"
depends on DVB_CORE && I2C
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 22/25] modified Makefile for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (17 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 21/25] modified Kconfig to include " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 23/25] modified em28xx-cards " Patrick Dickey
` (3 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/dvb/frontends/Makefile | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index f639f67..4709ebc 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -11,6 +11,7 @@ au8522-objs = au8522_dig.o au8522_decoder.o
drxd-objs = drxd_firm.o drxd_hard.o
cxd2820r-objs = cxd2820r_core.o cxd2820r_c.o cxd2820r_t.o cxd2820r_t2.o
drxk-objs := drxk_hard.o
+drx39xyj-objs := drx39xxj.o drx_driver.o drx39xxj_dummy.o drxj.o drx_dap_fasi.o
obj-$(CONFIG_DVB_PLL) += dvb-pll.o
obj-$(CONFIG_DVB_STV0299) += stv0299.o
@@ -86,6 +87,7 @@ obj-$(CONFIG_DVB_ISL6423) += isl6423.o
obj-$(CONFIG_DVB_EC100) += ec100.o
obj-$(CONFIG_DVB_DS3000) += ds3000.o
obj-$(CONFIG_DVB_MB86A16) += mb86a16.o
+obj-$(CONFIG_DVB_DRX39XYJ) += drx39xyj.o
obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
obj-$(CONFIG_DVB_IX2505V) += ix2505v.o
obj-$(CONFIG_DVB_STV0367) += stv0367.o
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 23/25] modified em28xx-cards for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (18 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 22/25] modified Makefile for " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 24/25] modified em28xx-dvb " Patrick Dickey
` (2 subsequent siblings)
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/video/em28xx/em28xx-cards.c | 20 ++++++++++++++++++++
1 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c
index 9b747c2..550bb8e 100644
--- a/drivers/media/video/em28xx/em28xx-cards.c
+++ b/drivers/media/video/em28xx/em28xx-cards.c
@@ -195,6 +195,17 @@ static struct em28xx_reg_seq pinnacle_hybrid_pro_digital[] = {
{ -1, -1, -1, -1},
};
+/* PCTV HD Mini (80e) GPIOs
+ 0-5: not used
+ 6: demod reset, active low
+ 7: LED on, active high */
+static struct em28xx_reg_seq em2874_pctv_80e_digital[] = {
+ {EM28XX_R06_I2C_CLK, 0x45, 0xff, 10}, /*400 KHz*/
+ {EM2874_R80_GPIO, 0x80, 0xff, 100},/*Demod reset*/
+ {EM2874_R80_GPIO, 0xc0, 0xff, 10},
+ { -1, -1, -1, -1},
+};
+
static struct em28xx_reg_seq terratec_cinergy_USB_XS_FR_analog[] = {
{EM28XX_R08_GPIO, 0x6d, ~EM_GPIO_4, 10},
{EM2880_R04_GPO, 0x00, 0xff, 10},
@@ -1808,6 +1819,13 @@ struct em28xx_board em28xx_boards[] = {
.tuner_gpio = reddo_dvb_c_usb_box,
.has_dvb = 1,
},
+ [EM2874_BOARD_PCTV_HD_MINI_80E] = {
+ .name = "Pinnacle PCTV HD Mini",
+ .tuner_type = TUNER_ABSENT,
+ .has_dvb = 1,
+ .dvb_gpio = em2874_pctv_80e_digital,
+ .decoder = EM28XX_NODECODER,
+ },
/* 1b80:a340 - Empia EM2870, NXP TDA18271HD and LG DT3304, sold
* initially as the KWorld PlusTV 340U, then as the UB435-Q.
* Early variants have a TDA18271HD/C1, later ones a TDA18271HD/C2 */
@@ -1961,6 +1979,8 @@ struct usb_device_id em28xx_id_table[] = {
.driver_info = EM2882_BOARD_PINNACLE_HYBRID_PRO_330E },
{ USB_DEVICE(0x2304, 0x0227),
.driver_info = EM2880_BOARD_PINNACLE_PCTV_HD_PRO },
+ { USB_DEVICE(0x2304, 0x023f),
+ .driver_info = EM2874_BOARD_PCTV_HD_MINI_80E },
{ USB_DEVICE(0x0413, 0x6023),
.driver_info = EM2800_BOARD_LEADTEK_WINFAST_USBII },
{ USB_DEVICE(0x093b, 0xa005),
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 24/25] modified em28xx-dvb for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (19 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 23/25] modified em28xx-cards " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-10 23:31 ` [PATCH 25/25] modified em28xx header " Patrick Dickey
2011-11-11 1:45 ` [PATCH 00/25] Add PCTV-80e Support to v4l Devin Heitmueller
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/video/em28xx/em28xx-dvb.c | 25 +++++++++++++++++++++++++
1 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c
index cef7a2d..b69e5f3 100644
--- a/drivers/media/video/em28xx/em28xx-dvb.c
+++ b/drivers/media/video/em28xx/em28xx-dvb.c
@@ -36,6 +36,7 @@
#include "mt352.h"
#include "mt352_priv.h" /* FIXME */
#include "tda1002x.h"
+#include "drx39xxj.h"
#include "tda18271.h"
#include "s921.h"
#include "drxd.h"
@@ -309,6 +310,20 @@ static struct drxd_config em28xx_drxd = {
.disable_i2c_gate_ctrl = 1,
};
+
+static struct tda18271_std_map drx_j_std_map = {
+ .atsc_6 = { .if_freq = 5000, .agc_mode = 3, .std = 0, .if_lvl = 1,
+ .rfagc_top = 0x37, },
+ .qam_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, .if_lvl = 1,
+ .rfagc_top = 0x37, },
+};
+
+static struct tda18271_config pinnacle_80e_dvb_config = {
+ .std_map = &drx_j_std_map,
+ .gate = TDA18271_GATE_DIGITAL,
+ .role = TDA18271_MASTER,
+};
+
struct drxk_config terratec_h5_drxk = {
.adr = 0x29,
.single_master = 1,
@@ -625,6 +640,7 @@ static int em28xx_dvb_init(struct em28xx *dev)
{
int result = 0, mfe_shared = 0;
struct em28xx_dvb *dvb;
+ struct dvb_frontend *fe;
if (!dev->board.has_dvb) {
/* This device does not support the extension */
@@ -752,6 +768,15 @@ static int em28xx_dvb_init(struct em28xx *dev)
}
}
break;
+ case EM2874_BOARD_PCTV_HD_MINI_80E:
+ dvb->fe[0] = dvb_attach(drx39xxj_attach, &dev->i2c_adap);
+ if (dvb->fe[0] != NULL) {
+ fe = dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
+ &dev->i2c_adap,
+ &pinnacle_80e_dvb_config);
+ printk(KERN_ERR "dvb_attach tuner result=%p\n", fe);
+ }
+ break;
case EM2870_BOARD_KWORLD_A340:
dvb->fe[0] = dvb_attach(lgdt3305_attach,
&em2870_lgdt3304_dev,
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 25/25] modified em28xx header for pctv80e support
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (20 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 24/25] modified em28xx-dvb " Patrick Dickey
@ 2011-11-10 23:31 ` Patrick Dickey
2011-11-11 1:45 ` [PATCH 00/25] Add PCTV-80e Support to v4l Devin Heitmueller
22 siblings, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-10 23:31 UTC (permalink / raw)
To: linux-media; +Cc: Patrick Dickey
---
drivers/media/video/em28xx/em28xx.h | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h
index 2a2cb7e..ead2cfe 100644
--- a/drivers/media/video/em28xx/em28xx.h
+++ b/drivers/media/video/em28xx/em28xx.h
@@ -121,6 +121,7 @@
#define EM28174_BOARD_PCTV_290E 78
#define EM2884_BOARD_TERRATEC_H5 79
#define EM28174_BOARD_PCTV_460E 80
+#define EM2874_BOARD_PCTV_HD_MINI_80E 81
/* Limits minimum and default number of buffers */
#define EM28XX_MIN_BUF 4
--
1.7.5.4
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 00/25] Add PCTV-80e Support to v4l
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
` (21 preceding siblings ...)
2011-11-10 23:31 ` [PATCH 25/25] modified em28xx header " Patrick Dickey
@ 2011-11-11 1:45 ` Devin Heitmueller
2011-11-11 2:36 ` Patrick Dickey
22 siblings, 1 reply; 28+ messages in thread
From: Devin Heitmueller @ 2011-11-11 1:45 UTC (permalink / raw)
To: Patrick Dickey; +Cc: Linux Media Mailing List, Mauro Carvalho Chehab
On Thu, Nov 10, 2011 at 6:31 PM, Patrick Dickey <pdickeybeta@gmail.com> wrote:
> These are the files required to support the Pinnacle PCTV-80e USB Tuner in
> video-4-linux. The files were originally downloaded from
> http://www.kernellabs.com/hg/~dheitmueller/v4l-dvb-80e and modified to fix
> compilation errors and also to move the driver files from the drx39xy
> subdirectory to the frontends directory.
<snip>
Hi Patrick,
It's great to see someone taking the time to work to get this
upstream. A few comments though:
None of these patches appear to have an Signed-off-by line. Since I'm
the one vouching for the Micronas code being legitimately allowed to
be submitted (in conformance with the Developer's Certificate of
Origin), I am the one who needs to be the top signed-off-by (in fact,
by arbitrarily breaking my tree into 25 patches, you effectively
stripped off my authorship).
Further, while it's commendable that you broke this into 25 patches, I
think it's perfectly fine that it essentially be the two patches as
found in my hg tree (plus the very minor change needed to get the code
to compile against 3.x). In fact, I suspect you could probably take
my two patches, apply them to the current 3.x tree, fix the two or
three conflicts, and have something that is submittable to staging.
It's not clear to me why you moved the driver files from
frontends/drx39xxj to just frontends. I don't think anybody has ever
complained about having a subdirectory if there is a large enough set
of files. Did somebody ask you to do that and I didn't see the email?
As you indicated, the code hasn't gone through any form of codingstyle
cleanup, and as a result needs to go against the staging tree instead
of the main tree. You should consult with Mauro on how to approach
this problem, because currently you cannot do a demodulator driver
against staging because of the dependency on the em28xx bridge which
is already in stable (adding Mauro to the cc: to get his opinion).
In short, it almost feels like you did *too much* work given you
didn't make any material changes to the code itself as it's in my
tree. I would suggest just submitting my two patches, and then on top
of that you can submit a whole series of patches doing cleanups.
And you should definitely review the following page on submitting
patches if you haven't already:
http://linuxtv.org/wiki/index.php/Development:_How_to_submit_patches
Cheers,
Devin
--
Devin J. Heitmueller - Kernel Labs
http://www.kernellabs.com
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/25] Add PCTV-80e Support to v4l
2011-11-11 1:45 ` [PATCH 00/25] Add PCTV-80e Support to v4l Devin Heitmueller
@ 2011-11-11 2:36 ` Patrick Dickey
2011-11-11 3:19 ` Devin Heitmueller
0 siblings, 1 reply; 28+ messages in thread
From: Patrick Dickey @ 2011-11-11 2:36 UTC (permalink / raw)
To: Devin Heitmueller; +Cc: Linux Media Mailing List, Mauro Carvalho Chehab
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 11/10/2011 07:45 PM, Devin Heitmueller wrote:
> On Thu, Nov 10, 2011 at 6:31 PM, Patrick Dickey
> <pdickeybeta@gmail.com> wrote:
>> These are the files required to support the Pinnacle PCTV-80e USB
>> Tuner in video-4-linux. The files were originally downloaded
>> from http://www.kernellabs.com/hg/~dheitmueller/v4l-dvb-80e and
>> modified to fix compilation errors and also to move the driver
>> files from the drx39xy subdirectory to the frontends directory.
> <snip>
>
> Hi Patrick,
>
> It's great to see someone taking the time to work to get this
> upstream. A few comments though:
>
> None of these patches appear to have an Signed-off-by line. Since
> I'm the one vouching for the Micronas code being legitimately
> allowed to be submitted (in conformance with the Developer's
> Certificate of Origin), I am the one who needs to be the top
> signed-off-by (in fact, by arbitrarily breaking my tree into 25
> patches, you effectively stripped off my authorship).
>
I thought the signed off lines were there. When I generated the
patches, I used "git format-patch -s --subject-prefix='PATCH]
[SIGNED-OFF' media-master " which I thought would add that in. However
it must not have. I'll resubmit the patches with your name on the top
and then mine below. It'll probably be tomorrow or Saturday before I
get to that, though.
> Further, while it's commendable that you broke this into 25
> patches, I think it's perfectly fine that it essentially be the two
> patches as found in my hg tree (plus the very minor change needed
> to get the code to compile against 3.x). In fact, I suspect you
> could probably take my two patches, apply them to the current 3.x
> tree, fix the two or three conflicts, and have something that is
> submittable to staging.
>
The reason that I broke it up into 25 patches is because I did a test
send to myself (as one patch for the entire driver) and it was almost
3MB in size. So, I decided to break it into a single patch for each
file to reduce the size--and so each file could be dealt with
separately. If that was the wrong thing to do, I'll fix it.
> It's not clear to me why you moved the driver files from
> frontends/drx39xxj to just frontends. I don't think anybody has
> ever complained about having a subdirectory if there is a large
> enough set of files. Did somebody ask you to do that and I didn't
> see the email?
>
This was another unilateral decision. When I was trying to get this
working on my computer, I found that make wouldn't even go into the
subdirectory. Which meant that whenever I plugged the USB Tuner in, it
would fail because it couldn't find the dvb_attach() method (from one
of the driver files). After moving them from the subdirectory to
frontends (and fixing the Makefile and Kconfig appropriately)
everything compiled and loaded correctly. In the end, that was the
only thing I found that worked. However, I can send them in the
subdirectory also.
> As you indicated, the code hasn't gone through any form of
> codingstyle cleanup, and as a result needs to go against the
> staging tree instead of the main tree. You should consult with
> Mauro on how to approach this problem, because currently you cannot
> do a demodulator driver against staging because of the dependency
> on the em28xx bridge which is already in stable (adding Mauro to
> the cc: to get his opinion).
>
This brings up a question for me. Most of the "trailing whitespace"
errors aren't showing up in any of my editors (nano or meld to name
two of them). And most of the trailing whitespace errors are in the
comments. So are those really issues that will block the files from
being submitted? Also, would they be happening because of the "DOS
Line Ending" errors on most of the same lines?
Also, I started to clean up the files tonight. Then I started thinking
about what you told me about the as102 drivers, and thought I should
submit them "as is" and then start the cleanup and submit those
patches separately. Also that way others could help with some of the
cleanup. I have to figure out if there's an easy way to convert all of
the "DOS Line Endings" to the appropriate style, or if I'll have to do
that manually (and whether my editor(s) caused this).
For Mauro: I can either resubmit everything once it's cleaned up, go
from here, start over and submit the original patches from Devin's
tree, or whatever you think is best.
> In short, it almost feels like you did *too much* work given you
> didn't make any material changes to the code itself as it's in my
> tree. I would suggest just submitting my two patches, and then on
> top of that you can submit a whole series of patches doing
> cleanups.
One reason I did the extra work is because your tree had other files
(the cx18 drivers for example) that didn't seem to be needed by the
tuner. So, I cleaned them out (partially because I have two cards that
use those drivers and didn't want to break those). I can review all
of the files to make sure that I didn't miss any. And I can update
all of the files from your tree to the most current versions and
submit everything again.
>
> And you should definitely review the following page on submitting
> patches if you haven't already:
>
> http://linuxtv.org/wiki/index.php/Development:_How_to_submit_patches
>
>
I'll re-read the page this weekend. I did read it, and it does a great
job of telling you what needs to be done. I was struggling with how to
get some of the things done though (such as adding the Signed Off
lines to the code). Which is probably why most of the issues that I'm
having are coming up.
> Cheers,
>
> Devin
>
Thank you for your quick reply to this. And I'm sorry if I created
more issues than I solved. I'll definitely take every bit of advice
in and rework everything properly.
Have a great evening. :)
Patrick.
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/25] Add PCTV-80e Support to v4l
2011-11-11 2:36 ` Patrick Dickey
@ 2011-11-11 3:19 ` Devin Heitmueller
2011-11-11 11:39 ` Patrick Dickey
2011-11-11 13:28 ` Patrick Dickey
0 siblings, 2 replies; 28+ messages in thread
From: Devin Heitmueller @ 2011-11-11 3:19 UTC (permalink / raw)
To: Patrick Dickey; +Cc: Linux Media Mailing List, Mauro Carvalho Chehab
On Thu, Nov 10, 2011 at 9:36 PM, Patrick Dickey <pdickeybeta@gmail.com> wrote:
> Also, I started to clean up the files tonight. Then I started thinking
> about what you told me about the as102 drivers, and thought I should
> submit them "as is" and then start the cleanup and submit those
> patches separately. Also that way others could help with some of the
> cleanup. I have to figure out if there's an easy way to convert all of
> the "DOS Line Endings" to the appropriate style, or if I'll have to do
> that manually (and whether my editor(s) caused this).
Definitely you want the cleanup fixes to be in separate patches from
the original patch with the driver. This is necessary because it
makes it *much* easier to figure out if something got broken as a
result of a cleanup patch (which isn't supposed to make any functional
change).
> One reason I did the extra work is because your tree had other files
> (the cx18 drivers for example) that didn't seem to be needed by the
> tuner. So, I cleaned them out (partially because I have two cards that
> use those drivers and didn't want to break those). I can review all
> of the files to make sure that I didn't miss any. And I can update
> all of the files from your tree to the most current versions and
> submit everything again.
This shouldn't be the case (the two patches will have no interaction
with any driver other than em28xx). I would suggest that instead of
treating it as a tree, just suck the two patches off the top and apply
them to your current tree one at a time, and fix any conflicts that
pop up.
http://kernellabs.com/hg/~dheitmueller/v4l-dvb-80e/raw-rev/c119f08c4dd2
http://kernellabs.com/hg/~dheitmueller/v4l-dvb-80e/raw-rev/30c6512030ac
If you just apply the patches instead of trying to hand-merge the two
trees together, you will only get the delta and will likely just have
to fix the 4 or five conflicts in em28xx.h and em28xx-cards.c (related
to the fact that subsequent boards were added to the driver after my
patch).
That approach should only take a few minutes, given the conflicts are
trivial to resolve.
Good luck!
Devin
--
Devin J. Heitmueller - Kernel Labs
http://www.kernellabs.com
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/25] Add PCTV-80e Support to v4l
2011-11-11 3:19 ` Devin Heitmueller
@ 2011-11-11 11:39 ` Patrick Dickey
2011-11-11 13:28 ` Patrick Dickey
1 sibling, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-11 11:39 UTC (permalink / raw)
To: Devin Heitmueller; +Cc: Linux Media Mailing List, Mauro Carvalho Chehab
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 11/10/2011 09:19 PM, Devin Heitmueller wrote:
> On Thu, Nov 10, 2011 at 9:36 PM, Patrick Dickey
> <pdickeybeta@gmail.com> wrote:
>> Also, I started to clean up the files tonight. Then I started
>> thinking about what you told me about the as102 drivers, and
>> thought I should submit them "as is" and then start the cleanup
>> and submit those patches separately. Also that way others could
>> help with some of the cleanup. I have to figure out if there's an
>> easy way to convert all of the "DOS Line Endings" to the
>> appropriate style, or if I'll have to do that manually (and
>> whether my editor(s) caused this).
>
> Definitely you want the cleanup fixes to be in separate patches
> from the original patch with the driver. This is necessary because
> it makes it *much* easier to figure out if something got broken as
> a result of a cleanup patch (which isn't supposed to make any
> functional change).
>
>> One reason I did the extra work is because your tree had other
>> files (the cx18 drivers for example) that didn't seem to be
>> needed by the tuner. So, I cleaned them out (partially because I
>> have two cards that use those drivers and didn't want to break
>> those). I can review all of the files to make sure that I didn't
>> miss any. And I can update all of the files from your tree to
>> the most current versions and submit everything again.
>
> This shouldn't be the case (the two patches will have no
> interaction with any driver other than em28xx). I would suggest
> that instead of treating it as a tree, just suck the two patches
> off the top and apply them to your current tree one at a time, and
> fix any conflicts that pop up.
>
> http://kernellabs.com/hg/~dheitmueller/v4l-dvb-80e/raw-rev/c119f08c4dd2
>
>
http://kernellabs.com/hg/~dheitmueller/v4l-dvb-80e/raw-rev/30c6512030ac
>
> If you just apply the patches instead of trying to hand-merge the
> two trees together, you will only get the delta and will likely
> just have to fix the 4 or five conflicts in em28xx.h and
> em28xx-cards.c (related to the fact that subsequent boards were
> added to the driver after my patch).
>
> That approach should only take a few minutes, given the conflicts
> are trivial to resolve.
>
> Good luck!
>
> Devin
>
Thank you again for the quick reply. I think that the problem I had
was that I hand merged everything (using meld, but that's beside the
point). While I was at work last night, I decided that I need to do
exactly what you suggested here. Hopefully that will take care of the
Signed Off By problems too (if not, then I'll manually enter them).
If this works as it should, how do I retract this patch series (as
they'll no longer be valid) or is it safe to say that they'll be
ignored from here out?
Have a great day:)
Patrick.
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/25] Add PCTV-80e Support to v4l
2011-11-11 3:19 ` Devin Heitmueller
2011-11-11 11:39 ` Patrick Dickey
@ 2011-11-11 13:28 ` Patrick Dickey
1 sibling, 0 replies; 28+ messages in thread
From: Patrick Dickey @ 2011-11-11 13:28 UTC (permalink / raw)
To: Devin Heitmueller; +Cc: Linux Media Mailing List, Mauro Carvalho Chehab
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
On 11/10/2011 09:19 PM, Devin Heitmueller wrote:
> On Thu, Nov 10, 2011 at 9:36 PM, Patrick Dickey
> <pdickeybeta@gmail.com> wrote: snipped to conserve space and also
> unrelated to this email....
>
> This shouldn't be the case (the two patches will have no
> interaction with any driver other than em28xx). I would suggest
> that instead of treating it as a tree, just suck the two patches
> off the top and apply them to your current tree one at a time, and
> fix any conflicts that pop up.
>
> http://kernellabs.com/hg/~dheitmueller/v4l-dvb-80e/raw-rev/c119f08c4dd2
>
>
http://kernellabs.com/hg/~dheitmueller/v4l-dvb-80e/raw-rev/30c6512030ac
>
> If you just apply the patches instead of trying to hand-merge the
> two trees together, you will only get the delta and will likely
> just have to fix the 4 or five conflicts in em28xx.h and
> em28xx-cards.c (related to the fact that subsequent boards were
> added to the driver after my patch).
>
Here are the results of applying the first patch (c119f08c4dd2.patch)
to my branch:
patch -p2 -i c119f08c4dd2.patch
patching file Documentation/video4linux/CARDLIST.em28xx
Hunk #1 FAILED at 72.
1 out of 1 hunk FAILED -- saving rejects to file
Documentation/video4linux/CARDLIST.em28xx.rej
patching file drivers/media/dvb/frontends/Kconfig
Hunk #1 FAILED at 614.
1 out of 1 hunk FAILED -- saving rejects to file
drivers/media/dvb/frontends/Kconfig.rej
patching file drivers/media/dvb/frontends/Makefile
Hunk #1 FAILED at 82.
1 out of 1 hunk FAILED -- saving rejects to file
drivers/media/dvb/frontends/Makefile.rej
patching file drivers/media/video/em28xx/em28xx-cards.c
Hunk #1 succeeded at 193 with fuzz 1 (offset 12 lines).
Hunk #2 succeeded at 1852 with fuzz 2 (offset 121 lines).
Hunk #3 succeeded at 1980 with fuzz 1 (offset 125 lines).
patching file drivers/media/video/em28xx/em28xx-dvb.c
Hunk #1 FAILED at 35.
Hunk #2 succeeded at 420 with fuzz 1 (offset 120 lines).
Hunk #3 succeeded at 639 with fuzz 2 (offset 172 lines).
Hunk #4 succeeded at 848 with fuzz 2 (offset 262 lines).
1 out of 4 hunks FAILED -- saving rejects to file
drivers/media/video/em28xx/em28xx-dvb.c.rej
patching file drivers/media/video/em28xx/em28xx.h
Hunk #1 FAILED at 114.
1 out of 1 hunk FAILED -- saving rejects to file
drivers/media/video/em28xx/em28xx.h.rej
patching file drivers/media/dvb/frontends/drx39xyj/Kconfig
patching file drivers/media/dvb/frontends/drx39xyj/Makefile
patching file drivers/media/dvb/frontends/drx39xyj/bsp_host.h
patching file drivers/media/dvb/frontends/drx39xyj/bsp_i2c.h
patching file drivers/media/dvb/frontends/drx39xyj/bsp_tuner.h
patching file drivers/media/dvb/frontends/drx39xyj/bsp_types.h
patching file drivers/media/dvb/frontends/drx39xyj/drx39xxj.c
patching file drivers/media/dvb/frontends/drx39xyj/drx39xxj.h
patching file drivers/media/dvb/frontends/drx39xyj/drx39xxj_dummy.c
patching file drivers/media/dvb/frontends/drx39xyj/drx_dap_fasi.c
patching file drivers/media/dvb/frontends/drx39xyj/drx_dap_fasi.h
patching file drivers/media/dvb/frontends/drx39xyj/drx_driver.c
patching file drivers/media/dvb/frontends/drx39xyj/drx_driver.h
patching file drivers/media/dvb/frontends/drx39xyj/drx_driver_version.h
patching file drivers/media/dvb/frontends/drx39xyj/drxj.c
patching file drivers/media/dvb/frontends/drx39xyj/drxj.h
patching file drivers/media/dvb/frontends/drx39xyj/drxj_map.h
patching file drivers/media/dvb/frontends/drx39xyj/drxj_mc.h
patching file drivers/media/dvb/frontends/drx39xyj/drxj_mc_vsb.h
patching file drivers/media/dvb/frontends/drx39xyj/drxj_mc_vsbqam.h
patching file drivers/media/dvb/frontends/drx39xyj/drxj_options.h
> That approach should only take a few minutes, given the conflicts
> are trivial to resolve.
Yes they are trivial to resolve. The CARDLIST.em28xx needs to be
changed to 81 and reflect the preceeding lines. The Kconfig and
Makefile just need to have lines adjusted (and the endif removed from
the Kconfig).
I successfully applied the second patch (30c6512030ac.patch) to
everything (since it's only changing your email address on the
drx39xyj files).
I have your two patches in my branch directory.Now I have a few
options to choose from (as I see it)
1. Should I submit your two patches and then go back and fix the bugs,
then submit those patches?
2. Should I fix the bugs first, then submit your two patches as 01 and
02, and my bug-fixes as 03 through 07?
3. Should I fix the bugs, then fix as many of the coding style issues
as I can find, and submit all of the patches as one giant group (your
two patches being 01 and 02, the bug fixes being 03 through 07, and
the coding style fixes being 08 through 25 or so)?
or
4. Should I fix your patches and submit those (I'm already ruling
this out, but it does seem like the easiest way through this whole
process)?
If these seem like trivial or newbie questions, I'm sorry. I look at
it like this: I messed up my first time through. So I want to make
sure I have all of my ducks in a row before I make my second attempt.
>
> Good luck!
>
> Devin
>
Thank you. My first time through wasn't as clean and pretty as I hoped
it would be. And I appreciate all of the help that I'm getting (from
you and everyone else).
Have a great day:)
Patrick.
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^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2011-11-11 13:28 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-11-10 23:31 [PATCH 00/25] Add PCTV-80e Support to v4l Patrick Dickey
2011-11-10 23:31 ` [PATCH 01/25] added PCTV80e information to cardlist file Patrick Dickey
2011-11-10 23:31 ` [PATCH 02/25] added bsp_host for pctv80e support Patrick Dickey
2011-11-10 23:31 ` [PATCH 03/25] added bsp_i2c " Patrick Dickey
2011-11-10 23:31 ` [PATCH 04/25] added bsp_tuner " Patrick Dickey
2011-11-10 23:31 ` [PATCH 05/25] added bsp_types " Patrick Dickey
2011-11-10 23:31 ` [PATCH 06/25] added drx39xxj " Patrick Dickey
2011-11-10 23:31 ` [PATCH 07/25] added drx39xxj header " Patrick Dickey
2011-11-10 23:31 ` [PATCH 08/25] added drx39_dummy " Patrick Dickey
2011-11-10 23:31 ` [PATCH 09/25] added drx_dap_fasi " Patrick Dickey
2011-11-10 23:31 ` [PATCH 10/25] added drx_dap_fasi header " Patrick Dickey
2011-11-10 23:31 ` [PATCH 11/25] added drx_driver " Patrick Dickey
2011-11-10 23:31 ` [PATCH 12/25] added drx_driver header " Patrick Dickey
2011-11-10 23:31 ` [PATCH 13/25] added drx_driver_version " Patrick Dickey
2011-11-10 23:31 ` [PATCH 15/25] added drxj " Patrick Dickey
2011-11-10 23:31 ` [PATCH 18/25] added drxj_mc_vsb " Patrick Dickey
2011-11-10 23:31 ` [PATCH 19/25] added drxj_mc_vsbqam " Patrick Dickey
2011-11-10 23:31 ` [PATCH 20/25] added drxj_options " Patrick Dickey
2011-11-10 23:31 ` [PATCH 21/25] modified Kconfig to include " Patrick Dickey
2011-11-10 23:31 ` [PATCH 22/25] modified Makefile for " Patrick Dickey
2011-11-10 23:31 ` [PATCH 23/25] modified em28xx-cards " Patrick Dickey
2011-11-10 23:31 ` [PATCH 24/25] modified em28xx-dvb " Patrick Dickey
2011-11-10 23:31 ` [PATCH 25/25] modified em28xx header " Patrick Dickey
2011-11-11 1:45 ` [PATCH 00/25] Add PCTV-80e Support to v4l Devin Heitmueller
2011-11-11 2:36 ` Patrick Dickey
2011-11-11 3:19 ` Devin Heitmueller
2011-11-11 11:39 ` Patrick Dickey
2011-11-11 13:28 ` Patrick Dickey
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