[PATCH 15/22] ARM: dts: imx6qdl: Add MIPI CSI-2 D-PHY compatible and clocks

Philipp Zabel
2016-10-07T16:01:29Z

>From the data sheets it is not quite clear what the clock inputs should
be named, but freescale code calls them "dphy_clk" (would that be per?)
and "pixel_clk" and connects them to the mipi_core_cfg and emi_podf
clocks, respectively. The mipi_core_cfg control is called hsi_tx
currently, but it really gates a whole lot of other clocks, too.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index cd325bd..2be6de4 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1123,9 +1123,16 @@
};

mipi_csi: mipi@021dc000 {
+ compatible = "fsl,imx6q-mipi-csi2", "dw-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>, /* mipi_core_cfg/ipg_clk_root */
+ <&clks IMX6QDL_CLK_HSI_TX>, /* mipi_core_cfg/video_27m_clk_root */
+ <&clks IMX6QDL_CLK_HSI_TX>, /* mipi_core_cfg/video_27m_clk_root */
+ <&clks IMX6QDL_CLK_EIM_PODF>; /* shoid be ipu1_ipu_hsp_clk_root on S/DL, axi_clk_root on D/Q */
+ clock-names = "pclk", "cfg", "ref", "pixel";
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};

mipi_dsi: mipi@021e0000 {
--
2.9.3