From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:47084 "EHLO mx0a-001b2d01.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728733AbeH3BI1 (ORCPT ); Wed, 29 Aug 2018 21:08:27 -0400 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w7TL9Epd047104 for ; Wed, 29 Aug 2018 17:09:46 -0400 Received: from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206]) by mx0a-001b2d01.pphosted.com with ESMTP id 2m61rcuaqd-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 29 Aug 2018 17:09:45 -0400 Received: from localhost by e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 29 Aug 2018 17:09:43 -0400 From: Eddie James To: linux-kernel@vger.kernel.org Cc: linux-media@vger.kernel.org, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, andrew@aj.id.au, mchehab@kernel.org, joel@jms.id.au, robh+dt@kernel.org, mark.rutland@arm.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, linux-arm-kernel@lists.infradead.org, Eddie James Subject: [PATCH 1/4] clock: aspeed: Add VIDEO reset index definition Date: Wed, 29 Aug 2018 16:09:30 -0500 In-Reply-To: <1535576973-8067-1-git-send-email-eajames@linux.vnet.ibm.com> References: <1535576973-8067-1-git-send-email-eajames@linux.vnet.ibm.com> Message-Id: <1535576973-8067-2-git-send-email-eajames@linux.vnet.ibm.com> Sender: linux-media-owner@vger.kernel.org List-ID: Add an index into the array of resets kept in the Aspeed clock driver. This isn't a HW bit definition. Signed-off-by: Eddie James --- include/dt-bindings/clock/aspeed-clock.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index f437386..15a9059 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -50,5 +50,6 @@ #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 #define ASPEED_RESET_CRT1 9 +#define ASPEED_RESET_VIDEO 10 #endif -- 1.8.3.1