Re: [PATCH 10/11] media: iris: Add platform data for glymur

Vishnu Reddy
2026-04-17T15:52:43Z

On 4/14/2026 9:35 PM, Dmitry Baryshkov wrote:
> On Tue, Apr 14, 2026 at 10:30:06AM +0530, Vishnu Reddy wrote:
>> Add glymur platform data by reusing most of the SM8550 definitions.
>> Move configuration that differs in a per-SoC platform specific data.
>>
>> Signed-off-by: Vishnu Reddy<busanna.reddy@oss.qualcomm.com>
>> ---
>> drivers/media/platform/qcom/iris/Makefile | 1 +
>> .../platform/qcom/iris/iris_platform_common.h | 1 +
>> .../media/platform/qcom/iris/iris_platform_gen2.c | 100 +++++++++++++++++++++
>> .../platform/qcom/iris/iris_platform_glymur.c | 93 +++++++++++++++++++
>> .../platform/qcom/iris/iris_platform_glymur.h | 17 ++++
>> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
>> 6 files changed, 216 insertions(+)
>>
>> diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/platform/qcom/iris/Makefile
>> index 6f4052b98491..677513c7c045 100644
>> --- a/drivers/media/platform/qcom/iris/Makefile
>> +++ b/drivers/media/platform/qcom/iris/Makefile
>> @@ -11,6 +11,7 @@ qcom-iris-objs += iris_buffer.o \
>> iris_hfi_gen2_response.o \
>> iris_hfi_queue.o \
>> iris_platform_gen2.o \
>> + iris_platform_glymur.o \
>> iris_power.o \
>> iris_probe.o \
>> iris_resources.o \
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> index aeb70f54be10..a279ea462ee6 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
>> @@ -41,6 +41,7 @@ enum pipe_type {
>> PIPE_4 = 4,
>> };
>>
>> +extern const struct iris_platform_data glymur_data;
>> extern const struct iris_platform_data qcs8300_data;
>> extern const struct iris_platform_data sc7280_data;
>> extern const struct iris_platform_data sm8250_data;
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> index 47c6b650f0b4..fa2115092be8 100644
>> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
>> @@ -12,6 +12,7 @@
>> #include "iris_vpu_buffer.h"
>> #include "iris_vpu_common.h"
>>
>> +#include "iris_platform_glymur.h"
>> #include "iris_platform_qcs8300.h"
>> #include "iris_platform_sm8650.h"
>> #include "iris_platform_sm8750.h"
>> @@ -921,6 +922,105 @@ static const u32 sm8550_enc_op_int_buf_tbl[] = {
>> BUF_SCRATCH_2,
>> };
>>
>> +const struct iris_platform_data glymur_data = {
> If you add a platform-specific file, then move the data to the file too.

glymur_data reusing the most of the sm8550 definitions which is in this
source file.
one option is to introduce gen2 header file and extern all the glymur
required definitions
in that. glymur source can include that gen2 header.

> Also, please use iris_something prefix for all your visible symbols.

Ack, I'll add iris prefix.

>> + .get_instance = iris_hfi_gen2_get_instance,
>> + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>> + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init,
>> + .get_vpu_buffer_size = iris_vpu_buf_size,
>> + .vpu_ops = &iris_vpu36_ops,
>> + .set_preset_registers = iris_set_sm8550_preset_registers,
>> + .init_cb_devs = glymur_init_cb_devs,
>> + .deinit_cb_devs = glymur_deinit_cb_devs,
>> + .icc_tbl = sm8550_icc_table,
>> + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table),
>> + .clk_rst_tbl = glymur_clk_reset_table,
>> + .clk_rst_tbl_size = ARRAY_SIZE(glymur_clk_reset_table),
>> + .bw_tbl_dec = sm8550_bw_table_dec,
>> + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec),
>> + .pmdomain_tbl = glymur_pmdomain_table,
>> + .pmdomain_tbl_size = ARRAY_SIZE(glymur_pmdomain_table),
>> + .opp_pd_tbl = sm8550_opp_pd_table,
>> + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table),
>> + .clk_tbl = glymur_clk_table,
>> + .clk_tbl_size = ARRAY_SIZE(glymur_clk_table),
>> + .opp_clk_tbl = glymur_opp_clk_table,
>> + /* Upper bound of DMA address range */
>> + .dma_mask = 0xffe00000 - 1,
>> + .fwname = "qcom/vpu/vpu36_p4_s7.mbn",
>> + .pas_id = IRIS_PAS_ID,
>> + .dual_core = true,
>> + .inst_iris_fmts = platform_fmts_sm8550_dec,
>> + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec),
>> + .inst_caps = &platform_inst_cap_sm8550,
>> + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec,
>> + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec),
>> + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc,
>> + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc),
>> + .tz_cp_config_data = tz_cp_config_glymur,
>> + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_glymur),
>> + .core_arch = VIDEO_ARCH_LX,
>> + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE,
>> + .ubwc_config = &ubwc_config_sm8550,
>> + .num_vpp_pipe = 4,
>> + .max_session_count = 16,
>> + .max_core_mbpf = NUM_MBS_8K * 2,
>> + .max_core_mbps = ((8192 * 4320) / 256) * 60,
>> + .dec_input_config_params_default =
>> + sm8550_vdec_input_config_params_default,
>> + .dec_input_config_params_default_size =
>> + ARRAY_SIZE(sm8550_vdec_input_config_params_default),
>> + .dec_input_config_params_hevc =
>> + sm8550_vdec_input_config_param_hevc,
>> + .dec_input_config_params_hevc_size =
>> + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc),
>> + .dec_input_config_params_vp9 =
>> + sm8550_vdec_input_config_param_vp9,
>> + .dec_input_config_params_vp9_size =
>> + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9),
>> + .dec_input_config_params_av1 =
>> + sm8550_vdec_input_config_param_av1,
>> + .dec_input_config_params_av1_size =
>> + ARRAY_SIZE(sm8550_vdec_input_config_param_av1),
>> + .dec_output_config_params =
>> + sm8550_vdec_output_config_params,
>> + .dec_output_config_params_size =
>> + ARRAY_SIZE(sm8550_vdec_output_config_params),
>> +
>> + .enc_input_config_params =
>> + sm8550_venc_input_config_params,
>> + .enc_input_config_params_size =
>> + ARRAY_SIZE(sm8550_venc_input_config_params),
>> + .enc_output_config_params =
>> + sm8550_venc_output_config_params,
>> + .enc_output_config_params_size =
>> + ARRAY_SIZE(sm8550_venc_output_config_params),
>> +
>> + .dec_input_prop = sm8550_vdec_subscribe_input_properties,
>> + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties),
>> + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc,
>> + .dec_output_prop_avc_size =
>> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc),
>> + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc,
>> + .dec_output_prop_hevc_size =
>> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc),
>> + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9,
>> + .dec_output_prop_vp9_size =
>> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9),
>> + .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1,
>> + .dec_output_prop_av1_size =
>> + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1),
>> +
>> + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl,
>> + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl),
>> + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl,
>> + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
>> +
>> + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl,
>> + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl),
>> + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl,
>> + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl),
>> +};
>> +
>> const struct iris_platform_data sm8550_data = {
>> .get_instance = iris_hfi_gen2_get_instance,
>> .init_hfi_command_ops = iris_hfi_gen2_command_ops_init,
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.c b/drivers/media/platform/qcom/iris/iris_platform_glymur.c
>> new file mode 100644
>> index 000000000000..64b150db9f73
>> --- /dev/null
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.c
>> @@ -0,0 +1,93 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/media/qcom,glymur-iris.h>
>> +#include "iris_core.h"
>> +#include "iris_platform_common.h"
>> +#include "iris_platform_glymur.h"
>> +
>> +#define VIDEO_REGION_SECURE_FW_REGION_ID 0
>> +#define VIDEO_REGION_VM0_SECURE_NP_ID 1
>> +#define VIDEO_REGION_VM0_NONSECURE_NP_ID 5
> These are not glymur-specific, are they?

It's common for upcoming platforms as well. I'll move this to common
platform header.

>> +
>> +const struct platform_clk_data glymur_clk_table[] = {
>> + {IRIS_AXI_VCODEC_CLK, "iface" },
>> + {IRIS_CTRL_CLK, "core" },
>> + {IRIS_VCODEC_CLK, "vcodec0_core" },
>> + {IRIS_AXI_CTRL_CLK, "iface_ctrl" },
>> + {IRIS_CTRL_FREERUN_CLK, "core_freerun" },
>> + {IRIS_VCODEC_FREERUN_CLK, "vcodec0_core_freerun" },
>> + {IRIS_AXI_VCODEC1_CLK, "iface1" },
>> + {IRIS_VCODEC1_CLK, "vcodec1_core" },
>> + {IRIS_VCODEC1_FREERUN_CLK, "vcodec1_core_freerun" },
>> +};
>> +
>> +const char * const glymur_clk_reset_table[] = {
>> + "bus0",
>> + "bus_ctrl",
>> + "core",
>> + "vcodec0_core",
>> + "bus1",
>> + "vcodec1_core",
>> +};
>> +
>> +const char * const glymur_opp_clk_table[] = {
>> + "vcodec0_core",
>> + "vcodec1_core",
>> + "core",
>> + NULL,
>> +};
>> +
>> +const char * const glymur_pmdomain_table[] = {
>> + "venus",
>> + "vcodec0",
>> + "vcodec1",
>> +};
>> +
>> +const struct tz_cp_config tz_cp_config_glymur[] = {
>> + {
>> + .cp_start = VIDEO_REGION_SECURE_FW_REGION_ID,
>> + .cp_size = 0,
>> + .cp_nonpixel_start = 0,
>> + .cp_nonpixel_size = 0x1000000,
>> + },
>> + {
>> + .cp_start = VIDEO_REGION_VM0_SECURE_NP_ID,
>> + .cp_size = 0,
>> + .cp_nonpixel_start = 0x1000000,
>> + .cp_nonpixel_size = 0x24800000,
>> + },
>> + {
>> + .cp_start = VIDEO_REGION_VM0_NONSECURE_NP_ID,
>> + .cp_size = 0,
>> + .cp_nonpixel_start = 0x25800000,
>> + .cp_nonpixel_size = 0xda600000,
>> + },
>> +};
>> +
>> +int glymur_init_cb_devs(struct iris_core *core)
>> +{
>> + const u32 f_id = IRIS_FIRMWARE;
>> + struct device *dev;
>> +
>> + dev = iris_create_cb_dev(core, "iris_firmware", &f_id);
>> + if (IS_ERR(dev))
>> + return PTR_ERR(dev);
>> +
>> + if (device_iommu_mapped(dev))
>> + core->dev_fw = dev;
>> + else
>> + device_unregister(dev);
>> +
>> + return 0;
>> +}
>> +
>> +void glymur_deinit_cb_devs(struct iris_core *core)
>> +{
>> + if (core->dev_fw)
>> + device_unregister(core->dev_fw);
>> +
>> + core->dev_fw = NULL;
> Why do you need to set it to NULL?

Not needed, I'll drop it.

Thanks,
Vishnu Reddy.

>> +}
>> diff --git a/drivers/media/platform/qcom/iris/iris_platform_glymur.h b/drivers/media/platform/qcom/iris/iris_platform_glymur.h
>> new file mode 100644
>> index 000000000000..03c83922f0d9
>> --- /dev/null
>> +++ b/drivers/media/platform/qcom/iris/iris_platform_glymur.h
>> @@ -0,0 +1,17 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/*
>> + * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef __IRIS_PLATFORM_GLYMUR_H__
>> +#define __IRIS_PLATFORM_GLYMUR_H__
>> +
>> +extern const struct platform_clk_data glymur_clk_table[9];
>> +extern const char * const glymur_clk_reset_table[6];
>> +extern const char * const glymur_opp_clk_table[4];
>> +extern const char * const glymur_pmdomain_table[3];
>> +extern const struct tz_cp_config tz_cp_config_glymur[3];
>> +int glymur_init_cb_devs(struct iris_core *core);
>> +void glymur_deinit_cb_devs(struct iris_core *core);
>> +
>> +#endif
>> diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/platform/qcom/iris/iris_probe.c
>> index 34751912f871..53869d9113d5 100644
>> --- a/drivers/media/platform/qcom/iris/iris_probe.c
>> +++ b/drivers/media/platform/qcom/iris/iris_probe.c
>> @@ -369,6 +369,10 @@ static const struct dev_pm_ops iris_pm_ops = {
>> };
>>
>> static const struct of_device_id iris_dt_match[] = {
>> + {
>> + .compatible = "qcom,glymur-iris",
>> + .data = &glymur_data,
>> + },
>> {
>> .compatible = "qcom,qcs8300-iris",
>> .data = &qcs8300_data,
>>
>> --
>> 2.34.1
>>