* [PATCH 6/7] V4L/DVB: tm6000: add request to registers of the group 05 [not found] <cover.1268311636.git.mchehab@redhat.com> @ 2010-03-11 13:26 ` Mauro Carvalho Chehab 2010-03-11 13:26 ` [PATCH 5/7] V4L/DVB: tm6000: Replace naming convention for registers of req 05 group Mauro Carvalho Chehab ` (5 subsequent siblings) 6 siblings, 0 replies; 7+ messages in thread From: Mauro Carvalho Chehab @ 2010-03-11 13:26 UTC (permalink / raw) To: linux-media Yet another script magic. This time, the change were generated by this script: cat tm6000-regs.h |perl -ne 'if (m/^(\#define TM6010_REQ)(05)([^\s]+)(\s+)0x([A-F0-9].)/) { \ $name="$1$2$3"; $sp=$4; $req=$2; $val=$5; $val=~tr/A-F/a-f/; \ printf "$name%s0x%s, 0x%s\n", $sp, $req, $val; } else { print $_ }' \ >a; mv a tm6000-regs.h Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> diff --git a/drivers/staging/tm6000/tm6000-regs.h b/drivers/staging/tm6000/tm6000-regs.h index 6be16b7..1c5289c 100644 --- a/drivers/staging/tm6000/tm6000-regs.h +++ b/drivers/staging/tm6000/tm6000-regs.h @@ -280,202 +280,202 @@ enum { #define TM6010_REQ07_RFF_SOFT_RESET 0x07, 0xff /* Define TM6000/TM6010 USB registers */ -#define TM6010_REQ05_R00_MAIN_CTRL 0x00 -#define TM6010_REQ05_R01_DEVADDR 0x01 -#define TM6010_REQ05_R02_TEST 0x02 -#define TM6010_REQ05_R04_SOFN0 0x04 -#define TM6010_REQ05_R05_SOFN1 0x05 -#define TM6010_REQ05_R06_SOFTM0 0x06 -#define TM6010_REQ05_R07_SOFTM1 0x07 -#define TM6010_REQ05_R08_PHY_TEST 0x08 -#define TM6010_REQ05_R09_VCTL 0x09 -#define TM6010_REQ05_R0A_VSTA 0x0A -#define TM6010_REQ05_R0B_CX_CFG 0x0B -#define TM6010_REQ05_R0C_ENDP0_REG0 0x0C -#define TM6010_REQ05_R10_GMASK 0x10 -#define TM6010_REQ05_R11_IMASK0 0x11 -#define TM6010_REQ05_R12_IMASK1 0x12 -#define TM6010_REQ05_R13_IMASK2 0x13 -#define TM6010_REQ05_R14_IMASK3 0x14 -#define TM6010_REQ05_R15_IMASK4 0x15 -#define TM6010_REQ05_R16_IMASK5 0x16 -#define TM6010_REQ05_R17_IMASK6 0x17 -#define TM6010_REQ05_R18_IMASK7 0x18 -#define TM6010_REQ05_R19_ZEROP0 0x19 -#define TM6010_REQ05_R1A_ZEROP1 0x1A -#define TM6010_REQ05_R1C_FIFO_EMP0 0x1C -#define TM6010_REQ05_R1D_FIFO_EMP1 0x1D -#define TM6010_REQ05_R20_IRQ_GROUP 0x20 -#define TM6010_REQ05_R21_IRQ_SOURCE0 0x21 -#define TM6010_REQ05_R22_IRQ_SOURCE1 0x22 -#define TM6010_REQ05_R23_IRQ_SOURCE2 0x23 -#define TM6010_REQ05_R24_IRQ_SOURCE3 0x24 -#define TM6010_REQ05_R25_IRQ_SOURCE4 0x25 -#define TM6010_REQ05_R26_IRQ_SOURCE5 0x26 -#define TM6010_REQ05_R27_IRQ_SOURCE6 0x27 -#define TM6010_REQ05_R28_IRQ_SOURCE7 0x28 -#define TM6010_REQ05_R29_SEQ_ERR0 0x29 -#define TM6010_REQ05_R2A_SEQ_ERR1 0x2A -#define TM6010_REQ05_R2B_SEQ_ABORT0 0x2B -#define TM6010_REQ05_R2C_SEQ_ABORT1 0x2C -#define TM6010_REQ05_R2D_TX_ZERO0 0x2D -#define TM6010_REQ05_R2E_TX_ZERO1 0x2E -#define TM6010_REQ05_R2F_IDLE_CNT 0x2F -#define TM6010_REQ05_R30_FNO_P1 0x30 -#define TM6010_REQ05_R31_FNO_P2 0x31 -#define TM6010_REQ05_R32_FNO_P3 0x32 -#define TM6010_REQ05_R33_FNO_P4 0x33 -#define TM6010_REQ05_R34_FNO_P5 0x34 -#define TM6010_REQ05_R35_FNO_P6 0x35 -#define TM6010_REQ05_R36_FNO_P7 0x36 -#define TM6010_REQ05_R37_FNO_P8 0x37 -#define TM6010_REQ05_R38_FNO_P9 0x38 -#define TM6010_REQ05_R30_FNO_P10 0x39 -#define TM6010_REQ05_R30_FNO_P11 0x3A -#define TM6010_REQ05_R30_FNO_P12 0x3B -#define TM6010_REQ05_R30_FNO_P13 0x3C -#define TM6010_REQ05_R30_FNO_P14 0x3D -#define TM6010_REQ05_R30_FNO_P15 0x3E -#define TM6010_REQ05_R40_IN_MAXPS_LOW1 0x40 -#define TM6010_REQ05_R41_IN_MAXPS_HIGH1 0x41 -#define TM6010_REQ05_R42_IN_MAXPS_LOW2 0x42 -#define TM6010_REQ05_R43_IN_MAXPS_HIGH2 0x43 -#define TM6010_REQ05_R44_IN_MAXPS_LOW3 0x44 -#define TM6010_REQ05_R45_IN_MAXPS_HIGH3 0x45 -#define TM6010_REQ05_R46_IN_MAXPS_LOW4 0x46 -#define TM6010_REQ05_R47_IN_MAXPS_HIGH4 0x47 -#define TM6010_REQ05_R48_IN_MAXPS_LOW5 0x48 -#define TM6010_REQ05_R49_IN_MAXPS_HIGH5 0x49 -#define TM6010_REQ05_R4A_IN_MAXPS_LOW6 0x4A -#define TM6010_REQ05_R4B_IN_MAXPS_HIGH6 0x4B -#define TM6010_REQ05_R4C_IN_MAXPS_LOW7 0x4C -#define TM6010_REQ05_R4D_IN_MAXPS_HIGH7 0x4D -#define TM6010_REQ05_R4E_IN_MAXPS_LOW8 0x4E -#define TM6010_REQ05_R4F_IN_MAXPS_HIGH8 0x4F -#define TM6010_REQ05_R50_IN_MAXPS_LOW9 0x50 -#define TM6010_REQ05_R51_IN_MAXPS_HIGH9 0x51 -#define TM6010_REQ05_R40_IN_MAXPS_LOW10 0x52 -#define TM6010_REQ05_R41_IN_MAXPS_HIGH10 0x53 -#define TM6010_REQ05_R40_IN_MAXPS_LOW11 0x54 -#define TM6010_REQ05_R41_IN_MAXPS_HIGH11 0x55 -#define TM6010_REQ05_R40_IN_MAXPS_LOW12 0x56 -#define TM6010_REQ05_R41_IN_MAXPS_HIGH12 0x57 -#define TM6010_REQ05_R40_IN_MAXPS_LOW13 0x58 -#define TM6010_REQ05_R41_IN_MAXPS_HIGH13 0x59 -#define TM6010_REQ05_R40_IN_MAXPS_LOW14 0x5A -#define TM6010_REQ05_R41_IN_MAXPS_HIGH14 0x5B -#define TM6010_REQ05_R40_IN_MAXPS_LOW15 0x5C -#define TM6010_REQ05_R41_IN_MAXPS_HIGH15 0x5D -#define TM6010_REQ05_R60_OUT_MAXPS_LOW1 0x60 -#define TM6010_REQ05_R61_OUT_MAXPS_HIGH1 0x61 -#define TM6010_REQ05_R62_OUT_MAXPS_LOW2 0x62 -#define TM6010_REQ05_R63_OUT_MAXPS_HIGH2 0x63 -#define TM6010_REQ05_R64_OUT_MAXPS_LOW3 0x64 -#define TM6010_REQ05_R65_OUT_MAXPS_HIGH3 0x65 -#define TM6010_REQ05_R66_OUT_MAXPS_LOW4 0x66 -#define TM6010_REQ05_R67_OUT_MAXPS_HIGH4 0x67 -#define TM6010_REQ05_R68_OUT_MAXPS_LOW5 0x68 -#define TM6010_REQ05_R69_OUT_MAXPS_HIGH5 0x69 -#define TM6010_REQ05_R6A_OUT_MAXPS_LOW6 0x6A -#define TM6010_REQ05_R6B_OUT_MAXPS_HIGH6 0x6B -#define TM6010_REQ05_R6C_OUT_MAXPS_LOW7 0x6C -#define TM6010_REQ05_R6D_OUT_MAXPS_HIGH7 0x6D -#define TM6010_REQ05_R6E_OUT_MAXPS_LOW8 0x6E -#define TM6010_REQ05_R6F_OUT_MAXPS_HIGH8 0x6F -#define TM6010_REQ05_R70_OUT_MAXPS_LOW9 0x70 -#define TM6010_REQ05_R71_OUT_MAXPS_HIGH9 0x71 -#define TM6010_REQ05_R60_OUT_MAXPS_LOW10 0x72 -#define TM6010_REQ05_R61_OUT_MAXPS_HIGH10 0x73 -#define TM6010_REQ05_R60_OUT_MAXPS_LOW11 0x74 -#define TM6010_REQ05_R61_OUT_MAXPS_HIGH11 0x75 -#define TM6010_REQ05_R60_OUT_MAXPS_LOW12 0x76 -#define TM6010_REQ05_R61_OUT_MAXPS_HIGH12 0x77 -#define TM6010_REQ05_R60_OUT_MAXPS_LOW13 0x78 -#define TM6010_REQ05_R61_OUT_MAXPS_HIGH13 0x79 -#define TM6010_REQ05_R60_OUT_MAXPS_LOW14 0x7A -#define TM6010_REQ05_R61_OUT_MAXPS_HIGH14 0x7B -#define TM6010_REQ05_R60_OUT_MAXPS_LOW15 0x7C -#define TM6010_REQ05_R61_OUT_MAXPS_HIGH15 0x7D -#define TM6010_REQ05_R80_FIFO0 0x80 -#define TM6010_REQ05_R81_FIFO1 0x81 -#define TM6010_REQ05_R82_FIFO2 0x82 -#define TM6010_REQ05_R83_FIFO3 0x83 -#define TM6010_REQ05_R84_FIFO4 0x84 -#define TM6010_REQ05_R85_FIFO5 0x85 -#define TM6010_REQ05_R86_FIFO6 0x86 -#define TM6010_REQ05_R87_FIFO7 0x87 -#define TM6010_REQ05_R88_FIFO8 0x88 -#define TM6010_REQ05_R89_FIFO9 0x89 -#define TM6010_REQ05_R81_FIFO10 0x8A -#define TM6010_REQ05_R81_FIFO11 0x8B -#define TM6010_REQ05_R81_FIFO12 0x8C -#define TM6010_REQ05_R81_FIFO13 0x8D -#define TM6010_REQ05_R81_FIFO14 0x8E -#define TM6010_REQ05_R81_FIFO15 0x8F -#define TM6010_REQ05_R90_CFG_FIFO0 0x90 -#define TM6010_REQ05_R91_CFG_FIFO1 0x91 -#define TM6010_REQ05_R92_CFG_FIFO2 0x92 -#define TM6010_REQ05_R93_CFG_FIFO3 0x93 -#define TM6010_REQ05_R94_CFG_FIFO4 0x94 -#define TM6010_REQ05_R95_CFG_FIFO5 0x95 -#define TM6010_REQ05_R96_CFG_FIFO6 0x96 -#define TM6010_REQ05_R97_CFG_FIFO7 0x97 -#define TM6010_REQ05_R98_CFG_FIFO8 0x98 -#define TM6010_REQ05_R99_CFG_FIFO9 0x99 -#define TM6010_REQ05_R91_CFG_FIFO10 0x9A -#define TM6010_REQ05_R91_CFG_FIFO11 0x9B -#define TM6010_REQ05_R91_CFG_FIFO12 0x9C -#define TM6010_REQ05_R91_CFG_FIFO13 0x9D -#define TM6010_REQ05_R91_CFG_FIFO14 0x9E -#define TM6010_REQ05_R91_CFG_FIFO15 0x9F -#define TM6010_REQ05_RA0_CTL_FIFO0 0xA0 -#define TM6010_REQ05_RA1_CTL_FIFO1 0xA1 -#define TM6010_REQ05_RA2_CTL_FIFO2 0xA2 -#define TM6010_REQ05_RA3_CTL_FIFO3 0xA3 -#define TM6010_REQ05_RA4_CTL_FIFO4 0xA4 -#define TM6010_REQ05_RA5_CTL_FIFO5 0xA5 -#define TM6010_REQ05_RA6_CTL_FIFO6 0xA6 -#define TM6010_REQ05_RA7_CTL_FIFO7 0xA7 -#define TM6010_REQ05_RA8_CTL_FIFO8 0xA8 -#define TM6010_REQ05_RA9_CTL_FIFO9 0xA9 -#define TM6010_REQ05_RA1_CTL_FIFO10 0xAA -#define TM6010_REQ05_RA1_CTL_FIFO11 0xAB -#define TM6010_REQ05_RA1_CTL_FIFO12 0xAC -#define TM6010_REQ05_RA1_CTL_FIFO13 0xAD -#define TM6010_REQ05_RA1_CTL_FIFO14 0xAE -#define TM6010_REQ05_RA1_CTL_FIFO15 0xAF -#define TM6010_REQ05_RB0_BC_LOW_FIFO0 0xB0 -#define TM6010_REQ05_RB1_BC_LOW_FIFO1 0xB1 -#define TM6010_REQ05_RB2_BC_LOW_FIFO2 0xB2 -#define TM6010_REQ05_RB3_BC_LOW_FIFO3 0xB3 -#define TM6010_REQ05_RB4_BC_LOW_FIFO4 0xB4 -#define TM6010_REQ05_RB5_BC_LOW_FIFO5 0xB5 -#define TM6010_REQ05_RB6_BC_LOW_FIFO6 0xB6 -#define TM6010_REQ05_RB7_BC_LOW_FIFO7 0xB7 -#define TM6010_REQ05_RB8_BC_LOW_FIFO8 0xB8 -#define TM6010_REQ05_RB9_BC_LOW_FIFO9 0xB9 -#define TM6010_REQ05_RB1_BC_LOW_FIFO10 0xBA -#define TM6010_REQ05_RB1_BC_LOW_FIFO11 0xBB -#define TM6010_REQ05_RB1_BC_LOW_FIFO12 0xBC -#define TM6010_REQ05_RB1_BC_LOW_FIFO13 0xBD -#define TM6010_REQ05_RB1_BC_LOW_FIFO14 0xBE -#define TM6010_REQ05_RB1_BC_LOW_FIFO15 0xBF -#define TM6010_REQ05_RC0_DATA_FIFO0 0xC0 -#define TM6010_REQ05_RC4_DATA_FIFO1 0xC4 -#define TM6010_REQ05_RC8_DATA_FIFO2 0xC8 -#define TM6010_REQ05_RCC_DATA_FIFO3 0xCC -#define TM6010_REQ05_RD0_DATA_FIFO4 0xD0 -#define TM6010_REQ05_RD4_DATA_FIFO5 0xD4 -#define TM6010_REQ05_RD8_DATA_FIFO6 0xD8 -#define TM6010_REQ05_RDC_DATA_FIFO7 0xDC -#define TM6010_REQ05_RE0_DATA_FIFO8 0xE0 -#define TM6010_REQ05_RE4_DATA_FIFO9 0xE4 -#define TM6010_REQ05_RC4_DATA_FIFO10 0xE8 -#define TM6010_REQ05_RC4_DATA_FIFO11 0xEC -#define TM6010_REQ05_RC4_DATA_FIFO12 0xF0 -#define TM6010_REQ05_RC4_DATA_FIFO13 0xF4 -#define TM6010_REQ05_RC4_DATA_FIFO14 0xF8 -#define TM6010_REQ05_RC4_DATA_FIFO15 0xFC +#define TM6010_REQ05_R00_MAIN_CTRL 0x05, 0x00 +#define TM6010_REQ05_R01_DEVADDR 0x05, 0x01 +#define TM6010_REQ05_R02_TEST 0x05, 0x02 +#define TM6010_REQ05_R04_SOFN0 0x05, 0x04 +#define TM6010_REQ05_R05_SOFN1 0x05, 0x05 +#define TM6010_REQ05_R06_SOFTM0 0x05, 0x06 +#define TM6010_REQ05_R07_SOFTM1 0x05, 0x07 +#define TM6010_REQ05_R08_PHY_TEST 0x05, 0x08 +#define TM6010_REQ05_R09_VCTL 0x05, 0x09 +#define TM6010_REQ05_R0A_VSTA 0x05, 0x0a +#define TM6010_REQ05_R0B_CX_CFG 0x05, 0x0b +#define TM6010_REQ05_R0C_ENDP0_REG0 0x05, 0x0c +#define TM6010_REQ05_R10_GMASK 0x05, 0x10 +#define TM6010_REQ05_R11_IMASK0 0x05, 0x11 +#define TM6010_REQ05_R12_IMASK1 0x05, 0x12 +#define TM6010_REQ05_R13_IMASK2 0x05, 0x13 +#define TM6010_REQ05_R14_IMASK3 0x05, 0x14 +#define TM6010_REQ05_R15_IMASK4 0x05, 0x15 +#define TM6010_REQ05_R16_IMASK5 0x05, 0x16 +#define TM6010_REQ05_R17_IMASK6 0x05, 0x17 +#define TM6010_REQ05_R18_IMASK7 0x05, 0x18 +#define TM6010_REQ05_R19_ZEROP0 0x05, 0x19 +#define TM6010_REQ05_R1A_ZEROP1 0x05, 0x1a +#define TM6010_REQ05_R1C_FIFO_EMP0 0x05, 0x1c +#define TM6010_REQ05_R1D_FIFO_EMP1 0x05, 0x1d +#define TM6010_REQ05_R20_IRQ_GROUP 0x05, 0x20 +#define TM6010_REQ05_R21_IRQ_SOURCE0 0x05, 0x21 +#define TM6010_REQ05_R22_IRQ_SOURCE1 0x05, 0x22 +#define TM6010_REQ05_R23_IRQ_SOURCE2 0x05, 0x23 +#define TM6010_REQ05_R24_IRQ_SOURCE3 0x05, 0x24 +#define TM6010_REQ05_R25_IRQ_SOURCE4 0x05, 0x25 +#define TM6010_REQ05_R26_IRQ_SOURCE5 0x05, 0x26 +#define TM6010_REQ05_R27_IRQ_SOURCE6 0x05, 0x27 +#define TM6010_REQ05_R28_IRQ_SOURCE7 0x05, 0x28 +#define TM6010_REQ05_R29_SEQ_ERR0 0x05, 0x29 +#define TM6010_REQ05_R2A_SEQ_ERR1 0x05, 0x2a +#define TM6010_REQ05_R2B_SEQ_ABORT0 0x05, 0x2b +#define TM6010_REQ05_R2C_SEQ_ABORT1 0x05, 0x2c +#define TM6010_REQ05_R2D_TX_ZERO0 0x05, 0x2d +#define TM6010_REQ05_R2E_TX_ZERO1 0x05, 0x2e +#define TM6010_REQ05_R2F_IDLE_CNT 0x05, 0x2f +#define TM6010_REQ05_R30_FNO_P1 0x05, 0x30 +#define TM6010_REQ05_R31_FNO_P2 0x05, 0x31 +#define TM6010_REQ05_R32_FNO_P3 0x05, 0x32 +#define TM6010_REQ05_R33_FNO_P4 0x05, 0x33 +#define TM6010_REQ05_R34_FNO_P5 0x05, 0x34 +#define TM6010_REQ05_R35_FNO_P6 0x05, 0x35 +#define TM6010_REQ05_R36_FNO_P7 0x05, 0x36 +#define TM6010_REQ05_R37_FNO_P8 0x05, 0x37 +#define TM6010_REQ05_R38_FNO_P9 0x05, 0x38 +#define TM6010_REQ05_R30_FNO_P10 0x05, 0x39 +#define TM6010_REQ05_R30_FNO_P11 0x05, 0x3a +#define TM6010_REQ05_R30_FNO_P12 0x05, 0x3b +#define TM6010_REQ05_R30_FNO_P13 0x05, 0x3c +#define TM6010_REQ05_R30_FNO_P14 0x05, 0x3d +#define TM6010_REQ05_R30_FNO_P15 0x05, 0x3e +#define TM6010_REQ05_R40_IN_MAXPS_LOW1 0x05, 0x40 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH1 0x05, 0x41 +#define TM6010_REQ05_R42_IN_MAXPS_LOW2 0x05, 0x42 +#define TM6010_REQ05_R43_IN_MAXPS_HIGH2 0x05, 0x43 +#define TM6010_REQ05_R44_IN_MAXPS_LOW3 0x05, 0x44 +#define TM6010_REQ05_R45_IN_MAXPS_HIGH3 0x05, 0x45 +#define TM6010_REQ05_R46_IN_MAXPS_LOW4 0x05, 0x46 +#define TM6010_REQ05_R47_IN_MAXPS_HIGH4 0x05, 0x47 +#define TM6010_REQ05_R48_IN_MAXPS_LOW5 0x05, 0x48 +#define TM6010_REQ05_R49_IN_MAXPS_HIGH5 0x05, 0x49 +#define TM6010_REQ05_R4A_IN_MAXPS_LOW6 0x05, 0x4a +#define TM6010_REQ05_R4B_IN_MAXPS_HIGH6 0x05, 0x4b +#define TM6010_REQ05_R4C_IN_MAXPS_LOW7 0x05, 0x4c +#define TM6010_REQ05_R4D_IN_MAXPS_HIGH7 0x05, 0x4d +#define TM6010_REQ05_R4E_IN_MAXPS_LOW8 0x05, 0x4e +#define TM6010_REQ05_R4F_IN_MAXPS_HIGH8 0x05, 0x4f +#define TM6010_REQ05_R50_IN_MAXPS_LOW9 0x05, 0x50 +#define TM6010_REQ05_R51_IN_MAXPS_HIGH9 0x05, 0x51 +#define TM6010_REQ05_R40_IN_MAXPS_LOW10 0x05, 0x52 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH10 0x05, 0x53 +#define TM6010_REQ05_R40_IN_MAXPS_LOW11 0x05, 0x54 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH11 0x05, 0x55 +#define TM6010_REQ05_R40_IN_MAXPS_LOW12 0x05, 0x56 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH12 0x05, 0x57 +#define TM6010_REQ05_R40_IN_MAXPS_LOW13 0x05, 0x58 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH13 0x05, 0x59 +#define TM6010_REQ05_R40_IN_MAXPS_LOW14 0x05, 0x5a +#define TM6010_REQ05_R41_IN_MAXPS_HIGH14 0x05, 0x5b +#define TM6010_REQ05_R40_IN_MAXPS_LOW15 0x05, 0x5c +#define TM6010_REQ05_R41_IN_MAXPS_HIGH15 0x05, 0x5d +#define TM6010_REQ05_R60_OUT_MAXPS_LOW1 0x05, 0x60 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH1 0x05, 0x61 +#define TM6010_REQ05_R62_OUT_MAXPS_LOW2 0x05, 0x62 +#define TM6010_REQ05_R63_OUT_MAXPS_HIGH2 0x05, 0x63 +#define TM6010_REQ05_R64_OUT_MAXPS_LOW3 0x05, 0x64 +#define TM6010_REQ05_R65_OUT_MAXPS_HIGH3 0x05, 0x65 +#define TM6010_REQ05_R66_OUT_MAXPS_LOW4 0x05, 0x66 +#define TM6010_REQ05_R67_OUT_MAXPS_HIGH4 0x05, 0x67 +#define TM6010_REQ05_R68_OUT_MAXPS_LOW5 0x05, 0x68 +#define TM6010_REQ05_R69_OUT_MAXPS_HIGH5 0x05, 0x69 +#define TM6010_REQ05_R6A_OUT_MAXPS_LOW6 0x05, 0x6a +#define TM6010_REQ05_R6B_OUT_MAXPS_HIGH6 0x05, 0x6b +#define TM6010_REQ05_R6C_OUT_MAXPS_LOW7 0x05, 0x6c +#define TM6010_REQ05_R6D_OUT_MAXPS_HIGH7 0x05, 0x6d +#define TM6010_REQ05_R6E_OUT_MAXPS_LOW8 0x05, 0x6e +#define TM6010_REQ05_R6F_OUT_MAXPS_HIGH8 0x05, 0x6f +#define TM6010_REQ05_R70_OUT_MAXPS_LOW9 0x05, 0x70 +#define TM6010_REQ05_R71_OUT_MAXPS_HIGH9 0x05, 0x71 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW10 0x05, 0x72 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH10 0x05, 0x73 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW11 0x05, 0x74 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH11 0x05, 0x75 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW12 0x05, 0x76 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH12 0x05, 0x77 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW13 0x05, 0x78 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH13 0x05, 0x79 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW14 0x05, 0x7a +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH14 0x05, 0x7b +#define TM6010_REQ05_R60_OUT_MAXPS_LOW15 0x05, 0x7c +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH15 0x05, 0x7d +#define TM6010_REQ05_R80_FIFO0 0x05, 0x80 +#define TM6010_REQ05_R81_FIFO1 0x05, 0x81 +#define TM6010_REQ05_R82_FIFO2 0x05, 0x82 +#define TM6010_REQ05_R83_FIFO3 0x05, 0x83 +#define TM6010_REQ05_R84_FIFO4 0x05, 0x84 +#define TM6010_REQ05_R85_FIFO5 0x05, 0x85 +#define TM6010_REQ05_R86_FIFO6 0x05, 0x86 +#define TM6010_REQ05_R87_FIFO7 0x05, 0x87 +#define TM6010_REQ05_R88_FIFO8 0x05, 0x88 +#define TM6010_REQ05_R89_FIFO9 0x05, 0x89 +#define TM6010_REQ05_R81_FIFO10 0x05, 0x8a +#define TM6010_REQ05_R81_FIFO11 0x05, 0x8b +#define TM6010_REQ05_R81_FIFO12 0x05, 0x8c +#define TM6010_REQ05_R81_FIFO13 0x05, 0x8d +#define TM6010_REQ05_R81_FIFO14 0x05, 0x8e +#define TM6010_REQ05_R81_FIFO15 0x05, 0x8f +#define TM6010_REQ05_R90_CFG_FIFO0 0x05, 0x90 +#define TM6010_REQ05_R91_CFG_FIFO1 0x05, 0x91 +#define TM6010_REQ05_R92_CFG_FIFO2 0x05, 0x92 +#define TM6010_REQ05_R93_CFG_FIFO3 0x05, 0x93 +#define TM6010_REQ05_R94_CFG_FIFO4 0x05, 0x94 +#define TM6010_REQ05_R95_CFG_FIFO5 0x05, 0x95 +#define TM6010_REQ05_R96_CFG_FIFO6 0x05, 0x96 +#define TM6010_REQ05_R97_CFG_FIFO7 0x05, 0x97 +#define TM6010_REQ05_R98_CFG_FIFO8 0x05, 0x98 +#define TM6010_REQ05_R99_CFG_FIFO9 0x05, 0x99 +#define TM6010_REQ05_R91_CFG_FIFO10 0x05, 0x9a +#define TM6010_REQ05_R91_CFG_FIFO11 0x05, 0x9b +#define TM6010_REQ05_R91_CFG_FIFO12 0x05, 0x9c +#define TM6010_REQ05_R91_CFG_FIFO13 0x05, 0x9d +#define TM6010_REQ05_R91_CFG_FIFO14 0x05, 0x9e +#define TM6010_REQ05_R91_CFG_FIFO15 0x05, 0x9f +#define TM6010_REQ05_RA0_CTL_FIFO0 0x05, 0xa0 +#define TM6010_REQ05_RA1_CTL_FIFO1 0x05, 0xa1 +#define TM6010_REQ05_RA2_CTL_FIFO2 0x05, 0xa2 +#define TM6010_REQ05_RA3_CTL_FIFO3 0x05, 0xa3 +#define TM6010_REQ05_RA4_CTL_FIFO4 0x05, 0xa4 +#define TM6010_REQ05_RA5_CTL_FIFO5 0x05, 0xa5 +#define TM6010_REQ05_RA6_CTL_FIFO6 0x05, 0xa6 +#define TM6010_REQ05_RA7_CTL_FIFO7 0x05, 0xa7 +#define TM6010_REQ05_RA8_CTL_FIFO8 0x05, 0xa8 +#define TM6010_REQ05_RA9_CTL_FIFO9 0x05, 0xa9 +#define TM6010_REQ05_RA1_CTL_FIFO10 0x05, 0xaa +#define TM6010_REQ05_RA1_CTL_FIFO11 0x05, 0xab +#define TM6010_REQ05_RA1_CTL_FIFO12 0x05, 0xac +#define TM6010_REQ05_RA1_CTL_FIFO13 0x05, 0xad +#define TM6010_REQ05_RA1_CTL_FIFO14 0x05, 0xae +#define TM6010_REQ05_RA1_CTL_FIFO15 0x05, 0xaf +#define TM6010_REQ05_RB0_BC_LOW_FIFO0 0x05, 0xb0 +#define TM6010_REQ05_RB1_BC_LOW_FIFO1 0x05, 0xb1 +#define TM6010_REQ05_RB2_BC_LOW_FIFO2 0x05, 0xb2 +#define TM6010_REQ05_RB3_BC_LOW_FIFO3 0x05, 0xb3 +#define TM6010_REQ05_RB4_BC_LOW_FIFO4 0x05, 0xb4 +#define TM6010_REQ05_RB5_BC_LOW_FIFO5 0x05, 0xb5 +#define TM6010_REQ05_RB6_BC_LOW_FIFO6 0x05, 0xb6 +#define TM6010_REQ05_RB7_BC_LOW_FIFO7 0x05, 0xb7 +#define TM6010_REQ05_RB8_BC_LOW_FIFO8 0x05, 0xb8 +#define TM6010_REQ05_RB9_BC_LOW_FIFO9 0x05, 0xb9 +#define TM6010_REQ05_RB1_BC_LOW_FIFO10 0x05, 0xba +#define TM6010_REQ05_RB1_BC_LOW_FIFO11 0x05, 0xbb +#define TM6010_REQ05_RB1_BC_LOW_FIFO12 0x05, 0xbc +#define TM6010_REQ05_RB1_BC_LOW_FIFO13 0x05, 0xbd +#define TM6010_REQ05_RB1_BC_LOW_FIFO14 0x05, 0xbe +#define TM6010_REQ05_RB1_BC_LOW_FIFO15 0x05, 0xbf +#define TM6010_REQ05_RC0_DATA_FIFO0 0x05, 0xc0 +#define TM6010_REQ05_RC4_DATA_FIFO1 0x05, 0xc4 +#define TM6010_REQ05_RC8_DATA_FIFO2 0x05, 0xc8 +#define TM6010_REQ05_RCC_DATA_FIFO3 0x05, 0xcc +#define TM6010_REQ05_RD0_DATA_FIFO4 0x05, 0xd0 +#define TM6010_REQ05_RD4_DATA_FIFO5 0x05, 0xd4 +#define TM6010_REQ05_RD8_DATA_FIFO6 0x05, 0xd8 +#define TM6010_REQ05_RDC_DATA_FIFO7 0x05, 0xdc +#define TM6010_REQ05_RE0_DATA_FIFO8 0x05, 0xe0 +#define TM6010_REQ05_RE4_DATA_FIFO9 0x05, 0xe4 +#define TM6010_REQ05_RC4_DATA_FIFO10 0x05, 0xe8 +#define TM6010_REQ05_RC4_DATA_FIFO11 0x05, 0xec +#define TM6010_REQ05_RC4_DATA_FIFO12 0x05, 0xf0 +#define TM6010_REQ05_RC4_DATA_FIFO13 0x05, 0xf4 +#define TM6010_REQ05_RC4_DATA_FIFO14 0x05, 0xf8 +#define TM6010_REQ05_RC4_DATA_FIFO15 0x05, 0xfc /* Define TM6000/TM6010 Audio decoder registers */ #define TM6010_REQ08_R00_A_VERSION 0x08, 0x00 -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 5/7] V4L/DVB: tm6000: Replace naming convention for registers of req 05 group [not found] <cover.1268311636.git.mchehab@redhat.com> 2010-03-11 13:26 ` [PATCH 6/7] V4L/DVB: tm6000: add request to registers of the group 05 Mauro Carvalho Chehab @ 2010-03-11 13:26 ` Mauro Carvalho Chehab 2010-03-11 13:26 ` [PATCH 7/7] V4L/DVB: tm6000: replace occurences of req05 magic by a naming alias Mauro Carvalho Chehab ` (4 subsequent siblings) 6 siblings, 0 replies; 7+ messages in thread From: Mauro Carvalho Chehab @ 2010-03-11 13:26 UTC (permalink / raw) To: linux-media After looking at the "magic" registers, it is clear that usb registers belong to request 5. Replace them with this script: cat /tmp/reg3 |perl -ne 'if (m/define (TM6000_U_)([^\s]+)\s+0x([A-F0-9].)/) { \ $name=$2; $val=$3; printf "s,$1$2,TM6010_REQ05_R%s_%s,g\n", $val, $name; }' >a; sed -f a tm6000-regs.h >b; mv b tm6000-regs.h Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> diff --git a/drivers/staging/tm6000/tm6000-regs.h b/drivers/staging/tm6000/tm6000-regs.h index 631984a..6be16b7 100644 --- a/drivers/staging/tm6000/tm6000-regs.h +++ b/drivers/staging/tm6000/tm6000-regs.h @@ -280,202 +280,202 @@ enum { #define TM6010_REQ07_RFF_SOFT_RESET 0x07, 0xff /* Define TM6000/TM6010 USB registers */ -#define TM6000_U_MAIN_CTRL 0x00 -#define TM6000_U_DEVADDR 0x01 -#define TM6000_U_TEST 0x02 -#define TM6000_U_SOFN0 0x04 -#define TM6000_U_SOFN1 0x05 -#define TM6000_U_SOFTM0 0x06 -#define TM6000_U_SOFTM1 0x07 -#define TM6000_U_PHY_TEST 0x08 -#define TM6000_U_VCTL 0x09 -#define TM6000_U_VSTA 0x0A -#define TM6000_U_CX_CFG 0x0B -#define TM6000_U_ENDP0_REG0 0x0C -#define TM6000_U_GMASK 0x10 -#define TM6000_U_IMASK0 0x11 -#define TM6000_U_IMASK1 0x12 -#define TM6000_U_IMASK2 0x13 -#define TM6000_U_IMASK3 0x14 -#define TM6000_U_IMASK4 0x15 -#define TM6000_U_IMASK5 0x16 -#define TM6000_U_IMASK6 0x17 -#define TM6000_U_IMASK7 0x18 -#define TM6000_U_ZEROP0 0x19 -#define TM6000_U_ZEROP1 0x1A -#define TM6000_U_FIFO_EMP0 0x1C -#define TM6000_U_FIFO_EMP1 0x1D -#define TM6000_U_IRQ_GROUP 0x20 -#define TM6000_U_IRQ_SOURCE0 0x21 -#define TM6000_U_IRQ_SOURCE1 0x22 -#define TM6000_U_IRQ_SOURCE2 0x23 -#define TM6000_U_IRQ_SOURCE3 0x24 -#define TM6000_U_IRQ_SOURCE4 0x25 -#define TM6000_U_IRQ_SOURCE5 0x26 -#define TM6000_U_IRQ_SOURCE6 0x27 -#define TM6000_U_IRQ_SOURCE7 0x28 -#define TM6000_U_SEQ_ERR0 0x29 -#define TM6000_U_SEQ_ERR1 0x2A -#define TM6000_U_SEQ_ABORT0 0x2B -#define TM6000_U_SEQ_ABORT1 0x2C -#define TM6000_U_TX_ZERO0 0x2D -#define TM6000_U_TX_ZERO1 0x2E -#define TM6000_U_IDLE_CNT 0x2F -#define TM6000_U_FNO_P1 0x30 -#define TM6000_U_FNO_P2 0x31 -#define TM6000_U_FNO_P3 0x32 -#define TM6000_U_FNO_P4 0x33 -#define TM6000_U_FNO_P5 0x34 -#define TM6000_U_FNO_P6 0x35 -#define TM6000_U_FNO_P7 0x36 -#define TM6000_U_FNO_P8 0x37 -#define TM6000_U_FNO_P9 0x38 -#define TM6000_U_FNO_P10 0x39 -#define TM6000_U_FNO_P11 0x3A -#define TM6000_U_FNO_P12 0x3B -#define TM6000_U_FNO_P13 0x3C -#define TM6000_U_FNO_P14 0x3D -#define TM6000_U_FNO_P15 0x3E -#define TM6000_U_IN_MAXPS_LOW1 0x40 -#define TM6000_U_IN_MAXPS_HIGH1 0x41 -#define TM6000_U_IN_MAXPS_LOW2 0x42 -#define TM6000_U_IN_MAXPS_HIGH2 0x43 -#define TM6000_U_IN_MAXPS_LOW3 0x44 -#define TM6000_U_IN_MAXPS_HIGH3 0x45 -#define TM6000_U_IN_MAXPS_LOW4 0x46 -#define TM6000_U_IN_MAXPS_HIGH4 0x47 -#define TM6000_U_IN_MAXPS_LOW5 0x48 -#define TM6000_U_IN_MAXPS_HIGH5 0x49 -#define TM6000_U_IN_MAXPS_LOW6 0x4A -#define TM6000_U_IN_MAXPS_HIGH6 0x4B -#define TM6000_U_IN_MAXPS_LOW7 0x4C -#define TM6000_U_IN_MAXPS_HIGH7 0x4D -#define TM6000_U_IN_MAXPS_LOW8 0x4E -#define TM6000_U_IN_MAXPS_HIGH8 0x4F -#define TM6000_U_IN_MAXPS_LOW9 0x50 -#define TM6000_U_IN_MAXPS_HIGH9 0x51 -#define TM6000_U_IN_MAXPS_LOW10 0x52 -#define TM6000_U_IN_MAXPS_HIGH10 0x53 -#define TM6000_U_IN_MAXPS_LOW11 0x54 -#define TM6000_U_IN_MAXPS_HIGH11 0x55 -#define TM6000_U_IN_MAXPS_LOW12 0x56 -#define TM6000_U_IN_MAXPS_HIGH12 0x57 -#define TM6000_U_IN_MAXPS_LOW13 0x58 -#define TM6000_U_IN_MAXPS_HIGH13 0x59 -#define TM6000_U_IN_MAXPS_LOW14 0x5A -#define TM6000_U_IN_MAXPS_HIGH14 0x5B -#define TM6000_U_IN_MAXPS_LOW15 0x5C -#define TM6000_U_IN_MAXPS_HIGH15 0x5D -#define TM6000_U_OUT_MAXPS_LOW1 0x60 -#define TM6000_U_OUT_MAXPS_HIGH1 0x61 -#define TM6000_U_OUT_MAXPS_LOW2 0x62 -#define TM6000_U_OUT_MAXPS_HIGH2 0x63 -#define TM6000_U_OUT_MAXPS_LOW3 0x64 -#define TM6000_U_OUT_MAXPS_HIGH3 0x65 -#define TM6000_U_OUT_MAXPS_LOW4 0x66 -#define TM6000_U_OUT_MAXPS_HIGH4 0x67 -#define TM6000_U_OUT_MAXPS_LOW5 0x68 -#define TM6000_U_OUT_MAXPS_HIGH5 0x69 -#define TM6000_U_OUT_MAXPS_LOW6 0x6A -#define TM6000_U_OUT_MAXPS_HIGH6 0x6B -#define TM6000_U_OUT_MAXPS_LOW7 0x6C -#define TM6000_U_OUT_MAXPS_HIGH7 0x6D -#define TM6000_U_OUT_MAXPS_LOW8 0x6E -#define TM6000_U_OUT_MAXPS_HIGH8 0x6F -#define TM6000_U_OUT_MAXPS_LOW9 0x70 -#define TM6000_U_OUT_MAXPS_HIGH9 0x71 -#define TM6000_U_OUT_MAXPS_LOW10 0x72 -#define TM6000_U_OUT_MAXPS_HIGH10 0x73 -#define TM6000_U_OUT_MAXPS_LOW11 0x74 -#define TM6000_U_OUT_MAXPS_HIGH11 0x75 -#define TM6000_U_OUT_MAXPS_LOW12 0x76 -#define TM6000_U_OUT_MAXPS_HIGH12 0x77 -#define TM6000_U_OUT_MAXPS_LOW13 0x78 -#define TM6000_U_OUT_MAXPS_HIGH13 0x79 -#define TM6000_U_OUT_MAXPS_LOW14 0x7A -#define TM6000_U_OUT_MAXPS_HIGH14 0x7B -#define TM6000_U_OUT_MAXPS_LOW15 0x7C -#define TM6000_U_OUT_MAXPS_HIGH15 0x7D -#define TM6000_U_FIFO0 0x80 -#define TM6000_U_FIFO1 0x81 -#define TM6000_U_FIFO2 0x82 -#define TM6000_U_FIFO3 0x83 -#define TM6000_U_FIFO4 0x84 -#define TM6000_U_FIFO5 0x85 -#define TM6000_U_FIFO6 0x86 -#define TM6000_U_FIFO7 0x87 -#define TM6000_U_FIFO8 0x88 -#define TM6000_U_FIFO9 0x89 -#define TM6000_U_FIFO10 0x8A -#define TM6000_U_FIFO11 0x8B -#define TM6000_U_FIFO12 0x8C -#define TM6000_U_FIFO13 0x8D -#define TM6000_U_FIFO14 0x8E -#define TM6000_U_FIFO15 0x8F -#define TM6000_U_CFG_FIFO0 0x90 -#define TM6000_U_CFG_FIFO1 0x91 -#define TM6000_U_CFG_FIFO2 0x92 -#define TM6000_U_CFG_FIFO3 0x93 -#define TM6000_U_CFG_FIFO4 0x94 -#define TM6000_U_CFG_FIFO5 0x95 -#define TM6000_U_CFG_FIFO6 0x96 -#define TM6000_U_CFG_FIFO7 0x97 -#define TM6000_U_CFG_FIFO8 0x98 -#define TM6000_U_CFG_FIFO9 0x99 -#define TM6000_U_CFG_FIFO10 0x9A -#define TM6000_U_CFG_FIFO11 0x9B -#define TM6000_U_CFG_FIFO12 0x9C -#define TM6000_U_CFG_FIFO13 0x9D -#define TM6000_U_CFG_FIFO14 0x9E -#define TM6000_U_CFG_FIFO15 0x9F -#define TM6000_U_CTL_FIFO0 0xA0 -#define TM6000_U_CTL_FIFO1 0xA1 -#define TM6000_U_CTL_FIFO2 0xA2 -#define TM6000_U_CTL_FIFO3 0xA3 -#define TM6000_U_CTL_FIFO4 0xA4 -#define TM6000_U_CTL_FIFO5 0xA5 -#define TM6000_U_CTL_FIFO6 0xA6 -#define TM6000_U_CTL_FIFO7 0xA7 -#define TM6000_U_CTL_FIFO8 0xA8 -#define TM6000_U_CTL_FIFO9 0xA9 -#define TM6000_U_CTL_FIFO10 0xAA -#define TM6000_U_CTL_FIFO11 0xAB -#define TM6000_U_CTL_FIFO12 0xAC -#define TM6000_U_CTL_FIFO13 0xAD -#define TM6000_U_CTL_FIFO14 0xAE -#define TM6000_U_CTL_FIFO15 0xAF -#define TM6000_U_BC_LOW_FIFO0 0xB0 -#define TM6000_U_BC_LOW_FIFO1 0xB1 -#define TM6000_U_BC_LOW_FIFO2 0xB2 -#define TM6000_U_BC_LOW_FIFO3 0xB3 -#define TM6000_U_BC_LOW_FIFO4 0xB4 -#define TM6000_U_BC_LOW_FIFO5 0xB5 -#define TM6000_U_BC_LOW_FIFO6 0xB6 -#define TM6000_U_BC_LOW_FIFO7 0xB7 -#define TM6000_U_BC_LOW_FIFO8 0xB8 -#define TM6000_U_BC_LOW_FIFO9 0xB9 -#define TM6000_U_BC_LOW_FIFO10 0xBA -#define TM6000_U_BC_LOW_FIFO11 0xBB -#define TM6000_U_BC_LOW_FIFO12 0xBC -#define TM6000_U_BC_LOW_FIFO13 0xBD -#define TM6000_U_BC_LOW_FIFO14 0xBE -#define TM6000_U_BC_LOW_FIFO15 0xBF -#define TM6000_U_DATA_FIFO0 0xC0 -#define TM6000_U_DATA_FIFO1 0xC4 -#define TM6000_U_DATA_FIFO2 0xC8 -#define TM6000_U_DATA_FIFO3 0xCC -#define TM6000_U_DATA_FIFO4 0xD0 -#define TM6000_U_DATA_FIFO5 0xD4 -#define TM6000_U_DATA_FIFO6 0xD8 -#define TM6000_U_DATA_FIFO7 0xDC -#define TM6000_U_DATA_FIFO8 0xE0 -#define TM6000_U_DATA_FIFO9 0xE4 -#define TM6000_U_DATA_FIFO10 0xE8 -#define TM6000_U_DATA_FIFO11 0xEC -#define TM6000_U_DATA_FIFO12 0xF0 -#define TM6000_U_DATA_FIFO13 0xF4 -#define TM6000_U_DATA_FIFO14 0xF8 -#define TM6000_U_DATA_FIFO15 0xFC +#define TM6010_REQ05_R00_MAIN_CTRL 0x00 +#define TM6010_REQ05_R01_DEVADDR 0x01 +#define TM6010_REQ05_R02_TEST 0x02 +#define TM6010_REQ05_R04_SOFN0 0x04 +#define TM6010_REQ05_R05_SOFN1 0x05 +#define TM6010_REQ05_R06_SOFTM0 0x06 +#define TM6010_REQ05_R07_SOFTM1 0x07 +#define TM6010_REQ05_R08_PHY_TEST 0x08 +#define TM6010_REQ05_R09_VCTL 0x09 +#define TM6010_REQ05_R0A_VSTA 0x0A +#define TM6010_REQ05_R0B_CX_CFG 0x0B +#define TM6010_REQ05_R0C_ENDP0_REG0 0x0C +#define TM6010_REQ05_R10_GMASK 0x10 +#define TM6010_REQ05_R11_IMASK0 0x11 +#define TM6010_REQ05_R12_IMASK1 0x12 +#define TM6010_REQ05_R13_IMASK2 0x13 +#define TM6010_REQ05_R14_IMASK3 0x14 +#define TM6010_REQ05_R15_IMASK4 0x15 +#define TM6010_REQ05_R16_IMASK5 0x16 +#define TM6010_REQ05_R17_IMASK6 0x17 +#define TM6010_REQ05_R18_IMASK7 0x18 +#define TM6010_REQ05_R19_ZEROP0 0x19 +#define TM6010_REQ05_R1A_ZEROP1 0x1A +#define TM6010_REQ05_R1C_FIFO_EMP0 0x1C +#define TM6010_REQ05_R1D_FIFO_EMP1 0x1D +#define TM6010_REQ05_R20_IRQ_GROUP 0x20 +#define TM6010_REQ05_R21_IRQ_SOURCE0 0x21 +#define TM6010_REQ05_R22_IRQ_SOURCE1 0x22 +#define TM6010_REQ05_R23_IRQ_SOURCE2 0x23 +#define TM6010_REQ05_R24_IRQ_SOURCE3 0x24 +#define TM6010_REQ05_R25_IRQ_SOURCE4 0x25 +#define TM6010_REQ05_R26_IRQ_SOURCE5 0x26 +#define TM6010_REQ05_R27_IRQ_SOURCE6 0x27 +#define TM6010_REQ05_R28_IRQ_SOURCE7 0x28 +#define TM6010_REQ05_R29_SEQ_ERR0 0x29 +#define TM6010_REQ05_R2A_SEQ_ERR1 0x2A +#define TM6010_REQ05_R2B_SEQ_ABORT0 0x2B +#define TM6010_REQ05_R2C_SEQ_ABORT1 0x2C +#define TM6010_REQ05_R2D_TX_ZERO0 0x2D +#define TM6010_REQ05_R2E_TX_ZERO1 0x2E +#define TM6010_REQ05_R2F_IDLE_CNT 0x2F +#define TM6010_REQ05_R30_FNO_P1 0x30 +#define TM6010_REQ05_R31_FNO_P2 0x31 +#define TM6010_REQ05_R32_FNO_P3 0x32 +#define TM6010_REQ05_R33_FNO_P4 0x33 +#define TM6010_REQ05_R34_FNO_P5 0x34 +#define TM6010_REQ05_R35_FNO_P6 0x35 +#define TM6010_REQ05_R36_FNO_P7 0x36 +#define TM6010_REQ05_R37_FNO_P8 0x37 +#define TM6010_REQ05_R38_FNO_P9 0x38 +#define TM6010_REQ05_R30_FNO_P10 0x39 +#define TM6010_REQ05_R30_FNO_P11 0x3A +#define TM6010_REQ05_R30_FNO_P12 0x3B +#define TM6010_REQ05_R30_FNO_P13 0x3C +#define TM6010_REQ05_R30_FNO_P14 0x3D +#define TM6010_REQ05_R30_FNO_P15 0x3E +#define TM6010_REQ05_R40_IN_MAXPS_LOW1 0x40 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH1 0x41 +#define TM6010_REQ05_R42_IN_MAXPS_LOW2 0x42 +#define TM6010_REQ05_R43_IN_MAXPS_HIGH2 0x43 +#define TM6010_REQ05_R44_IN_MAXPS_LOW3 0x44 +#define TM6010_REQ05_R45_IN_MAXPS_HIGH3 0x45 +#define TM6010_REQ05_R46_IN_MAXPS_LOW4 0x46 +#define TM6010_REQ05_R47_IN_MAXPS_HIGH4 0x47 +#define TM6010_REQ05_R48_IN_MAXPS_LOW5 0x48 +#define TM6010_REQ05_R49_IN_MAXPS_HIGH5 0x49 +#define TM6010_REQ05_R4A_IN_MAXPS_LOW6 0x4A +#define TM6010_REQ05_R4B_IN_MAXPS_HIGH6 0x4B +#define TM6010_REQ05_R4C_IN_MAXPS_LOW7 0x4C +#define TM6010_REQ05_R4D_IN_MAXPS_HIGH7 0x4D +#define TM6010_REQ05_R4E_IN_MAXPS_LOW8 0x4E +#define TM6010_REQ05_R4F_IN_MAXPS_HIGH8 0x4F +#define TM6010_REQ05_R50_IN_MAXPS_LOW9 0x50 +#define TM6010_REQ05_R51_IN_MAXPS_HIGH9 0x51 +#define TM6010_REQ05_R40_IN_MAXPS_LOW10 0x52 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH10 0x53 +#define TM6010_REQ05_R40_IN_MAXPS_LOW11 0x54 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH11 0x55 +#define TM6010_REQ05_R40_IN_MAXPS_LOW12 0x56 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH12 0x57 +#define TM6010_REQ05_R40_IN_MAXPS_LOW13 0x58 +#define TM6010_REQ05_R41_IN_MAXPS_HIGH13 0x59 +#define TM6010_REQ05_R40_IN_MAXPS_LOW14 0x5A +#define TM6010_REQ05_R41_IN_MAXPS_HIGH14 0x5B +#define TM6010_REQ05_R40_IN_MAXPS_LOW15 0x5C +#define TM6010_REQ05_R41_IN_MAXPS_HIGH15 0x5D +#define TM6010_REQ05_R60_OUT_MAXPS_LOW1 0x60 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH1 0x61 +#define TM6010_REQ05_R62_OUT_MAXPS_LOW2 0x62 +#define TM6010_REQ05_R63_OUT_MAXPS_HIGH2 0x63 +#define TM6010_REQ05_R64_OUT_MAXPS_LOW3 0x64 +#define TM6010_REQ05_R65_OUT_MAXPS_HIGH3 0x65 +#define TM6010_REQ05_R66_OUT_MAXPS_LOW4 0x66 +#define TM6010_REQ05_R67_OUT_MAXPS_HIGH4 0x67 +#define TM6010_REQ05_R68_OUT_MAXPS_LOW5 0x68 +#define TM6010_REQ05_R69_OUT_MAXPS_HIGH5 0x69 +#define TM6010_REQ05_R6A_OUT_MAXPS_LOW6 0x6A +#define TM6010_REQ05_R6B_OUT_MAXPS_HIGH6 0x6B +#define TM6010_REQ05_R6C_OUT_MAXPS_LOW7 0x6C +#define TM6010_REQ05_R6D_OUT_MAXPS_HIGH7 0x6D +#define TM6010_REQ05_R6E_OUT_MAXPS_LOW8 0x6E +#define TM6010_REQ05_R6F_OUT_MAXPS_HIGH8 0x6F +#define TM6010_REQ05_R70_OUT_MAXPS_LOW9 0x70 +#define TM6010_REQ05_R71_OUT_MAXPS_HIGH9 0x71 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW10 0x72 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH10 0x73 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW11 0x74 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH11 0x75 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW12 0x76 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH12 0x77 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW13 0x78 +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH13 0x79 +#define TM6010_REQ05_R60_OUT_MAXPS_LOW14 0x7A +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH14 0x7B +#define TM6010_REQ05_R60_OUT_MAXPS_LOW15 0x7C +#define TM6010_REQ05_R61_OUT_MAXPS_HIGH15 0x7D +#define TM6010_REQ05_R80_FIFO0 0x80 +#define TM6010_REQ05_R81_FIFO1 0x81 +#define TM6010_REQ05_R82_FIFO2 0x82 +#define TM6010_REQ05_R83_FIFO3 0x83 +#define TM6010_REQ05_R84_FIFO4 0x84 +#define TM6010_REQ05_R85_FIFO5 0x85 +#define TM6010_REQ05_R86_FIFO6 0x86 +#define TM6010_REQ05_R87_FIFO7 0x87 +#define TM6010_REQ05_R88_FIFO8 0x88 +#define TM6010_REQ05_R89_FIFO9 0x89 +#define TM6010_REQ05_R81_FIFO10 0x8A +#define TM6010_REQ05_R81_FIFO11 0x8B +#define TM6010_REQ05_R81_FIFO12 0x8C +#define TM6010_REQ05_R81_FIFO13 0x8D +#define TM6010_REQ05_R81_FIFO14 0x8E +#define TM6010_REQ05_R81_FIFO15 0x8F +#define TM6010_REQ05_R90_CFG_FIFO0 0x90 +#define TM6010_REQ05_R91_CFG_FIFO1 0x91 +#define TM6010_REQ05_R92_CFG_FIFO2 0x92 +#define TM6010_REQ05_R93_CFG_FIFO3 0x93 +#define TM6010_REQ05_R94_CFG_FIFO4 0x94 +#define TM6010_REQ05_R95_CFG_FIFO5 0x95 +#define TM6010_REQ05_R96_CFG_FIFO6 0x96 +#define TM6010_REQ05_R97_CFG_FIFO7 0x97 +#define TM6010_REQ05_R98_CFG_FIFO8 0x98 +#define TM6010_REQ05_R99_CFG_FIFO9 0x99 +#define TM6010_REQ05_R91_CFG_FIFO10 0x9A +#define TM6010_REQ05_R91_CFG_FIFO11 0x9B +#define TM6010_REQ05_R91_CFG_FIFO12 0x9C +#define TM6010_REQ05_R91_CFG_FIFO13 0x9D +#define TM6010_REQ05_R91_CFG_FIFO14 0x9E +#define TM6010_REQ05_R91_CFG_FIFO15 0x9F +#define TM6010_REQ05_RA0_CTL_FIFO0 0xA0 +#define TM6010_REQ05_RA1_CTL_FIFO1 0xA1 +#define TM6010_REQ05_RA2_CTL_FIFO2 0xA2 +#define TM6010_REQ05_RA3_CTL_FIFO3 0xA3 +#define TM6010_REQ05_RA4_CTL_FIFO4 0xA4 +#define TM6010_REQ05_RA5_CTL_FIFO5 0xA5 +#define TM6010_REQ05_RA6_CTL_FIFO6 0xA6 +#define TM6010_REQ05_RA7_CTL_FIFO7 0xA7 +#define TM6010_REQ05_RA8_CTL_FIFO8 0xA8 +#define TM6010_REQ05_RA9_CTL_FIFO9 0xA9 +#define TM6010_REQ05_RA1_CTL_FIFO10 0xAA +#define TM6010_REQ05_RA1_CTL_FIFO11 0xAB +#define TM6010_REQ05_RA1_CTL_FIFO12 0xAC +#define TM6010_REQ05_RA1_CTL_FIFO13 0xAD +#define TM6010_REQ05_RA1_CTL_FIFO14 0xAE +#define TM6010_REQ05_RA1_CTL_FIFO15 0xAF +#define TM6010_REQ05_RB0_BC_LOW_FIFO0 0xB0 +#define TM6010_REQ05_RB1_BC_LOW_FIFO1 0xB1 +#define TM6010_REQ05_RB2_BC_LOW_FIFO2 0xB2 +#define TM6010_REQ05_RB3_BC_LOW_FIFO3 0xB3 +#define TM6010_REQ05_RB4_BC_LOW_FIFO4 0xB4 +#define TM6010_REQ05_RB5_BC_LOW_FIFO5 0xB5 +#define TM6010_REQ05_RB6_BC_LOW_FIFO6 0xB6 +#define TM6010_REQ05_RB7_BC_LOW_FIFO7 0xB7 +#define TM6010_REQ05_RB8_BC_LOW_FIFO8 0xB8 +#define TM6010_REQ05_RB9_BC_LOW_FIFO9 0xB9 +#define TM6010_REQ05_RB1_BC_LOW_FIFO10 0xBA +#define TM6010_REQ05_RB1_BC_LOW_FIFO11 0xBB +#define TM6010_REQ05_RB1_BC_LOW_FIFO12 0xBC +#define TM6010_REQ05_RB1_BC_LOW_FIFO13 0xBD +#define TM6010_REQ05_RB1_BC_LOW_FIFO14 0xBE +#define TM6010_REQ05_RB1_BC_LOW_FIFO15 0xBF +#define TM6010_REQ05_RC0_DATA_FIFO0 0xC0 +#define TM6010_REQ05_RC4_DATA_FIFO1 0xC4 +#define TM6010_REQ05_RC8_DATA_FIFO2 0xC8 +#define TM6010_REQ05_RCC_DATA_FIFO3 0xCC +#define TM6010_REQ05_RD0_DATA_FIFO4 0xD0 +#define TM6010_REQ05_RD4_DATA_FIFO5 0xD4 +#define TM6010_REQ05_RD8_DATA_FIFO6 0xD8 +#define TM6010_REQ05_RDC_DATA_FIFO7 0xDC +#define TM6010_REQ05_RE0_DATA_FIFO8 0xE0 +#define TM6010_REQ05_RE4_DATA_FIFO9 0xE4 +#define TM6010_REQ05_RC4_DATA_FIFO10 0xE8 +#define TM6010_REQ05_RC4_DATA_FIFO11 0xEC +#define TM6010_REQ05_RC4_DATA_FIFO12 0xF0 +#define TM6010_REQ05_RC4_DATA_FIFO13 0xF4 +#define TM6010_REQ05_RC4_DATA_FIFO14 0xF8 +#define TM6010_REQ05_RC4_DATA_FIFO15 0xFC /* Define TM6000/TM6010 Audio decoder registers */ #define TM6010_REQ08_R00_A_VERSION 0x08, 0x00 -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 7/7] V4L/DVB: tm6000: replace occurences of req05 magic by a naming alias [not found] <cover.1268311636.git.mchehab@redhat.com> 2010-03-11 13:26 ` [PATCH 6/7] V4L/DVB: tm6000: add request to registers of the group 05 Mauro Carvalho Chehab 2010-03-11 13:26 ` [PATCH 5/7] V4L/DVB: tm6000: Replace naming convention for registers of req 05 group Mauro Carvalho Chehab @ 2010-03-11 13:26 ` Mauro Carvalho Chehab 2010-03-11 13:26 ` [PATCH 4/7] V4L/DVB: tm6000: Replace all magic values by a register alias Mauro Carvalho Chehab ` (3 subsequent siblings) 6 siblings, 0 replies; 7+ messages in thread From: Mauro Carvalho Chehab @ 2010-03-11 13:26 UTC (permalink / raw) To: linux-media Yet another naming replace magic thanks to perl scripts. This time, it is done with: cat tm6000-regs.h |perl -ne 'if (m/(TM6010_REQ[^\s]+)\s+0x([a-f0-9]+)\, 0x([a-f0-9]+)/) { $name="$1"; $req=$2; $val=$3; printf "s/REQ_${req}_SET_GET_USBREG, 0x[0]*$3,/$1,/\n" }' >a; for i in tm*.c; do sed -f a $i >b && mv b $i; done Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> diff --git a/drivers/staging/tm6000/tm6000-core.c b/drivers/staging/tm6000/tm6000-core.c index d501df2..1b588f8 100644 --- a/drivers/staging/tm6000/tm6000-core.c +++ b/drivers/staging/tm6000/tm6000-core.c @@ -341,7 +341,7 @@ struct reg_init tm6000_init_tab[] = { { TM6010_REQ07_RC1_TRESHOLD, 0xd0 }, { TM6010_REQ07_RC3_HSTART1, 0x88 }, { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */ - { REQ_05_SET_GET_USBREG, 0x18, 0x00 }, + { TM6010_REQ05_R18_IMASK7, 0x00 }, }; struct reg_init tm6010_init_tab[] = { @@ -414,7 +414,7 @@ struct reg_init tm6010_init_tab[] = { { TM6010_REQ07_RC3_HSTART1, 0x88 }, { TM6010_REQ07_R3F_RESET, 0x00 }, - { REQ_05_SET_GET_USBREG, 0x18, 0x00 }, + { TM6010_REQ05_R18_IMASK7, 0x00 }, { TM6010_REQ07_RD8_IR_LEADER1, 0xaa }, { TM6010_REQ07_RD8_IR_LEADER0, 0x30 }, -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/7] V4L/DVB: tm6000: Replace all magic values by a register alias [not found] <cover.1268311636.git.mchehab@redhat.com> ` (2 preceding siblings ...) 2010-03-11 13:26 ` [PATCH 7/7] V4L/DVB: tm6000: replace occurences of req05 magic by a naming alias Mauro Carvalho Chehab @ 2010-03-11 13:26 ` Mauro Carvalho Chehab 2010-03-11 13:26 ` [PATCH 3/7] V4L/DVB: tm6000: Add request at Req07/Req08 register definitions Mauro Carvalho Chehab ` (2 subsequent siblings) 6 siblings, 0 replies; 7+ messages in thread From: Mauro Carvalho Chehab @ 2010-03-11 13:26 UTC (permalink / raw) To: linux-media Instead of using magic pairs of req/reg, replace them by the defined values. This patch were generated by the following script: cat tm6000-regs.h |perl -ne 'if (m/(TM6010_REQ[^\s]+)\s+0x([a-f0-9]+)\, 0x([a-f0-9]+)/) { $name="$1"; $req=$2; $val=$3; printf "s/REQ_${req}_SET_GET_AVREG[_BIT]*, 0x[0]*$3,/$1,/\n" }' >a; for i in tm*.c; do sed -f a $i >b && mv b $i; done Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> diff --git a/drivers/staging/tm6000/tm6000-alsa.c b/drivers/staging/tm6000/tm6000-alsa.c index 7cc2ac7..bc89f9d 100644 --- a/drivers/staging/tm6000/tm6000-alsa.c +++ b/drivers/staging/tm6000/tm6000-alsa.c @@ -100,11 +100,11 @@ static int _tm6000_start_audio_dma(struct snd_tm6000_card *chip) int val; /* Enables audio */ - val = tm6000_get_reg(core, REQ_07_SET_GET_AVREG, 0xcc, 0x0); + val = tm6000_get_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0x0); val |= 0x20; - tm6000_set_reg(core, REQ_07_SET_GET_AVREG, 0xcc, val); + tm6000_set_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val); - tm6000_set_reg(core, REQ_08_SET_GET_AVREG_BIT, 0x01, 0x80); + tm6000_set_reg(core, TM6010_REQ08_R01_A_INIT, 0x80); return 0; } @@ -119,11 +119,11 @@ static int _tm6000_stop_audio_dma(struct snd_tm6000_card *chip) dprintk(1, "Stopping audio DMA\n"); /* Enables audio */ - val = tm6000_get_reg(core, REQ_07_SET_GET_AVREG, 0xcc, 0x0); + val = tm6000_get_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0x0); val &= ~0x20; - tm6000_set_reg(core, REQ_07_SET_GET_AVREG, 0xcc, val); + tm6000_set_reg(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val); - tm6000_set_reg(core, REQ_08_SET_GET_AVREG_BIT, 0x01, 0); + tm6000_set_reg(core, TM6010_REQ08_R01_A_INIT, 0); return 0; } diff --git a/drivers/staging/tm6000/tm6000-core.c b/drivers/staging/tm6000/tm6000-core.c index bf40aa8..d501df2 100644 --- a/drivers/staging/tm6000/tm6000-core.c +++ b/drivers/staging/tm6000/tm6000-core.c @@ -143,14 +143,14 @@ void tm6000_set_fourcc_format(struct tm6000_core *dev) { if (dev->dev_type == TM6010) { if (dev->fourcc == V4L2_PIX_FMT_UYVY) - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfc); + tm6000_set_reg (dev, TM6010_REQ07_RC1_TRESHOLD, 0xfc); else - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xfd); + tm6000_set_reg (dev, TM6010_REQ07_RC1_TRESHOLD, 0xfd); } else { if (dev->fourcc == V4L2_PIX_FMT_UYVY) - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0xd0); + tm6000_set_reg (dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0); else - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0xc1, 0x90); + tm6000_set_reg (dev, TM6010_REQ07_RC1_TRESHOLD, 0x90); } } @@ -160,40 +160,40 @@ int tm6000_init_analog_mode (struct tm6000_core *dev) int val; /* Enable video */ - val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0); + val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0); val |= 0x60; - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val); - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0xcf); + tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val); + tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0xcf); } else { /* Enables soft reset */ - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x01); + tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01); if (dev->scaler) { - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x20); + tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20); } else { /* Enable Hfilter and disable TS Drop err */ - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0x80); + tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80); } - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc3, 0x88); - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xda, 0x23); - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd1, 0xc0); - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd2, 0xd8); - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xd6, 0x06); - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xdf, 0x1f); + tm6000_set_reg(dev, TM6010_REQ07_RC3_HSTART1, 0x88); + tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23); + tm6000_set_reg(dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xc0); + tm6000_set_reg(dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xd8); + tm6000_set_reg(dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x06); + tm6000_set_reg(dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f); /* AP Software reset */ - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x08); - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xff, 0x00); + tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08); + tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00); tm6000_set_fourcc_format(dev); /* Disables soft reset */ - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0x3f, 0x00); + tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00); /* E3: Select input 0 - TV tuner */ - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xe3, 0x00); + tm6000_set_reg(dev, TM6010_REQ07_RE3_OUT_SEL1, 0x00); tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xeb, 0x60); /* This controls input */ @@ -225,38 +225,38 @@ int tm6000_init_digital_mode (struct tm6000_core *dev) u8 buf[2]; /* digital init */ - val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, 0); + val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0); val &= ~0x60; - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xcc, val); - val = tm6000_get_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, 0); + tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val); + val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0); val |= 0x40; - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xc0, val); - tm6000_set_reg(dev, REQ_07_SET_GET_AVREG, 0xfe, 0x28); - tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xfc); - tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xe6, 0xff); - tm6000_set_reg(dev, REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe); + tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val); + tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28); + tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc); + tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff); + tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe); tm6000_read_write_usb (dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2); printk (KERN_INFO "buf %#x %#x \n", buf[0], buf[1]); } else { - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x08); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00ff, 0x00); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x003f, 0x01); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00df, 0x08); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff); + tm6000_set_reg (dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08); + tm6000_set_reg (dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00); + tm6000_set_reg (dev, TM6010_REQ07_R3F_RESET, 0x01); + tm6000_set_reg (dev, TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x08); + tm6000_set_reg (dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c); + tm6000_set_reg (dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff); tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0xd8); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c0, 0x40); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c1, 0xd0); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00c3, 0x09); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00da, 0x37); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d1, 0xd8); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d2, 0xc0); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00d6, 0x60); + tm6000_set_reg (dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x40); + tm6000_set_reg (dev, TM6010_REQ07_RC1_TRESHOLD, 0xd0); + tm6000_set_reg (dev, TM6010_REQ07_RC3_HSTART1, 0x09); + tm6000_set_reg (dev, TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x37); + tm6000_set_reg (dev, TM6010_REQ07_RD1_ADDR_FOR_REQ1, 0xd8); + tm6000_set_reg (dev, TM6010_REQ07_RD2_ADDR_FOR_REQ2, 0xc0); + tm6000_set_reg (dev, TM6010_REQ07_RD6_ENDP_REQ1_REQ2, 0x60); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e2, 0x0c); - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00e8, 0xff); + tm6000_set_reg (dev, TM6010_REQ07_RE2_OUT_SEL2, 0x0c); + tm6000_set_reg (dev, TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0xff); tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x00eb, 0x08); msleep(50); @@ -279,153 +279,153 @@ struct reg_init { /* The meaning of those initializations are unknown */ struct reg_init tm6000_init_tab[] = { /* REG VALUE */ - { REQ_07_SET_GET_AVREG, 0xdf, 0x1f }, - { REQ_07_SET_GET_AVREG, 0xff, 0x08 }, - { REQ_07_SET_GET_AVREG, 0xff, 0x00 }, - { REQ_07_SET_GET_AVREG, 0xd5, 0x4f }, - { REQ_07_SET_GET_AVREG, 0xda, 0x23 }, - { REQ_07_SET_GET_AVREG, 0xdb, 0x08 }, - { REQ_07_SET_GET_AVREG, 0xe2, 0x00 }, - { REQ_07_SET_GET_AVREG, 0xe3, 0x10 }, - { REQ_07_SET_GET_AVREG, 0xe5, 0x00 }, - { REQ_07_SET_GET_AVREG, 0xe8, 0x00 }, + { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0x1f }, + { TM6010_REQ07_RFF_SOFT_RESET, 0x08 }, + { TM6010_REQ07_RFF_SOFT_RESET, 0x00 }, + { TM6010_REQ07_RD5_POWERSAVE, 0x4f }, + { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0x23 }, + { TM6010_REQ07_RD8_IR_WAKEUP_ADD, 0x08 }, + { TM6010_REQ07_RE2_OUT_SEL2, 0x00 }, + { TM6010_REQ07_RE3_OUT_SEL1, 0x10 }, + { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0x00 }, + { TM6010_REQ07_RE8_TYPESEL_MOS_I2S, 0x00 }, { REQ_07_SET_GET_AVREG, 0xeb, 0x64 }, /* 48000 bits/sample, external input */ { REQ_07_SET_GET_AVREG, 0xee, 0xc2 }, - { REQ_07_SET_GET_AVREG, 0x3f, 0x01 }, /* Start of soft reset */ - { REQ_07_SET_GET_AVREG, 0x00, 0x00 }, - { REQ_07_SET_GET_AVREG, 0x01, 0x07 }, - { REQ_07_SET_GET_AVREG, 0x02, 0x5f }, - { REQ_07_SET_GET_AVREG, 0x03, 0x00 }, - { REQ_07_SET_GET_AVREG, 0x05, 0x64 }, - { REQ_07_SET_GET_AVREG, 0x07, 0x01 }, - { REQ_07_SET_GET_AVREG, 0x08, 0x82 }, - { REQ_07_SET_GET_AVREG, 0x09, 0x36 }, - { REQ_07_SET_GET_AVREG, 0x0a, 0x50 }, - { REQ_07_SET_GET_AVREG, 0x0c, 0x6a }, - { REQ_07_SET_GET_AVREG, 0x11, 0xc9 }, - { REQ_07_SET_GET_AVREG, 0x12, 0x07 }, - { REQ_07_SET_GET_AVREG, 0x13, 0x3b }, - { REQ_07_SET_GET_AVREG, 0x14, 0x47 }, - { REQ_07_SET_GET_AVREG, 0x15, 0x6f }, - { REQ_07_SET_GET_AVREG, 0x17, 0xcd }, - { REQ_07_SET_GET_AVREG, 0x18, 0x1e }, - { REQ_07_SET_GET_AVREG, 0x19, 0x8b }, - { REQ_07_SET_GET_AVREG, 0x1a, 0xa2 }, - { REQ_07_SET_GET_AVREG, 0x1b, 0xe9 }, - { REQ_07_SET_GET_AVREG, 0x1c, 0x1c }, - { REQ_07_SET_GET_AVREG, 0x1d, 0xcc }, - { REQ_07_SET_GET_AVREG, 0x1e, 0xcc }, - { REQ_07_SET_GET_AVREG, 0x1f, 0xcd }, - { REQ_07_SET_GET_AVREG, 0x20, 0x3c }, - { REQ_07_SET_GET_AVREG, 0x21, 0x3c }, - { REQ_07_SET_GET_AVREG, 0x2d, 0x48 }, - { REQ_07_SET_GET_AVREG, 0x2e, 0x88 }, - { REQ_07_SET_GET_AVREG, 0x30, 0x22 }, - { REQ_07_SET_GET_AVREG, 0x31, 0x61 }, - { REQ_07_SET_GET_AVREG, 0x32, 0x74 }, - { REQ_07_SET_GET_AVREG, 0x33, 0x1c }, - { REQ_07_SET_GET_AVREG, 0x34, 0x74 }, - { REQ_07_SET_GET_AVREG, 0x35, 0x1c }, - { REQ_07_SET_GET_AVREG, 0x36, 0x7a }, - { REQ_07_SET_GET_AVREG, 0x37, 0x26 }, - { REQ_07_SET_GET_AVREG, 0x38, 0x40 }, - { REQ_07_SET_GET_AVREG, 0x39, 0x0a }, - { REQ_07_SET_GET_AVREG, 0x42, 0x55 }, - { REQ_07_SET_GET_AVREG, 0x51, 0x11 }, - { REQ_07_SET_GET_AVREG, 0x55, 0x01 }, - { REQ_07_SET_GET_AVREG, 0x57, 0x02 }, - { REQ_07_SET_GET_AVREG, 0x58, 0x35 }, - { REQ_07_SET_GET_AVREG, 0x59, 0xa0 }, - { REQ_07_SET_GET_AVREG, 0x80, 0x15 }, - { REQ_07_SET_GET_AVREG, 0x82, 0x42 }, - { REQ_07_SET_GET_AVREG, 0xc1, 0xd0 }, - { REQ_07_SET_GET_AVREG, 0xc3, 0x88 }, - { REQ_07_SET_GET_AVREG, 0x3f, 0x00 }, /* End of the soft reset */ + { TM6010_REQ07_R3F_RESET, 0x01 }, /* Start of soft reset */ + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 }, + { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 }, + { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 }, + { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 }, + { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 }, + { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a }, + { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 }, + { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 }, + { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b }, + { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 }, + { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f }, + { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c }, + { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c }, + { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, + { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c }, + { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a }, + { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 }, + { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 }, + { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a }, + { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 }, + { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 }, + { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 }, + { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 }, + { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 }, + { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 }, + { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, + { TM6010_REQ07_RC1_TRESHOLD, 0xd0 }, + { TM6010_REQ07_RC3_HSTART1, 0x88 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, /* End of the soft reset */ { REQ_05_SET_GET_USBREG, 0x18, 0x00 }, }; struct reg_init tm6010_init_tab[] = { - { REQ_07_SET_GET_AVREG, 0xc0, 0x00 }, - { REQ_07_SET_GET_AVREG, 0xc4, 0xa0 }, - { REQ_07_SET_GET_AVREG, 0xc6, 0x40 }, - { REQ_07_SET_GET_AVREG, 0xca, 0x31 }, - { REQ_07_SET_GET_AVREG, 0xcc, 0xe1 }, - { REQ_07_SET_GET_AVREG, 0xe0, 0x03 }, - { REQ_07_SET_GET_AVREG, 0xfe, 0x7f }, + { TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x00 }, + { TM6010_REQ07_RC4_HSTART0, 0xa0 }, + { TM6010_REQ07_RC6_HEND0, 0x40 }, + { TM6010_REQ07_RCA_VEND0, 0x31 }, + { TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0xe1 }, + { TM6010_REQ07_RE0_DVIDEO_SOURCE, 0x03 }, + { TM6010_REQ07_RFE_POWER_DOWN, 0x7f }, - { REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0 }, - { REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4 }, - { REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8 }, - { REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00 }, - { REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2 }, - { REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0 }, - { REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2 }, - { REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60 }, - { REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc }, + { TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0 }, + { TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4 }, + { TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8 }, + { TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00 }, + { TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2 }, + { TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 }, + { TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 }, + { TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 }, + { TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc }, - { REQ_07_SET_GET_AVREG, 0x3f, 0x01 }, - { REQ_07_SET_GET_AVREG, 0x00, 0x00 }, - { REQ_07_SET_GET_AVREG, 0x01, 0x07 }, - { REQ_07_SET_GET_AVREG, 0x02, 0x5f }, - { REQ_07_SET_GET_AVREG, 0x03, 0x00 }, - { REQ_07_SET_GET_AVREG, 0x05, 0x64 }, - { REQ_07_SET_GET_AVREG, 0x07, 0x01 }, - { REQ_07_SET_GET_AVREG, 0x08, 0x82 }, - { REQ_07_SET_GET_AVREG, 0x09, 0x36 }, - { REQ_07_SET_GET_AVREG, 0x0a, 0x50 }, - { REQ_07_SET_GET_AVREG, 0x0c, 0x6a }, - { REQ_07_SET_GET_AVREG, 0x11, 0xc9 }, - { REQ_07_SET_GET_AVREG, 0x12, 0x07 }, - { REQ_07_SET_GET_AVREG, 0x13, 0x3b }, - { REQ_07_SET_GET_AVREG, 0x14, 0x47 }, - { REQ_07_SET_GET_AVREG, 0x15, 0x6f }, - { REQ_07_SET_GET_AVREG, 0x17, 0xcd }, - { REQ_07_SET_GET_AVREG, 0x18, 0x1e }, - { REQ_07_SET_GET_AVREG, 0x19, 0x8b }, - { REQ_07_SET_GET_AVREG, 0x1a, 0xa2 }, - { REQ_07_SET_GET_AVREG, 0x1b, 0xe9 }, - { REQ_07_SET_GET_AVREG, 0x1c, 0x1c }, - { REQ_07_SET_GET_AVREG, 0x1d, 0xcc }, - { REQ_07_SET_GET_AVREG, 0x1e, 0xcc }, - { REQ_07_SET_GET_AVREG, 0x1f, 0xcd }, - { REQ_07_SET_GET_AVREG, 0x20, 0x3c }, - { REQ_07_SET_GET_AVREG, 0x21, 0x3c }, - { REQ_07_SET_GET_AVREG, 0x2d, 0x48 }, - { REQ_07_SET_GET_AVREG, 0x2e, 0x88 }, - { REQ_07_SET_GET_AVREG, 0x30, 0x22 }, - { REQ_07_SET_GET_AVREG, 0x31, 0x61 }, - { REQ_07_SET_GET_AVREG, 0x32, 0x74 }, - { REQ_07_SET_GET_AVREG, 0x33, 0x1c }, - { REQ_07_SET_GET_AVREG, 0x34, 0x74 }, - { REQ_07_SET_GET_AVREG, 0x35, 0x1c }, - { REQ_07_SET_GET_AVREG, 0x36, 0x7a }, - { REQ_07_SET_GET_AVREG, 0x37, 0x26 }, - { REQ_07_SET_GET_AVREG, 0x38, 0x40 }, - { REQ_07_SET_GET_AVREG, 0x39, 0x0a }, - { REQ_07_SET_GET_AVREG, 0x42, 0x55 }, - { REQ_07_SET_GET_AVREG, 0x51, 0x11 }, - { REQ_07_SET_GET_AVREG, 0x55, 0x01 }, - { REQ_07_SET_GET_AVREG, 0x57, 0x02 }, - { REQ_07_SET_GET_AVREG, 0x58, 0x35 }, - { REQ_07_SET_GET_AVREG, 0x59, 0xa0 }, - { REQ_07_SET_GET_AVREG, 0x80, 0x15 }, - { REQ_07_SET_GET_AVREG, 0x82, 0x42 }, - { REQ_07_SET_GET_AVREG, 0xc1, 0xd0 }, - { REQ_07_SET_GET_AVREG, 0xc3, 0x88 }, - { REQ_07_SET_GET_AVREG, 0x3f, 0x00 }, + { TM6010_REQ07_R3F_RESET, 0x01 }, + { TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00 }, + { TM6010_REQ07_R01_VIDEO_CONTROL1, 0x07 }, + { TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f }, + { TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00 }, + { TM6010_REQ07_R05_NOISE_THRESHOLD, 0x64 }, + { TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01 }, + { TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0x82 }, + { TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0x36 }, + { TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0x50 }, + { TM6010_REQ07_R0C_CHROMA_AGC_CONTROL, 0x6a }, + { TM6010_REQ07_R11_AGC_PEAK_CONTROL, 0xc9 }, + { TM6010_REQ07_R12_AGC_GATE_STARTH, 0x07 }, + { TM6010_REQ07_R13_AGC_GATE_STARTL, 0x3b }, + { TM6010_REQ07_R14_AGC_GATE_WIDTH, 0x47 }, + { TM6010_REQ07_R15_AGC_BP_DELAY, 0x6f }, + { TM6010_REQ07_R17_HLOOP_MAXSTATE, 0xcd }, + { TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e }, + { TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b }, + { TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2 }, + { TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9 }, + { TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c }, + { TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc }, + { TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc }, + { TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd }, + { TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME, 0x3c }, + { TM6010_REQ07_R21_HSYNC_PHASE_OFFSET, 0x3c }, + { TM6010_REQ07_R2D_CHROMA_BURST_END, 0x48 }, + { TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88 }, + { TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22 }, + { TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61 }, + { TM6010_REQ07_R32_VSYNC_HLOCK_MIN, 0x74 }, + { TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c }, + { TM6010_REQ07_R34_VSYNC_AGC_MIN, 0x74 }, + { TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c }, + { TM6010_REQ07_R36_VSYNC_VBI_MIN, 0x7a }, + { TM6010_REQ07_R37_VSYNC_VBI_MAX, 0x26 }, + { TM6010_REQ07_R38_VSYNC_THRESHOLD, 0x40 }, + { TM6010_REQ07_R39_VSYNC_TIME_CONSTANT, 0x0a }, + { TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL, 0x55 }, + { TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21, 0x11 }, + { TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN, 0x01 }, + { TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN, 0x02 }, + { TM6010_REQ07_R58_VBI_CAPTION_DTO1, 0x35 }, + { TM6010_REQ07_R59_VBI_CAPTION_DTO0, 0xa0 }, + { TM6010_REQ07_R80_COMB_FILTER_TRESHOLD, 0x15 }, + { TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42 }, + { TM6010_REQ07_RC1_TRESHOLD, 0xd0 }, + { TM6010_REQ07_RC3_HSTART1, 0x88 }, + { TM6010_REQ07_R3F_RESET, 0x00 }, { REQ_05_SET_GET_USBREG, 0x18, 0x00 }, - { REQ_07_SET_GET_AVREG, 0xdc, 0xaa }, - { REQ_07_SET_GET_AVREG, 0xdd, 0x30 }, - { REQ_07_SET_GET_AVREG, 0xde, 0x20 }, - { REQ_07_SET_GET_AVREG, 0xdf, 0xd0 }, + { TM6010_REQ07_RD8_IR_LEADER1, 0xaa }, + { TM6010_REQ07_RD8_IR_LEADER0, 0x30 }, + { TM6010_REQ07_RD8_IR_PULSE_CNT1, 0x20 }, + { TM6010_REQ07_RD8_IR_PULSE_CNT0, 0xd0 }, { REQ_04_EN_DISABLE_MCU_INT, 0x02, 0x00 }, - { REQ_07_SET_GET_AVREG, 0xd8, 0x2f }, + { TM6010_REQ07_RD8_IR, 0x2f }, /* set remote wakeup key:any key wakeup */ - { REQ_07_SET_GET_AVREG, 0xe5, 0xfe }, - { REQ_07_SET_GET_AVREG, 0xda, 0xff }, + { TM6010_REQ07_RE5_REMOTE_WAKEUP, 0xfe }, + { TM6010_REQ07_RD8_IR_WAKEUP_SEL, 0xff }, }; int tm6000_init (struct tm6000_core *dev) diff --git a/drivers/staging/tm6000/tm6000-stds.c b/drivers/staging/tm6000/tm6000-stds.c index 1e142e5..b3564f6 100644 --- a/drivers/staging/tm6000/tm6000-stds.c +++ b/drivers/staging/tm6000/tm6000-stds.c @@ -44,290 +44,290 @@ static struct tm6000_std_tv_settings tv_stds[] = { { .id = V4L2_STD_PAL_M, .sif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, - {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe}, + {TM6010_REQ07_RFE_POWER_DOWN, 0xcb}, {0, 0, 0}, }, .nosif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, {0, 0, 0}, }, .common = { - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x04}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x00}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x83}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x0a}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xe0}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, - {REQ_07_SET_GET_AVREG, 0x30, 0x20}, - {REQ_07_SET_GET_AVREG, 0x31, 0x61}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_PAL_Nc, .sif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, - {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe}, + {TM6010_REQ07_RFE_POWER_DOWN, 0xcb}, {0, 0, 0}, }, .nosif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, {0, 0, 0}, }, .common = { - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x36}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x02}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x91}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x1f}, - {REQ_07_SET_GET_AVREG, 0x1b, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, - {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_PAL, .sif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, - {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe}, + {TM6010_REQ07_RFE_POWER_DOWN, 0xcb}, {0, 0, 0} }, .nosif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, {0, 0, 0}, }, .common = { - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x32}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x02}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x25}, - {REQ_07_SET_GET_AVREG, 0x19, 0xd5}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x63}, - {REQ_07_SET_GET_AVREG, 0x1b, 0x50}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, - {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_SECAM, .sif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, - {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe}, + {TM6010_REQ07_RFE_POWER_DOWN, 0xcb}, {0, 0, 0}, }, .nosif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, {0, 0, 0}, }, .common = { - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x38}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x02}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x24}, - {REQ_07_SET_GET_AVREG, 0x19, 0x92}, - {REQ_07_SET_GET_AVREG, 0x1a, 0xe8}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xed}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, - {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x18}, - {REQ_07_SET_GET_AVREG, 0x82, 0x42}, - {REQ_07_SET_GET_AVREG, 0x83, 0xFF}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_NTSC, .sif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x08}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x62}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfe}, - {REQ_07_SET_GET_AVREG, 0xfe, 0xcb}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe}, + {TM6010_REQ07_RFE_POWER_DOWN, 0xcb}, {0, 0, 0}, }, .nosif = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x60}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, {0, 0, 0}, }, .common = { - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x00}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0f}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x00}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x1a, 0xa2}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xe9}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, - {REQ_07_SET_GET_AVREG, 0x30, 0x22}, - {REQ_07_SET_GET_AVREG, 0x31, 0x61}, - {REQ_07_SET_GET_AVREG, 0x33, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x42}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdd}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, @@ -337,210 +337,210 @@ static struct tm6000_std_settings composite_stds[] = { { .id = V4L2_STD_PAL_M, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x04}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x00}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x83}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x0a}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xe0}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, - {REQ_07_SET_GET_AVREG, 0x30, 0x20}, - {REQ_07_SET_GET_AVREG, 0x31, 0x61}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_PAL_Nc, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x36}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x02}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x91}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x1f}, - {REQ_07_SET_GET_AVREG, 0x1b, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, - {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_PAL, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x32}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x02}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x25}, - {REQ_07_SET_GET_AVREG, 0x19, 0xd5}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x63}, - {REQ_07_SET_GET_AVREG, 0x1b, 0x50}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, - {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_SECAM, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x38}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x02}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x24}, - {REQ_07_SET_GET_AVREG, 0x19, 0x92}, - {REQ_07_SET_GET_AVREG, 0x1a, 0xe8}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xed}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, - {REQ_07_SET_GET_AVREG, 0x30, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x18}, - {REQ_07_SET_GET_AVREG, 0x82, 0x42}, - {REQ_07_SET_GET_AVREG, 0x83, 0xFF}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_NTSC, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xf4}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf3}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x0f}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf1}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe8}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8b}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe8}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x00}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0f}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x00}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x1a, 0xa2}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xe9}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, - {REQ_07_SET_GET_AVREG, 0x30, 0x22}, - {REQ_07_SET_GET_AVREG, 0x31, 0x61}, - {REQ_07_SET_GET_AVREG, 0x33, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x42}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdd}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, @@ -550,211 +550,211 @@ static struct tm6000_std_settings svideo_stds[] = { { .id = V4L2_STD_PAL_M, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe0}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8a}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x05}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x04}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x83}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x0a}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xe0}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, - {REQ_07_SET_GET_AVREG, 0x30, 0x22}, - {REQ_07_SET_GET_AVREG, 0x31, 0x61}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x05}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_PAL_Nc, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe0}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8a}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x37}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x04}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x91}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x1f}, - {REQ_07_SET_GET_AVREG, 0x1b, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, - {REQ_07_SET_GET_AVREG, 0x30, 0x22}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x37}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_PAL, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe0}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8a}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x33}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x04}, - {REQ_07_SET_GET_AVREG, 0x07, 0x00}, - {REQ_07_SET_GET_AVREG, 0x18, 0x25}, - {REQ_07_SET_GET_AVREG, 0x19, 0xd5}, - {REQ_07_SET_GET_AVREG, 0x1a, 0x63}, - {REQ_07_SET_GET_AVREG, 0x1b, 0x50}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, - {REQ_07_SET_GET_AVREG, 0x30, 0x2a}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x0c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x52}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x33}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x04}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x00}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdc}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_SECAM, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe0}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8a}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x39}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0e}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x03}, - {REQ_07_SET_GET_AVREG, 0x07, 0x01}, - {REQ_07_SET_GET_AVREG, 0x18, 0x24}, - {REQ_07_SET_GET_AVREG, 0x19, 0x92}, - {REQ_07_SET_GET_AVREG, 0x1a, 0xe8}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xed}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x8c}, - {REQ_07_SET_GET_AVREG, 0x30, 0x2a}, - {REQ_07_SET_GET_AVREG, 0x31, 0xc1}, - {REQ_07_SET_GET_AVREG, 0x33, 0x2c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x18}, - {REQ_07_SET_GET_AVREG, 0x82, 0x42}, - {REQ_07_SET_GET_AVREG, 0x83, 0xFF}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x01}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, { .id = V4L2_STD_NTSC, .common = { - {REQ_08_SET_GET_AVREG_BIT, 0xe2, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xe3, 0xfc}, - {REQ_08_SET_GET_AVREG_BIT, 0xe4, 0xf8}, - {REQ_08_SET_GET_AVREG_BIT, 0xe6, 0x00}, - {REQ_08_SET_GET_AVREG_BIT, 0xea, 0xf2}, - {REQ_08_SET_GET_AVREG_BIT, 0xeb, 0xf0}, - {REQ_08_SET_GET_AVREG_BIT, 0xec, 0xc2}, - {REQ_08_SET_GET_AVREG_BIT, 0xed, 0xe0}, - {REQ_08_SET_GET_AVREG_BIT, 0xf0, 0x68}, - {REQ_08_SET_GET_AVREG_BIT, 0xf1, 0xfc}, - {REQ_07_SET_GET_AVREG, 0xfe, 0x8a}, + {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0}, + {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc}, + {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8}, + {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00}, + {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2}, + {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0}, + {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2}, + {TM6010_REQ08_RED_GAIN_SEL, 0xe0}, + {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68}, + {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc}, + {TM6010_REQ07_RFE_POWER_DOWN, 0x8a}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x01}, - {REQ_07_SET_GET_AVREG, 0x00, 0x01}, - {REQ_07_SET_GET_AVREG, 0x01, 0x0f}, - {REQ_07_SET_GET_AVREG, 0x02, 0x5f}, - {REQ_07_SET_GET_AVREG, 0x03, 0x03}, - {REQ_07_SET_GET_AVREG, 0x07, 0x00}, - {REQ_07_SET_GET_AVREG, 0x17, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x18, 0x1e}, - {REQ_07_SET_GET_AVREG, 0x19, 0x8b}, - {REQ_07_SET_GET_AVREG, 0x1a, 0xa2}, - {REQ_07_SET_GET_AVREG, 0x1b, 0xe9}, - {REQ_07_SET_GET_AVREG, 0x1c, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x1d, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1e, 0xcc}, - {REQ_07_SET_GET_AVREG, 0x1f, 0xcd}, - {REQ_07_SET_GET_AVREG, 0x2e, 0x88}, - {REQ_07_SET_GET_AVREG, 0x30, 0x22}, - {REQ_07_SET_GET_AVREG, 0x31, 0x61}, - {REQ_07_SET_GET_AVREG, 0x33, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x35, 0x1c}, - {REQ_07_SET_GET_AVREG, 0x82, 0x42}, - {REQ_07_SET_GET_AVREG, 0x83, 0x6F}, + {TM6010_REQ07_R3F_RESET, 0x01}, + {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x01}, + {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f}, + {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f}, + {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03}, + {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x00}, + {TM6010_REQ07_R17_HLOOP_MAXSTATE, 0x8b}, + {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e}, + {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b}, + {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2}, + {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9}, + {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c}, + {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc}, + {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc}, + {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd}, + {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88}, + {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22}, + {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61}, + {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c}, + {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c}, + {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42}, + {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F}, - {REQ_07_SET_GET_AVREG, 0x04, 0xdd}, - {REQ_07_SET_GET_AVREG, 0x0d, 0x07}, - {REQ_07_SET_GET_AVREG, 0x3f, 0x00}, + {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd}, + {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07}, + {TM6010_REQ07_R3F_RESET, 0x00}, {0, 0, 0}, }, }, diff --git a/drivers/staging/tm6000/tm6000-video.c b/drivers/staging/tm6000/tm6000-video.c index 66f922d..7ed2fd6 100644 --- a/drivers/staging/tm6000/tm6000-video.c +++ b/drivers/staging/tm6000/tm6000-video.c @@ -1184,16 +1184,16 @@ static int vidioc_g_ctrl (struct file *file, void *priv, /* FIXME: Probably, those won't work! Maybe we need shadow regs */ switch (ctrl->id) { case V4L2_CID_CONTRAST: - val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x08, 0); + val=tm6000_get_reg (dev, TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, 0); break; case V4L2_CID_BRIGHTNESS: - val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x09, 0); + val=tm6000_get_reg (dev, TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, 0); return 0; case V4L2_CID_SATURATION: - val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x0a, 0); + val=tm6000_get_reg (dev, TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, 0); return 0; case V4L2_CID_HUE: - val=tm6000_get_reg (dev, REQ_07_SET_GET_AVREG, 0x0b, 0); + val=tm6000_get_reg (dev, TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ, 0); return 0; default: return -EINVAL; @@ -1215,16 +1215,16 @@ static int vidioc_s_ctrl (struct file *file, void *priv, switch (ctrl->id) { case V4L2_CID_CONTRAST: - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x08, val); + tm6000_set_reg (dev, TM6010_REQ07_R08_LUMA_CONTRAST_ADJ, val); return 0; case V4L2_CID_BRIGHTNESS: - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x09, val); + tm6000_set_reg (dev, TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ, val); return 0; case V4L2_CID_SATURATION: - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0a, val); + tm6000_set_reg (dev, TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ, val); return 0; case V4L2_CID_HUE: - tm6000_set_reg (dev, REQ_07_SET_GET_AVREG, 0x0b, val); + tm6000_set_reg (dev, TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ, val); return 0; } return -EINVAL; -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/7] V4L/DVB: tm6000: Add request at Req07/Req08 register definitions [not found] <cover.1268311636.git.mchehab@redhat.com> ` (3 preceding siblings ...) 2010-03-11 13:26 ` [PATCH 4/7] V4L/DVB: tm6000: Replace all magic values by a register alias Mauro Carvalho Chehab @ 2010-03-11 13:26 ` Mauro Carvalho Chehab 2010-03-11 13:26 ` [PATCH 2/7] V4L/DVB: tm6000: Replace all Req 8 group of regs with another naming convention Mauro Carvalho Chehab 2010-03-11 13:26 ` [PATCH 1/7] V4L/DVB: tm6000: Replace all Req 7 " Mauro Carvalho Chehab 6 siblings, 0 replies; 7+ messages in thread From: Mauro Carvalho Chehab @ 2010-03-11 13:26 UTC (permalink / raw) To: linux-media Use a pair Req/Reg for all registers at req07 and req08 groups. This makes easier to replace them at the code with a script and helps to avoid using the wrong req with some register. This change were generated by this script: if (m/^(\#define TM6010_REQ)([0-9].)([^\s]+)(\s+)0x([A-F0-9].)/) { $name="$1$2$3"; $sp=$4; $req=$2; $val=$5; $val=~tr/A-F/a-f/; printf "$name%s0x%s, 0x%s\n", $sp, $req, $val; } else { print $_ } Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> diff --git a/drivers/staging/tm6000/tm6000-regs.h b/drivers/staging/tm6000/tm6000-regs.h index 00f7e04..631984a 100644 --- a/drivers/staging/tm6000/tm6000-regs.h +++ b/drivers/staging/tm6000/tm6000-regs.h @@ -98,186 +98,186 @@ enum { }; /* Define TM6000/TM6010 Video decoder registers */ -#define TM6010_REQ07_R00_VIDEO_CONTROL0 0x00 -#define TM6010_REQ07_R01_VIDEO_CONTROL1 0x01 -#define TM6010_REQ07_R02_VIDEO_CONTROL2 0x02 -#define TM6010_REQ07_R03_YC_SEP_CONTROL 0x03 -#define TM6010_REQ07_R04_LUMA_HAGC_CONTROL 0x04 -#define TM6010_REQ07_R05_NOISE_THRESHOLD 0x05 -#define TM6010_REQ07_R06_AGC_GATE_THRESHOLD 0x06 -#define TM6010_REQ07_R07_OUTPUT_CONTROL 0x07 -#define TM6010_REQ07_R08_LUMA_CONTRAST_ADJ 0x08 -#define TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ 0x09 -#define TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ 0x0A -#define TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ 0x0B -#define TM6010_REQ07_R0C_CHROMA_AGC_CONTROL 0x0C -#define TM6010_REQ07_R0D_CHROMA_KILL_LEVEL 0x0D -#define TM6010_REQ07_R0F_CHROMA_AUTO_POSITION 0x0F -#define TM6010_REQ07_R10_AGC_PEAK_NOMINAL 0x10 -#define TM6010_REQ07_R11_AGC_PEAK_CONTROL 0x11 -#define TM6010_REQ07_R12_AGC_GATE_STARTH 0x12 -#define TM6010_REQ07_R13_AGC_GATE_STARTL 0x13 -#define TM6010_REQ07_R14_AGC_GATE_WIDTH 0x14 -#define TM6010_REQ07_R15_AGC_BP_DELAY 0x15 -#define TM6010_REQ07_R16_LOCK_COUNT 0x16 -#define TM6010_REQ07_R17_HLOOP_MAXSTATE 0x17 -#define TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3 0x18 -#define TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2 0x19 -#define TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1 0x1A -#define TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0 0x1B -#define TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3 0x1C -#define TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2 0x1D -#define TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1 0x1E -#define TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0 0x1F -#define TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME 0x20 -#define TM6010_REQ07_R21_HSYNC_PHASE_OFFSET 0x21 -#define TM6010_REQ07_R22_HSYNC_PLL_START_TIME 0x22 -#define TM6010_REQ07_R23_HSYNC_PLL_END_TIME 0x23 -#define TM6010_REQ07_R24_HSYNC_TIP_START_TIME 0x24 -#define TM6010_REQ07_R25_HSYNC_TIP_END_TIME 0x25 -#define TM6010_REQ07_R26_HSYNC_RISING_EDGE_START 0x26 -#define TM6010_REQ07_R27_HSYNC_RISING_EDGE_END 0x27 -#define TM6010_REQ07_R28_BACKPORCH_START 0x28 -#define TM6010_REQ07_R29_BACKPORCH_END 0x29 -#define TM6010_REQ07_R2A_HSYNC_FILTER_START 0x2A -#define TM6010_REQ07_R2B_HSYNC_FILTER_END 0x2B -#define TM6010_REQ07_R2C_CHROMA_BURST_START 0x2C -#define TM6010_REQ07_R2D_CHROMA_BURST_END 0x2D -#define TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART 0x2E -#define TM6010_REQ07_R2F_ACTIVE_VIDEO_HWIDTH 0x2F -#define TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART 0x30 -#define TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT 0x31 -#define TM6010_REQ07_R32_VSYNC_HLOCK_MIN 0x32 -#define TM6010_REQ07_R33_VSYNC_HLOCK_MAX 0x33 -#define TM6010_REQ07_R34_VSYNC_AGC_MIN 0x34 -#define TM6010_REQ07_R35_VSYNC_AGC_MAX 0x35 -#define TM6010_REQ07_R36_VSYNC_VBI_MIN 0x36 -#define TM6010_REQ07_R37_VSYNC_VBI_MAX 0x37 -#define TM6010_REQ07_R38_VSYNC_THRESHOLD 0x38 -#define TM6010_REQ07_R39_VSYNC_TIME_CONSTANT 0x39 -#define TM6010_REQ07_R3A_STATUS1 0x3A -#define TM6010_REQ07_R3B_STATUS2 0x3B -#define TM6010_REQ07_R3C_STATUS3 0x3C -#define TM6010_REQ07_R3F_RESET 0x3F -#define TM6010_REQ07_R40_TELETEXT_VBI_CODE0 0x40 -#define TM6010_REQ07_R41_TELETEXT_VBI_CODE1 0x41 -#define TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL 0x42 -#define TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7 0x43 -#define TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8 0x44 -#define TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9 0x45 -#define TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10 0x46 -#define TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11 0x47 -#define TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12 0x48 -#define TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13 0x49 -#define TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14 0x4A -#define TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15 0x4B -#define TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16 0x4C -#define TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17 0x4D -#define TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18 0x4E -#define TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19 0x4F -#define TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20 0x50 -#define TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21 0x51 -#define TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22 0x52 -#define TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23 0x53 -#define TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES 0x54 -#define TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN 0x55 -#define TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN 0x56 -#define TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN 0x57 -#define TM6010_REQ07_R58_VBI_CAPTION_DTO1 0x58 -#define TM6010_REQ07_R59_VBI_CAPTION_DTO0 0x59 -#define TM6010_REQ07_R5A_VBI_TELETEXT_DTO1 0x5A -#define TM6010_REQ07_R5B_VBI_TELETEXT_DTO0 0x5B -#define TM6010_REQ07_R5C_VBI_WSS625_DTO1 0x5C -#define TM6010_REQ07_R5D_VBI_WSS625_DTO0 0x5D -#define TM6010_REQ07_R5E_VBI_CAPTION_FRAME_START 0x5E -#define TM6010_REQ07_R5F_VBI_WSS625_FRAME_START 0x5F -#define TM6010_REQ07_R60_TELETEXT_FRAME_START 0x60 -#define TM6010_REQ07_R61_VBI_CCDATA1 0x61 -#define TM6010_REQ07_R62_VBI_CCDATA2 0x62 -#define TM6010_REQ07_R63_VBI_WSS625_DATA1 0x63 -#define TM6010_REQ07_R64_VBI_WSS625_DATA2 0x64 -#define TM6010_REQ07_R65_VBI_DATA_STATUS 0x65 -#define TM6010_REQ07_R66_VBI_CAPTION_START 0x66 -#define TM6010_REQ07_R67_VBI_WSS625_START 0x67 -#define TM6010_REQ07_R68_VBI_TELETEXT_START 0x68 -#define TM6010_REQ07_R70_HSYNC_DTO_INC_STATUS3 0x70 -#define TM6010_REQ07_R71_HSYNC_DTO_INC_STATUS2 0x71 -#define TM6010_REQ07_R72_HSYNC_DTO_INC_STATUS1 0x72 -#define TM6010_REQ07_R73_HSYNC_DTO_INC_STATUS0 0x73 -#define TM6010_REQ07_R74_CHROMA_DTO_INC_STATUS3 0x74 -#define TM6010_REQ07_R75_CHROMA_DTO_INC_STATUS2 0x75 -#define TM6010_REQ07_R76_CHROMA_DTO_INC_STATUS1 0x76 -#define TM6010_REQ07_R77_CHROMA_DTO_INC_STATUS0 0x77 -#define TM6010_REQ07_R78_AGC_AGAIN_STATUS 0x78 -#define TM6010_REQ07_R79_AGC_DGAIN_STATUS 0x79 -#define TM6010_REQ07_R7A_CHROMA_MAG_STATUS 0x7A -#define TM6010_REQ07_R7B_CHROMA_GAIN_STATUS1 0x7B -#define TM6010_REQ07_R7C_CHROMA_GAIN_STATUS0 0x7C -#define TM6010_REQ07_R7D_CORDIC_FREQ_STATUS 0x7D -#define TM6010_REQ07_R7F_STATUS_NOISE 0x7F -#define TM6010_REQ07_R80_COMB_FILTER_TRESHOLD 0x80 -#define TM6010_REQ07_R82_COMB_FILTER_CONFIG 0x82 -#define TM6010_REQ07_R83_CHROMA_LOCK_CONFIG 0x83 -#define TM6010_REQ07_R84_NOISE_NTSC_C 0x84 -#define TM6010_REQ07_R85_NOISE_PAL_C 0x85 -#define TM6010_REQ07_R86_NOISE_PHASE_C 0x86 -#define TM6010_REQ07_R87_NOISE_PHASE_Y 0x87 -#define TM6010_REQ07_R8A_CHROMA_LOOPFILTER_STATE 0x8A -#define TM6010_REQ07_R8B_CHROMA_HRESAMPLER 0x8B -#define TM6010_REQ07_R8D_CPUMP_DELAY_ADJ 0x8D -#define TM6010_REQ07_R8E_CPUMP_ADJ 0x8E -#define TM6010_REQ07_R8F_CPUMP_DELAY 0x8F +#define TM6010_REQ07_R00_VIDEO_CONTROL0 0x07, 0x00 +#define TM6010_REQ07_R01_VIDEO_CONTROL1 0x07, 0x01 +#define TM6010_REQ07_R02_VIDEO_CONTROL2 0x07, 0x02 +#define TM6010_REQ07_R03_YC_SEP_CONTROL 0x07, 0x03 +#define TM6010_REQ07_R04_LUMA_HAGC_CONTROL 0x07, 0x04 +#define TM6010_REQ07_R05_NOISE_THRESHOLD 0x07, 0x05 +#define TM6010_REQ07_R06_AGC_GATE_THRESHOLD 0x07, 0x06 +#define TM6010_REQ07_R07_OUTPUT_CONTROL 0x07, 0x07 +#define TM6010_REQ07_R08_LUMA_CONTRAST_ADJ 0x07, 0x08 +#define TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ 0x07, 0x09 +#define TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ 0x07, 0x0a +#define TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ 0x07, 0x0b +#define TM6010_REQ07_R0C_CHROMA_AGC_CONTROL 0x07, 0x0c +#define TM6010_REQ07_R0D_CHROMA_KILL_LEVEL 0x07, 0x0d +#define TM6010_REQ07_R0F_CHROMA_AUTO_POSITION 0x07, 0x0f +#define TM6010_REQ07_R10_AGC_PEAK_NOMINAL 0x07, 0x10 +#define TM6010_REQ07_R11_AGC_PEAK_CONTROL 0x07, 0x11 +#define TM6010_REQ07_R12_AGC_GATE_STARTH 0x07, 0x12 +#define TM6010_REQ07_R13_AGC_GATE_STARTL 0x07, 0x13 +#define TM6010_REQ07_R14_AGC_GATE_WIDTH 0x07, 0x14 +#define TM6010_REQ07_R15_AGC_BP_DELAY 0x07, 0x15 +#define TM6010_REQ07_R16_LOCK_COUNT 0x07, 0x16 +#define TM6010_REQ07_R17_HLOOP_MAXSTATE 0x07, 0x17 +#define TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3 0x07, 0x18 +#define TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2 0x07, 0x19 +#define TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1 0x07, 0x1a +#define TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0 0x07, 0x1b +#define TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3 0x07, 0x1c +#define TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2 0x07, 0x1d +#define TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1 0x07, 0x1e +#define TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0 0x07, 0x1f +#define TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME 0x07, 0x20 +#define TM6010_REQ07_R21_HSYNC_PHASE_OFFSET 0x07, 0x21 +#define TM6010_REQ07_R22_HSYNC_PLL_START_TIME 0x07, 0x22 +#define TM6010_REQ07_R23_HSYNC_PLL_END_TIME 0x07, 0x23 +#define TM6010_REQ07_R24_HSYNC_TIP_START_TIME 0x07, 0x24 +#define TM6010_REQ07_R25_HSYNC_TIP_END_TIME 0x07, 0x25 +#define TM6010_REQ07_R26_HSYNC_RISING_EDGE_START 0x07, 0x26 +#define TM6010_REQ07_R27_HSYNC_RISING_EDGE_END 0x07, 0x27 +#define TM6010_REQ07_R28_BACKPORCH_START 0x07, 0x28 +#define TM6010_REQ07_R29_BACKPORCH_END 0x07, 0x29 +#define TM6010_REQ07_R2A_HSYNC_FILTER_START 0x07, 0x2a +#define TM6010_REQ07_R2B_HSYNC_FILTER_END 0x07, 0x2b +#define TM6010_REQ07_R2C_CHROMA_BURST_START 0x07, 0x2c +#define TM6010_REQ07_R2D_CHROMA_BURST_END 0x07, 0x2d +#define TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART 0x07, 0x2e +#define TM6010_REQ07_R2F_ACTIVE_VIDEO_HWIDTH 0x07, 0x2f +#define TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART 0x07, 0x30 +#define TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT 0x07, 0x31 +#define TM6010_REQ07_R32_VSYNC_HLOCK_MIN 0x07, 0x32 +#define TM6010_REQ07_R33_VSYNC_HLOCK_MAX 0x07, 0x33 +#define TM6010_REQ07_R34_VSYNC_AGC_MIN 0x07, 0x34 +#define TM6010_REQ07_R35_VSYNC_AGC_MAX 0x07, 0x35 +#define TM6010_REQ07_R36_VSYNC_VBI_MIN 0x07, 0x36 +#define TM6010_REQ07_R37_VSYNC_VBI_MAX 0x07, 0x37 +#define TM6010_REQ07_R38_VSYNC_THRESHOLD 0x07, 0x38 +#define TM6010_REQ07_R39_VSYNC_TIME_CONSTANT 0x07, 0x39 +#define TM6010_REQ07_R3A_STATUS1 0x07, 0x3a +#define TM6010_REQ07_R3B_STATUS2 0x07, 0x3b +#define TM6010_REQ07_R3C_STATUS3 0x07, 0x3c +#define TM6010_REQ07_R3F_RESET 0x07, 0x3f +#define TM6010_REQ07_R40_TELETEXT_VBI_CODE0 0x07, 0x40 +#define TM6010_REQ07_R41_TELETEXT_VBI_CODE1 0x07, 0x41 +#define TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL 0x07, 0x42 +#define TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7 0x07, 0x43 +#define TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8 0x07, 0x44 +#define TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9 0x07, 0x45 +#define TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10 0x07, 0x46 +#define TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11 0x07, 0x47 +#define TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12 0x07, 0x48 +#define TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13 0x07, 0x49 +#define TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14 0x07, 0x4a +#define TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15 0x07, 0x4b +#define TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16 0x07, 0x4c +#define TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17 0x07, 0x4d +#define TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18 0x07, 0x4e +#define TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19 0x07, 0x4f +#define TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20 0x07, 0x50 +#define TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21 0x07, 0x51 +#define TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22 0x07, 0x52 +#define TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23 0x07, 0x53 +#define TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES 0x07, 0x54 +#define TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN 0x07, 0x55 +#define TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN 0x07, 0x56 +#define TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN 0x07, 0x57 +#define TM6010_REQ07_R58_VBI_CAPTION_DTO1 0x07, 0x58 +#define TM6010_REQ07_R59_VBI_CAPTION_DTO0 0x07, 0x59 +#define TM6010_REQ07_R5A_VBI_TELETEXT_DTO1 0x07, 0x5a +#define TM6010_REQ07_R5B_VBI_TELETEXT_DTO0 0x07, 0x5b +#define TM6010_REQ07_R5C_VBI_WSS625_DTO1 0x07, 0x5c +#define TM6010_REQ07_R5D_VBI_WSS625_DTO0 0x07, 0x5d +#define TM6010_REQ07_R5E_VBI_CAPTION_FRAME_START 0x07, 0x5e +#define TM6010_REQ07_R5F_VBI_WSS625_FRAME_START 0x07, 0x5f +#define TM6010_REQ07_R60_TELETEXT_FRAME_START 0x07, 0x60 +#define TM6010_REQ07_R61_VBI_CCDATA1 0x07, 0x61 +#define TM6010_REQ07_R62_VBI_CCDATA2 0x07, 0x62 +#define TM6010_REQ07_R63_VBI_WSS625_DATA1 0x07, 0x63 +#define TM6010_REQ07_R64_VBI_WSS625_DATA2 0x07, 0x64 +#define TM6010_REQ07_R65_VBI_DATA_STATUS 0x07, 0x65 +#define TM6010_REQ07_R66_VBI_CAPTION_START 0x07, 0x66 +#define TM6010_REQ07_R67_VBI_WSS625_START 0x07, 0x67 +#define TM6010_REQ07_R68_VBI_TELETEXT_START 0x07, 0x68 +#define TM6010_REQ07_R70_HSYNC_DTO_INC_STATUS3 0x07, 0x70 +#define TM6010_REQ07_R71_HSYNC_DTO_INC_STATUS2 0x07, 0x71 +#define TM6010_REQ07_R72_HSYNC_DTO_INC_STATUS1 0x07, 0x72 +#define TM6010_REQ07_R73_HSYNC_DTO_INC_STATUS0 0x07, 0x73 +#define TM6010_REQ07_R74_CHROMA_DTO_INC_STATUS3 0x07, 0x74 +#define TM6010_REQ07_R75_CHROMA_DTO_INC_STATUS2 0x07, 0x75 +#define TM6010_REQ07_R76_CHROMA_DTO_INC_STATUS1 0x07, 0x76 +#define TM6010_REQ07_R77_CHROMA_DTO_INC_STATUS0 0x07, 0x77 +#define TM6010_REQ07_R78_AGC_AGAIN_STATUS 0x07, 0x78 +#define TM6010_REQ07_R79_AGC_DGAIN_STATUS 0x07, 0x79 +#define TM6010_REQ07_R7A_CHROMA_MAG_STATUS 0x07, 0x7a +#define TM6010_REQ07_R7B_CHROMA_GAIN_STATUS1 0x07, 0x7b +#define TM6010_REQ07_R7C_CHROMA_GAIN_STATUS0 0x07, 0x7c +#define TM6010_REQ07_R7D_CORDIC_FREQ_STATUS 0x07, 0x7d +#define TM6010_REQ07_R7F_STATUS_NOISE 0x07, 0x7f +#define TM6010_REQ07_R80_COMB_FILTER_TRESHOLD 0x07, 0x80 +#define TM6010_REQ07_R82_COMB_FILTER_CONFIG 0x07, 0x82 +#define TM6010_REQ07_R83_CHROMA_LOCK_CONFIG 0x07, 0x83 +#define TM6010_REQ07_R84_NOISE_NTSC_C 0x07, 0x84 +#define TM6010_REQ07_R85_NOISE_PAL_C 0x07, 0x85 +#define TM6010_REQ07_R86_NOISE_PHASE_C 0x07, 0x86 +#define TM6010_REQ07_R87_NOISE_PHASE_Y 0x07, 0x87 +#define TM6010_REQ07_R8A_CHROMA_LOOPFILTER_STATE 0x07, 0x8a +#define TM6010_REQ07_R8B_CHROMA_HRESAMPLER 0x07, 0x8b +#define TM6010_REQ07_R8D_CPUMP_DELAY_ADJ 0x07, 0x8d +#define TM6010_REQ07_R8E_CPUMP_ADJ 0x07, 0x8e +#define TM6010_REQ07_R8F_CPUMP_DELAY 0x07, 0x8f /* Define TM6000/TM6010 Miscellaneous registers */ -#define TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE 0xC0 -#define TM6010_REQ07_RC1_TRESHOLD 0xC1 -#define TM6010_REQ07_RC2_HSYNC_WIDTH 0xC2 -#define TM6010_REQ07_RC3_HSTART1 0xC3 -#define TM6010_REQ07_RC4_HSTART0 0xC4 -#define TM6010_REQ07_RC5_HEND1 0xC5 -#define TM6010_REQ07_RC6_HEND0 0xC6 -#define TM6010_REQ07_RC7_VSTART1 0xC7 -#define TM6010_REQ07_RC8_VSTART0 0xC8 -#define TM6010_REQ07_RC9_VEND1 0xC9 -#define TM6010_REQ07_RCA_VEND0 0xCA -#define TM6010_REQ07_RCB_DELAY 0xCB -#define TM6010_REQ07_RCC_ACTIVE_VIDEO_IF 0xCC -#define TM6010_REQ07_RD0_USB_PERIPHERY_CONTROL 0xD0 -#define TM6010_REQ07_RD1_ADDR_FOR_REQ1 0xD1 -#define TM6010_REQ07_RD2_ADDR_FOR_REQ2 0xD2 -#define TM6010_REQ07_RD3_ADDR_FOR_REQ3 0xD3 -#define TM6010_REQ07_RD4_ADDR_FOR_REQ4 0xD4 -#define TM6010_REQ07_RD5_POWERSAVE 0xD5 -#define TM6010_REQ07_RD6_ENDP_REQ1_REQ2 0xD6 -#define TM6010_REQ07_RD7_ENDP_REQ3_REQ4 0xD7 -#define TM6010_REQ07_RD8_IR 0xD8 -#define TM6010_REQ07_RD8_IR_BSIZE 0xD9 -#define TM6010_REQ07_RD8_IR_WAKEUP_SEL 0xDA -#define TM6010_REQ07_RD8_IR_WAKEUP_ADD 0xDB -#define TM6010_REQ07_RD8_IR_LEADER1 0xDC -#define TM6010_REQ07_RD8_IR_LEADER0 0xDD -#define TM6010_REQ07_RD8_IR_PULSE_CNT1 0xDE -#define TM6010_REQ07_RD8_IR_PULSE_CNT0 0xDF -#define TM6010_REQ07_RE0_DVIDEO_SOURCE 0xE0 -#define TM6010_REQ07_RE0_DVIDEO_SOURCE_IF 0xE1 -#define TM6010_REQ07_RE2_OUT_SEL2 0xE2 -#define TM6010_REQ07_RE3_OUT_SEL1 0xE3 -#define TM6010_REQ07_RE4_OUT_SEL0 0xE4 -#define TM6010_REQ07_RE5_REMOTE_WAKEUP 0xE5 -#define TM6010_REQ07_RE7_PUB_GPIO 0xE7 -#define TM6010_REQ07_RE8_TYPESEL_MOS_I2S 0xE8 -#define TM6010_REQ07_RE9_TYPESEL_MOS_TS 0xE9 -#define TM6010_REQ07_REA_TYPESEL_MOS_CCIR 0xEA -#define TM6010_REQ07_RF0_BIST_CRC_RESULT0 0xF0 -#define TM6010_REQ07_RF1_BIST_CRC_RESULT1 0xF1 -#define TM6010_REQ07_RF2_BIST_CRC_RESULT2 0xF2 -#define TM6010_REQ07_RF3_BIST_CRC_RESULT3 0xF3 -#define TM6010_REQ07_RF4_BIST_ERR_VST2 0xF4 -#define TM6010_REQ07_RF5_BIST_ERR_VST1 0xF5 -#define TM6010_REQ07_RF6_BIST_ERR_VST0 0xF6 -#define TM6010_REQ07_RF7_BIST 0xF7 -#define TM6010_REQ07_RFE_POWER_DOWN 0xFE -#define TM6010_REQ07_RFF_SOFT_RESET 0xFF +#define TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE 0x07, 0xc0 +#define TM6010_REQ07_RC1_TRESHOLD 0x07, 0xc1 +#define TM6010_REQ07_RC2_HSYNC_WIDTH 0x07, 0xc2 +#define TM6010_REQ07_RC3_HSTART1 0x07, 0xc3 +#define TM6010_REQ07_RC4_HSTART0 0x07, 0xc4 +#define TM6010_REQ07_RC5_HEND1 0x07, 0xc5 +#define TM6010_REQ07_RC6_HEND0 0x07, 0xc6 +#define TM6010_REQ07_RC7_VSTART1 0x07, 0xc7 +#define TM6010_REQ07_RC8_VSTART0 0x07, 0xc8 +#define TM6010_REQ07_RC9_VEND1 0x07, 0xc9 +#define TM6010_REQ07_RCA_VEND0 0x07, 0xca +#define TM6010_REQ07_RCB_DELAY 0x07, 0xcb +#define TM6010_REQ07_RCC_ACTIVE_VIDEO_IF 0x07, 0xcc +#define TM6010_REQ07_RD0_USB_PERIPHERY_CONTROL 0x07, 0xd0 +#define TM6010_REQ07_RD1_ADDR_FOR_REQ1 0x07, 0xd1 +#define TM6010_REQ07_RD2_ADDR_FOR_REQ2 0x07, 0xd2 +#define TM6010_REQ07_RD3_ADDR_FOR_REQ3 0x07, 0xd3 +#define TM6010_REQ07_RD4_ADDR_FOR_REQ4 0x07, 0xd4 +#define TM6010_REQ07_RD5_POWERSAVE 0x07, 0xd5 +#define TM6010_REQ07_RD6_ENDP_REQ1_REQ2 0x07, 0xd6 +#define TM6010_REQ07_RD7_ENDP_REQ3_REQ4 0x07, 0xd7 +#define TM6010_REQ07_RD8_IR 0x07, 0xd8 +#define TM6010_REQ07_RD8_IR_BSIZE 0x07, 0xd9 +#define TM6010_REQ07_RD8_IR_WAKEUP_SEL 0x07, 0xda +#define TM6010_REQ07_RD8_IR_WAKEUP_ADD 0x07, 0xdb +#define TM6010_REQ07_RD8_IR_LEADER1 0x07, 0xdc +#define TM6010_REQ07_RD8_IR_LEADER0 0x07, 0xdd +#define TM6010_REQ07_RD8_IR_PULSE_CNT1 0x07, 0xde +#define TM6010_REQ07_RD8_IR_PULSE_CNT0 0x07, 0xdf +#define TM6010_REQ07_RE0_DVIDEO_SOURCE 0x07, 0xe0 +#define TM6010_REQ07_RE0_DVIDEO_SOURCE_IF 0x07, 0xe1 +#define TM6010_REQ07_RE2_OUT_SEL2 0x07, 0xe2 +#define TM6010_REQ07_RE3_OUT_SEL1 0x07, 0xe3 +#define TM6010_REQ07_RE4_OUT_SEL0 0x07, 0xe4 +#define TM6010_REQ07_RE5_REMOTE_WAKEUP 0x07, 0xe5 +#define TM6010_REQ07_RE7_PUB_GPIO 0x07, 0xe7 +#define TM6010_REQ07_RE8_TYPESEL_MOS_I2S 0x07, 0xe8 +#define TM6010_REQ07_RE9_TYPESEL_MOS_TS 0x07, 0xe9 +#define TM6010_REQ07_REA_TYPESEL_MOS_CCIR 0x07, 0xea +#define TM6010_REQ07_RF0_BIST_CRC_RESULT0 0x07, 0xf0 +#define TM6010_REQ07_RF1_BIST_CRC_RESULT1 0x07, 0xf1 +#define TM6010_REQ07_RF2_BIST_CRC_RESULT2 0x07, 0xf2 +#define TM6010_REQ07_RF3_BIST_CRC_RESULT3 0x07, 0xf3 +#define TM6010_REQ07_RF4_BIST_ERR_VST2 0x07, 0xf4 +#define TM6010_REQ07_RF5_BIST_ERR_VST1 0x07, 0xf5 +#define TM6010_REQ07_RF6_BIST_ERR_VST0 0x07, 0xf6 +#define TM6010_REQ07_RF7_BIST 0x07, 0xf7 +#define TM6010_REQ07_RFE_POWER_DOWN 0x07, 0xfe +#define TM6010_REQ07_RFF_SOFT_RESET 0x07, 0xff /* Define TM6000/TM6010 USB registers */ #define TM6000_U_MAIN_CTRL 0x00 @@ -478,64 +478,64 @@ enum { #define TM6000_U_DATA_FIFO15 0xFC /* Define TM6000/TM6010 Audio decoder registers */ -#define TM6010_REQ08_R00_A_VERSION 0x00 -#define TM6010_REQ08_R01_A_INIT 0x01 -#define TM6010_REQ08_R02_A_FIX_GAIN_CTRL 0x02 -#define TM6010_REQ08_R03_A_AUTO_GAIN_CTRL 0x03 -#define TM6010_REQ08_R04_A_SIF_AMP_CTRL 0x04 -#define TM6010_REQ08_R05_A_STANDARD_MOD 0x05 -#define TM6010_REQ08_R06_A_SOUND_MOD 0x06 -#define TM6010_REQ08_R07_A_LEFT_VOL 0x07 -#define TM6010_REQ08_R08_A_RIGHT_VOL 0x08 -#define TM6010_REQ08_R09_A_MAIN_VOL 0x09 -#define TM6010_REQ08_R0A_A_I2S_MOD 0x0A -#define TM6010_REQ08_R0B_A_ASD_THRES1 0x0B -#define TM6010_REQ08_R0C_A_ASD_THRES2 0x0C -#define TM6010_REQ08_R0D_A_AMD_THRES 0x0D -#define TM6010_REQ08_R0E_A_MONO_THRES1 0x0E -#define TM6010_REQ08_R0F_A_MONO_THRES2 0x0F -#define TM6010_REQ08_R10_A_MUTE_THRES1 0x10 -#define TM6010_REQ08_R11_A_MUTE_THRES2 0x11 -#define TM6010_REQ08_R12_A_AGC_U 0x12 -#define TM6010_REQ08_R13_A_AGC_ERR_T 0x13 -#define TM6010_REQ08_R14_A_AGC_GAIN_INIT 0x14 -#define TM6010_REQ08_R15_A_AGC_STEP_THR 0x15 -#define TM6010_REQ08_R16_A_AGC_GAIN_MAX 0x16 -#define TM6010_REQ08_R17_A_AGC_GAIN_MIN 0x17 -#define TM6010_REQ08_R18_A_TR_CTRL 0x18 -#define TM6010_REQ08_R19_A_FH_2FH_GAIN 0x19 -#define TM6010_REQ08_R1A_A_NICAM_SER_MAX 0x1A -#define TM6010_REQ08_R1B_A_NICAM_SER_MIN 0x1B -#define TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT 0x1E -#define TM6010_REQ08_R1F_A_TEST_INTF_SEL 0x1F -#define TM6010_REQ08_R20_A_TEST_PIN_SEL 0x20 -#define TM6010_REQ08_R21_A_AGC_ERR 0x21 -#define TM6010_REQ08_R22_A_AGC_GAIN 0x22 -#define TM6010_REQ08_R23_A_NICAM_INFO 0x23 -#define TM6010_REQ08_R24_A_SER 0x24 -#define TM6010_REQ08_R25_A_C1_AMP 0x25 -#define TM6010_REQ08_R26_A_C2_AMP 0x26 -#define TM6010_REQ08_R27_A_NOISE_AMP 0x27 -#define TM6010_REQ08_R28_A_AUDIO_MODE_RES 0x28 +#define TM6010_REQ08_R00_A_VERSION 0x08, 0x00 +#define TM6010_REQ08_R01_A_INIT 0x08, 0x01 +#define TM6010_REQ08_R02_A_FIX_GAIN_CTRL 0x08, 0x02 +#define TM6010_REQ08_R03_A_AUTO_GAIN_CTRL 0x08, 0x03 +#define TM6010_REQ08_R04_A_SIF_AMP_CTRL 0x08, 0x04 +#define TM6010_REQ08_R05_A_STANDARD_MOD 0x08, 0x05 +#define TM6010_REQ08_R06_A_SOUND_MOD 0x08, 0x06 +#define TM6010_REQ08_R07_A_LEFT_VOL 0x08, 0x07 +#define TM6010_REQ08_R08_A_RIGHT_VOL 0x08, 0x08 +#define TM6010_REQ08_R09_A_MAIN_VOL 0x08, 0x09 +#define TM6010_REQ08_R0A_A_I2S_MOD 0x08, 0x0a +#define TM6010_REQ08_R0B_A_ASD_THRES1 0x08, 0x0b +#define TM6010_REQ08_R0C_A_ASD_THRES2 0x08, 0x0c +#define TM6010_REQ08_R0D_A_AMD_THRES 0x08, 0x0d +#define TM6010_REQ08_R0E_A_MONO_THRES1 0x08, 0x0e +#define TM6010_REQ08_R0F_A_MONO_THRES2 0x08, 0x0f +#define TM6010_REQ08_R10_A_MUTE_THRES1 0x08, 0x10 +#define TM6010_REQ08_R11_A_MUTE_THRES2 0x08, 0x11 +#define TM6010_REQ08_R12_A_AGC_U 0x08, 0x12 +#define TM6010_REQ08_R13_A_AGC_ERR_T 0x08, 0x13 +#define TM6010_REQ08_R14_A_AGC_GAIN_INIT 0x08, 0x14 +#define TM6010_REQ08_R15_A_AGC_STEP_THR 0x08, 0x15 +#define TM6010_REQ08_R16_A_AGC_GAIN_MAX 0x08, 0x16 +#define TM6010_REQ08_R17_A_AGC_GAIN_MIN 0x08, 0x17 +#define TM6010_REQ08_R18_A_TR_CTRL 0x08, 0x18 +#define TM6010_REQ08_R19_A_FH_2FH_GAIN 0x08, 0x19 +#define TM6010_REQ08_R1A_A_NICAM_SER_MAX 0x08, 0x1a +#define TM6010_REQ08_R1B_A_NICAM_SER_MIN 0x08, 0x1b +#define TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT 0x08, 0x1e +#define TM6010_REQ08_R1F_A_TEST_INTF_SEL 0x08, 0x1f +#define TM6010_REQ08_R20_A_TEST_PIN_SEL 0x08, 0x20 +#define TM6010_REQ08_R21_A_AGC_ERR 0x08, 0x21 +#define TM6010_REQ08_R22_A_AGC_GAIN 0x08, 0x22 +#define TM6010_REQ08_R23_A_NICAM_INFO 0x08, 0x23 +#define TM6010_REQ08_R24_A_SER 0x08, 0x24 +#define TM6010_REQ08_R25_A_C1_AMP 0x08, 0x25 +#define TM6010_REQ08_R26_A_C2_AMP 0x08, 0x26 +#define TM6010_REQ08_R27_A_NOISE_AMP 0x08, 0x27 +#define TM6010_REQ08_R28_A_AUDIO_MODE_RES 0x08, 0x28 /* Define TM6000/TM6010 Video ADC registers */ -#define TM6010_REQ08_RE0_ADC_REF 0xE0 -#define TM6010_REQ08_RE1_DAC_CLMP 0xE1 -#define TM6010_REQ08_RE2_POWER_DOWN_CTRL1 0xE2 -#define TM6010_REQ08_RE3_ADC_IN1_SEL 0xE3 -#define TM6010_REQ08_RE4_ADC_IN2_SEL 0xE4 -#define TM6010_REQ08_RE5_GAIN_PARAM 0xE5 -#define TM6010_REQ08_RE6_POWER_DOWN_CTRL2 0xE6 -#define TM6010_REQ08_RE7_REG_GAIN_Y 0xE7 -#define TM6010_REQ08_RE8_REG_GAIN_C 0xE8 -#define TM6010_REQ08_RE9_BIAS_CTRL 0xE9 -#define TM6010_REQ08_REA_BUFF_DRV_CTRL 0xEA -#define TM6010_REQ08_REB_SIF_GAIN_CTRL 0xEB -#define TM6010_REQ08_REC_REVERSE_YC_CTRL 0xEC -#define TM6010_REQ08_RED_GAIN_SEL 0xED +#define TM6010_REQ08_RE0_ADC_REF 0x08, 0xe0 +#define TM6010_REQ08_RE1_DAC_CLMP 0x08, 0xe1 +#define TM6010_REQ08_RE2_POWER_DOWN_CTRL1 0x08, 0xe2 +#define TM6010_REQ08_RE3_ADC_IN1_SEL 0x08, 0xe3 +#define TM6010_REQ08_RE4_ADC_IN2_SEL 0x08, 0xe4 +#define TM6010_REQ08_RE5_GAIN_PARAM 0x08, 0xe5 +#define TM6010_REQ08_RE6_POWER_DOWN_CTRL2 0x08, 0xe6 +#define TM6010_REQ08_RE7_REG_GAIN_Y 0x08, 0xe7 +#define TM6010_REQ08_RE8_REG_GAIN_C 0x08, 0xe8 +#define TM6010_REQ08_RE9_BIAS_CTRL 0x08, 0xe9 +#define TM6010_REQ08_REA_BUFF_DRV_CTRL 0x08, 0xea +#define TM6010_REQ08_REB_SIF_GAIN_CTRL 0x08, 0xeb +#define TM6010_REQ08_REC_REVERSE_YC_CTRL 0x08, 0xec +#define TM6010_REQ08_RED_GAIN_SEL 0x08, 0xed /* Define TM6000/TM6010 Audio ADC registers */ -#define TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG 0xF0 -#define TM6010_REQ08_RF1_AADC_POWER_DOWN 0xF1 -#define TM6010_REQ08_RF2_LEFT_CHANNEL_VOL 0xF2 -#define TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL 0xF3 +#define TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG 0x08, 0xf0 +#define TM6010_REQ08_RF1_AADC_POWER_DOWN 0x08, 0xf1 +#define TM6010_REQ08_RF2_LEFT_CHANNEL_VOL 0x08, 0xf2 +#define TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL 0x08, 0xf3 -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/7] V4L/DVB: tm6000: Replace all Req 8 group of regs with another naming convention [not found] <cover.1268311636.git.mchehab@redhat.com> ` (4 preceding siblings ...) 2010-03-11 13:26 ` [PATCH 3/7] V4L/DVB: tm6000: Add request at Req07/Req08 register definitions Mauro Carvalho Chehab @ 2010-03-11 13:26 ` Mauro Carvalho Chehab 2010-03-11 13:26 ` [PATCH 1/7] V4L/DVB: tm6000: Replace all Req 7 " Mauro Carvalho Chehab 6 siblings, 0 replies; 7+ messages in thread From: Mauro Carvalho Chehab @ 2010-03-11 13:26 UTC (permalink / raw) To: linux-media According with the original patch that added the register names, those are related to tm6010, so name it properly as such. Also, clearly indicates when a register belongs to Request 0x08 and add its register value at the name. This makes easier to double check if the proper register is used along the driver. This patch were made with the help of this simple perl script, applied over the definitions of the last register groups: if (m/define (TM6000_)([^\s]+)\s+0x([A-F0-9].)/) { $name=$2; $val=$3; printf "s,$1$2,TM6010_REQ08_R%s_%s,g\n", $val, $name; } And were manually adjusted to fix a few minor issues. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> diff --git a/drivers/staging/tm6000/tm6000-regs.h b/drivers/staging/tm6000/tm6000-regs.h index 321eb3f..00f7e04 100644 --- a/drivers/staging/tm6000/tm6000-regs.h +++ b/drivers/staging/tm6000/tm6000-regs.h @@ -478,64 +478,64 @@ enum { #define TM6000_U_DATA_FIFO15 0xFC /* Define TM6000/TM6010 Audio decoder registers */ -#define TM6000_A_VERSION 0x00 -#define TM6000_A_INIT 0x01 -#define TM6000_A_FIX_GAIN_CTRL 0x02 -#define TM6000_A_AUTO_GAIN_CTRL 0x03 -#define TM6000_A_SIF_AMP_CTRL 0x04 -#define TM6000_A_STANDARD_MOD 0x05 -#define TM6000_A_SOUND_MOD 0x06 -#define TM6000_A_LEFT_VOL 0x07 -#define TM6000_A_RIGHT_VOL 0x08 -#define TM6000_A_MAIN_VOL 0x09 -#define TM6000_A_I2S_MOD 0x0A -#define TM6000_A_ASD_THRES1 0x0B -#define TM6000_A_ASD_THRES2 0x0C -#define TM6000_A_AMD_THRES 0x0D -#define TM6000_A_MONO_THRES1 0x0E -#define TM6000_A_MONO_THRES2 0x0F -#define TM6000_A_MUTE_THRES1 0x10 -#define TM6000_A_MUTE_THRES2 0x11 -#define TM6000_A_AGC_U 0x12 -#define TM6000_A_AGC_ERR_T 0x13 -#define TM6000_A_AGC_GAIN_INIT 0x14 -#define TM6000_A_AGC_STEP_THR 0x15 -#define TM6000_A_AGC_GAIN_MAX 0x16 -#define TM6000_A_AGC_GAIN_MIN 0x17 -#define TM6000_A_TR_CTRL 0x18 -#define TM6000_A_FH_2FH_GAIN 0x19 -#define TM6000_A_NICAM_SER_MAX 0x1A -#define TM6000_A_NICAM_SER_MIN 0x1B -#define TM6000_A_GAIN_DEEMPH_OUT 0x1E -#define TM6000_A_TEST_INTF_SEL 0x1F -#define TM6000_A_TEST_PIN_SEL 0x20 -#define TM6000_A_AGC_ERR 0x21 -#define TM6000_A_AGC_GAIN 0x22 -#define TM6000_A_NICAM_INFO 0x23 -#define TM6000_A_SER 0x24 -#define TM6000_A_C1_AMP 0x25 -#define TM6000_A_C2_AMP 0x26 -#define TM6000_A_NOISE_AMP 0x27 -#define TM6000_A_AUDIO_MODE_RES 0x28 +#define TM6010_REQ08_R00_A_VERSION 0x00 +#define TM6010_REQ08_R01_A_INIT 0x01 +#define TM6010_REQ08_R02_A_FIX_GAIN_CTRL 0x02 +#define TM6010_REQ08_R03_A_AUTO_GAIN_CTRL 0x03 +#define TM6010_REQ08_R04_A_SIF_AMP_CTRL 0x04 +#define TM6010_REQ08_R05_A_STANDARD_MOD 0x05 +#define TM6010_REQ08_R06_A_SOUND_MOD 0x06 +#define TM6010_REQ08_R07_A_LEFT_VOL 0x07 +#define TM6010_REQ08_R08_A_RIGHT_VOL 0x08 +#define TM6010_REQ08_R09_A_MAIN_VOL 0x09 +#define TM6010_REQ08_R0A_A_I2S_MOD 0x0A +#define TM6010_REQ08_R0B_A_ASD_THRES1 0x0B +#define TM6010_REQ08_R0C_A_ASD_THRES2 0x0C +#define TM6010_REQ08_R0D_A_AMD_THRES 0x0D +#define TM6010_REQ08_R0E_A_MONO_THRES1 0x0E +#define TM6010_REQ08_R0F_A_MONO_THRES2 0x0F +#define TM6010_REQ08_R10_A_MUTE_THRES1 0x10 +#define TM6010_REQ08_R11_A_MUTE_THRES2 0x11 +#define TM6010_REQ08_R12_A_AGC_U 0x12 +#define TM6010_REQ08_R13_A_AGC_ERR_T 0x13 +#define TM6010_REQ08_R14_A_AGC_GAIN_INIT 0x14 +#define TM6010_REQ08_R15_A_AGC_STEP_THR 0x15 +#define TM6010_REQ08_R16_A_AGC_GAIN_MAX 0x16 +#define TM6010_REQ08_R17_A_AGC_GAIN_MIN 0x17 +#define TM6010_REQ08_R18_A_TR_CTRL 0x18 +#define TM6010_REQ08_R19_A_FH_2FH_GAIN 0x19 +#define TM6010_REQ08_R1A_A_NICAM_SER_MAX 0x1A +#define TM6010_REQ08_R1B_A_NICAM_SER_MIN 0x1B +#define TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT 0x1E +#define TM6010_REQ08_R1F_A_TEST_INTF_SEL 0x1F +#define TM6010_REQ08_R20_A_TEST_PIN_SEL 0x20 +#define TM6010_REQ08_R21_A_AGC_ERR 0x21 +#define TM6010_REQ08_R22_A_AGC_GAIN 0x22 +#define TM6010_REQ08_R23_A_NICAM_INFO 0x23 +#define TM6010_REQ08_R24_A_SER 0x24 +#define TM6010_REQ08_R25_A_C1_AMP 0x25 +#define TM6010_REQ08_R26_A_C2_AMP 0x26 +#define TM6010_REQ08_R27_A_NOISE_AMP 0x27 +#define TM6010_REQ08_R28_A_AUDIO_MODE_RES 0x28 /* Define TM6000/TM6010 Video ADC registers */ -#define TM6000_ADC_REF 0xE0 -#define TM6000_DAC_CLMP 0xE1 -#define TM6000_POWER_DOWN_CTRL1 0xE2 -#define TM6000_ADC_IN1_SEL 0xE3 -#define TM6000_ADC_IN2_SEL 0xE4 -#define TM6000_GAIN_PARAM 0xE5 -#define TM6000_POWER_DOWN_CTRL2 0xE6 -#define TM6000_REG_GAIN_Y 0xE7 -#define TM6000_REG_GAIN_C 0xE8 -#define TM6000_BIAS_CTRL 0xE9 -#define TM6000_BUFF_DRV_CTRL 0xEA -#define TM6000_SIF_GAIN_CTRL 0xEB -#define TM6000_REVERSE_YC_CTRL 0xEC -#define TM6000_GAIN_SEL 0xED +#define TM6010_REQ08_RE0_ADC_REF 0xE0 +#define TM6010_REQ08_RE1_DAC_CLMP 0xE1 +#define TM6010_REQ08_RE2_POWER_DOWN_CTRL1 0xE2 +#define TM6010_REQ08_RE3_ADC_IN1_SEL 0xE3 +#define TM6010_REQ08_RE4_ADC_IN2_SEL 0xE4 +#define TM6010_REQ08_RE5_GAIN_PARAM 0xE5 +#define TM6010_REQ08_RE6_POWER_DOWN_CTRL2 0xE6 +#define TM6010_REQ08_RE7_REG_GAIN_Y 0xE7 +#define TM6010_REQ08_RE8_REG_GAIN_C 0xE8 +#define TM6010_REQ08_RE9_BIAS_CTRL 0xE9 +#define TM6010_REQ08_REA_BUFF_DRV_CTRL 0xEA +#define TM6010_REQ08_REB_SIF_GAIN_CTRL 0xEB +#define TM6010_REQ08_REC_REVERSE_YC_CTRL 0xEC +#define TM6010_REQ08_RED_GAIN_SEL 0xED /* Define TM6000/TM6010 Audio ADC registers */ -#define TM6000_DAUDIO_INPUT_CONFIG 0xF0 -#define TM6000_AADC_POWER_DOWN 0xF1 -#define TM6000_LEFT_CHANNEL_VOL 0xF2 -#define TM6000_RIGHT_CHANNEL_VOL 0xF3 +#define TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG 0xF0 +#define TM6010_REQ08_RF1_AADC_POWER_DOWN 0xF1 +#define TM6010_REQ08_RF2_LEFT_CHANNEL_VOL 0xF2 +#define TM6010_REQ08_RF3_RIGHT_CHANNEL_VOL 0xF3 -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 1/7] V4L/DVB: tm6000: Replace all Req 7 group of regs with another naming convention [not found] <cover.1268311636.git.mchehab@redhat.com> ` (5 preceding siblings ...) 2010-03-11 13:26 ` [PATCH 2/7] V4L/DVB: tm6000: Replace all Req 8 group of regs with another naming convention Mauro Carvalho Chehab @ 2010-03-11 13:26 ` Mauro Carvalho Chehab 6 siblings, 0 replies; 7+ messages in thread From: Mauro Carvalho Chehab @ 2010-03-11 13:26 UTC (permalink / raw) To: linux-media According with the original patch that added the register names, those are related to tm6010, so name it properly as such. Also, clearly indicates when a register belongs to Request 0x07 and add its register value at the name. This makes easier to double check if the proper register is used along the driver. This patch were made with the help of this simple perl script: if (m/define (TM6000_)([^\s]+)\s+0x([A-F0-9].)/) { $name=$2; $val=$3; printf "s,$1$2,TM6010_REQ07_R%s_%s,g\n", $val, $name; } And were manually adjusted to fix a few minor issues. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> diff --git a/drivers/staging/tm6000/tm6000-regs.h b/drivers/staging/tm6000/tm6000-regs.h index 9af4c06..321eb3f 100644 --- a/drivers/staging/tm6000/tm6000-regs.h +++ b/drivers/staging/tm6000/tm6000-regs.h @@ -98,186 +98,186 @@ enum { }; /* Define TM6000/TM6010 Video decoder registers */ -#define TM6000_VIDEO_CONTROL0 0x00 -#define TM6000_VIDEO_CONTROL1 0x01 -#define TM6000_VIDEO_CONTROL2 0x02 -#define TM6000_YC_SEP_CONTROL 0x03 -#define TM6000_LUMA_HAGC_CONTROL 0x04 -#define TM6000_NOISE_THRESHOLD 0x05 -#define TM6000_AGC_GATE_THRESHOLD 0x06 -#define TM6000_OUTPUT_CONTROL 0x07 -#define TM6000_LUMA_CONTRAST_ADJ 0x08 -#define TM6000_LUMA_BRIGHTNESS_ADJ 0x09 -#define TM6000_CHROMA_SATURATION_ADJ 0x0A -#define TM6000_CHROMA_HUE_PHASE_ADJ 0x0B -#define TM6000_CHROMA_AGC_CONTROL 0x0C -#define TM6000_CHROMA_KILL_LEVEL 0x0D -#define TM6000_CHROMA_AUTO_POSITION 0x0F -#define TM6000_AGC_PEAK_NOMINAL 0x10 -#define TM6000_AGC_PEAK_CONTROL 0x11 -#define TM6000_AGC_GATE_STARTH 0x12 -#define TM6000_AGC_GATE_STARTL 0x13 -#define TM6000_AGC_GATE_WIDTH 0x14 -#define TM6000_AGC_BP_DELAY 0x15 -#define TM6000_LOCK_COUNT 0x16 -#define TM6000_HLOOP_MAXSTATE 0x17 -#define TM6000_CHROMA_DTO_INCREMENT3 0x18 -#define TM6000_CHROMA_DTO_INCREMENT2 0x19 -#define TM6000_CHROMA_DTO_INCREMENT1 0x1A -#define TM6000_CHROMA_DTO_INCREMENT0 0x1B -#define TM6000_HSYNC_DTO_INCREMENT3 0x1C -#define TM6000_HSYNC_DTO_INCREMENT2 0x1D -#define TM6000_HSYNC_DTO_INCREMENT1 0x1E -#define TM6000_HSYNC_DTO_INCREMENT0 0x1F -#define TM6000_HSYNC_RISING_EDGE_TIME 0x20 -#define TM6000_HSYNC_PHASE_OFFSET 0x21 -#define TM6000_HSYNC_PLL_START_TIME 0x22 -#define TM6000_HSYNC_PLL_END_TIME 0x23 -#define TM6000_HSYNC_TIP_START_TIME 0x24 -#define TM6000_HSYNC_TIP_END_TIME 0x25 -#define TM6000_HSYNC_RISING_EDGE_START 0x26 -#define TM6000_HSYNC_RISING_EDGE_END 0x27 -#define TM6000_BACKPORCH_START 0x28 -#define TM6000_BACKPORCH_END 0x29 -#define TM6000_HSYNC_FILTER_START 0x2A -#define TM6000_HSYNC_FILTER_END 0x2B -#define TM6000_CHROMA_BURST_START 0x2C -#define TM6000_CHROMA_BURST_END 0x2D -#define TM6000_ACTIVE_VIDEO_HSTART 0x2E -#define TM6000_ACTIVE_VIDEO_HWIDTH 0x2F -#define TM6000_ACTIVE_VIDEO_VSTART 0x30 -#define TM6000_ACTIVE_VIDEO_VHIGHT 0x31 -#define TM6000_VSYNC_HLOCK_MIN 0x32 -#define TM6000_VSYNC_HLOCK_MAX 0x33 -#define TM6000_VSYNC_AGC_MIN 0x34 -#define TM6000_VSYNC_AGC_MAX 0x35 -#define TM6000_VSYNC_VBI_MIN 0x36 -#define TM6000_VSYNC_VBI_MAX 0x37 -#define TM6000_VSYNC_THRESHOLD 0x38 -#define TM6000_VSYNC_TIME_CONSTANT 0x39 -#define TM6000_STATUS1 0x3A -#define TM6000_STATUS2 0x3B -#define TM6000_STATUS3 0x3C -#define TM6000_RESET 0x3F -#define TM6000_TELETEXT_VBI_CODE0 0x40 -#define TM6000_TELETEXT_VBI_CODE1 0x41 -#define TM6000_VBI_DATA_HIGH_LEVEL 0x42 -#define TM6000_VBI_DATA_TYPE_LINE7 0x43 -#define TM6000_VBI_DATA_TYPE_LINE8 0x44 -#define TM6000_VBI_DATA_TYPE_LINE9 0x45 -#define TM6000_VBI_DATA_TYPE_LINE10 0x46 -#define TM6000_VBI_DATA_TYPE_LINE11 0x47 -#define TM6000_VBI_DATA_TYPE_LINE12 0x48 -#define TM6000_VBI_DATA_TYPE_LINE13 0x49 -#define TM6000_VBI_DATA_TYPE_LINE14 0x4A -#define TM6000_VBI_DATA_TYPE_LINE15 0x4B -#define TM6000_VBI_DATA_TYPE_LINE16 0x4C -#define TM6000_VBI_DATA_TYPE_LINE17 0x4D -#define TM6000_VBI_DATA_TYPE_LINE18 0x4E -#define TM6000_VBI_DATA_TYPE_LINE19 0x4F -#define TM6000_VBI_DATA_TYPE_LINE20 0x50 -#define TM6000_VBI_DATA_TYPE_LINE21 0x51 -#define TM6000_VBI_DATA_TYPE_LINE22 0x52 -#define TM6000_VBI_DATA_TYPE_LINE23 0x53 -#define TM6000_VBI_DATA_TYPE_RLINES 0x54 -#define TM6000_VBI_LOOP_FILTER_GAIN 0x55 -#define TM6000_VBI_LOOP_FILTER_I_GAIN 0x56 -#define TM6000_VBI_LOOP_FILTER_P_GAIN 0x57 -#define TM6000_VBI_CAPTION_DTO1 0x58 -#define TM6000_VBI_CAPTION_DTO0 0x59 -#define TM6000_VBI_TELETEXT_DTO1 0x5A -#define TM6000_VBI_TELETEXT_DTO0 0x5B -#define TM6000_VBI_WSS625_DTO1 0x5C -#define TM6000_VBI_WSS625_DTO0 0x5D -#define TM6000_VBI_CAPTION_FRAME_START 0x5E -#define TM6000_VBI_WSS625_FRAME_START 0x5F -#define TM6000_TELETEXT_FRAME_START 0x60 -#define TM6000_VBI_CCDATA1 0x61 -#define TM6000_VBI_CCDATA2 0x62 -#define TM6000_VBI_WSS625_DATA1 0x63 -#define TM6000_VBI_WSS625_DATA2 0x64 -#define TM6000_VBI_DATA_STATUS 0x65 -#define TM6000_VBI_CAPTION_START 0x66 -#define TM6000_VBI_WSS625_START 0x67 -#define TM6000_VBI_TELETEXT_START 0x68 -#define TM6000_HSYNC_DTO_INC_STATUS3 0x70 -#define TM6000_HSYNC_DTO_INC_STATUS2 0x71 -#define TM6000_HSYNC_DTO_INC_STATUS1 0x72 -#define TM6000_HSYNC_DTO_INC_STATUS0 0x73 -#define TM6000_CHROMA_DTO_INC_STATUS3 0x74 -#define TM6000_CHROMA_DTO_INC_STATUS2 0x75 -#define TM6000_CHROMA_DTO_INC_STATUS1 0x76 -#define TM6000_CHROMA_DTO_INC_STATUS0 0x77 -#define TM6000_AGC_AGAIN_STATUS 0x78 -#define TM6000_AGC_DGAIN_STATUS 0x79 -#define TM6000_CHROMA_MAG_STATUS 0x7A -#define TM6000_CHROMA_GAIN_STATUS1 0x7B -#define TM6000_CHROMA_GAIN_STATUS0 0x7C -#define TM6000_CORDIC_FREQ_STATUS 0x7D -#define TM6000_STATUS_NOISE 0x7F -#define TM6000_COMB_FILTER_TRESHOLD 0x80 -#define TM6000_COMB_FILTER_CONFIG 0x82 -#define TM6000_CHROMA_LOCK_CONFIG 0x83 -#define TM6000_NOISE_NTSC_C 0x84 -#define TM6000_NOISE_PAL_C 0x85 -#define TM6000_NOISE_PHASE_C 0x86 -#define TM6000_NOISE_PHASE_Y 0x87 -#define TM6000_CHROMA_LOOPFILTER_STATE 0x8A -#define TM6000_CHROMA_HRESAMPLER 0x8B -#define TM6000_CPUMP_DELAY_ADJ 0x8D -#define TM6000_CPUMP_ADJ 0x8E -#define TM6000_CPUMP_DELAY 0x8F +#define TM6010_REQ07_R00_VIDEO_CONTROL0 0x00 +#define TM6010_REQ07_R01_VIDEO_CONTROL1 0x01 +#define TM6010_REQ07_R02_VIDEO_CONTROL2 0x02 +#define TM6010_REQ07_R03_YC_SEP_CONTROL 0x03 +#define TM6010_REQ07_R04_LUMA_HAGC_CONTROL 0x04 +#define TM6010_REQ07_R05_NOISE_THRESHOLD 0x05 +#define TM6010_REQ07_R06_AGC_GATE_THRESHOLD 0x06 +#define TM6010_REQ07_R07_OUTPUT_CONTROL 0x07 +#define TM6010_REQ07_R08_LUMA_CONTRAST_ADJ 0x08 +#define TM6010_REQ07_R09_LUMA_BRIGHTNESS_ADJ 0x09 +#define TM6010_REQ07_R0A_CHROMA_SATURATION_ADJ 0x0A +#define TM6010_REQ07_R0B_CHROMA_HUE_PHASE_ADJ 0x0B +#define TM6010_REQ07_R0C_CHROMA_AGC_CONTROL 0x0C +#define TM6010_REQ07_R0D_CHROMA_KILL_LEVEL 0x0D +#define TM6010_REQ07_R0F_CHROMA_AUTO_POSITION 0x0F +#define TM6010_REQ07_R10_AGC_PEAK_NOMINAL 0x10 +#define TM6010_REQ07_R11_AGC_PEAK_CONTROL 0x11 +#define TM6010_REQ07_R12_AGC_GATE_STARTH 0x12 +#define TM6010_REQ07_R13_AGC_GATE_STARTL 0x13 +#define TM6010_REQ07_R14_AGC_GATE_WIDTH 0x14 +#define TM6010_REQ07_R15_AGC_BP_DELAY 0x15 +#define TM6010_REQ07_R16_LOCK_COUNT 0x16 +#define TM6010_REQ07_R17_HLOOP_MAXSTATE 0x17 +#define TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3 0x18 +#define TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2 0x19 +#define TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1 0x1A +#define TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0 0x1B +#define TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3 0x1C +#define TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2 0x1D +#define TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1 0x1E +#define TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0 0x1F +#define TM6010_REQ07_R20_HSYNC_RISING_EDGE_TIME 0x20 +#define TM6010_REQ07_R21_HSYNC_PHASE_OFFSET 0x21 +#define TM6010_REQ07_R22_HSYNC_PLL_START_TIME 0x22 +#define TM6010_REQ07_R23_HSYNC_PLL_END_TIME 0x23 +#define TM6010_REQ07_R24_HSYNC_TIP_START_TIME 0x24 +#define TM6010_REQ07_R25_HSYNC_TIP_END_TIME 0x25 +#define TM6010_REQ07_R26_HSYNC_RISING_EDGE_START 0x26 +#define TM6010_REQ07_R27_HSYNC_RISING_EDGE_END 0x27 +#define TM6010_REQ07_R28_BACKPORCH_START 0x28 +#define TM6010_REQ07_R29_BACKPORCH_END 0x29 +#define TM6010_REQ07_R2A_HSYNC_FILTER_START 0x2A +#define TM6010_REQ07_R2B_HSYNC_FILTER_END 0x2B +#define TM6010_REQ07_R2C_CHROMA_BURST_START 0x2C +#define TM6010_REQ07_R2D_CHROMA_BURST_END 0x2D +#define TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART 0x2E +#define TM6010_REQ07_R2F_ACTIVE_VIDEO_HWIDTH 0x2F +#define TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART 0x30 +#define TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT 0x31 +#define TM6010_REQ07_R32_VSYNC_HLOCK_MIN 0x32 +#define TM6010_REQ07_R33_VSYNC_HLOCK_MAX 0x33 +#define TM6010_REQ07_R34_VSYNC_AGC_MIN 0x34 +#define TM6010_REQ07_R35_VSYNC_AGC_MAX 0x35 +#define TM6010_REQ07_R36_VSYNC_VBI_MIN 0x36 +#define TM6010_REQ07_R37_VSYNC_VBI_MAX 0x37 +#define TM6010_REQ07_R38_VSYNC_THRESHOLD 0x38 +#define TM6010_REQ07_R39_VSYNC_TIME_CONSTANT 0x39 +#define TM6010_REQ07_R3A_STATUS1 0x3A +#define TM6010_REQ07_R3B_STATUS2 0x3B +#define TM6010_REQ07_R3C_STATUS3 0x3C +#define TM6010_REQ07_R3F_RESET 0x3F +#define TM6010_REQ07_R40_TELETEXT_VBI_CODE0 0x40 +#define TM6010_REQ07_R41_TELETEXT_VBI_CODE1 0x41 +#define TM6010_REQ07_R42_VBI_DATA_HIGH_LEVEL 0x42 +#define TM6010_REQ07_R43_VBI_DATA_TYPE_LINE7 0x43 +#define TM6010_REQ07_R44_VBI_DATA_TYPE_LINE8 0x44 +#define TM6010_REQ07_R45_VBI_DATA_TYPE_LINE9 0x45 +#define TM6010_REQ07_R46_VBI_DATA_TYPE_LINE10 0x46 +#define TM6010_REQ07_R47_VBI_DATA_TYPE_LINE11 0x47 +#define TM6010_REQ07_R48_VBI_DATA_TYPE_LINE12 0x48 +#define TM6010_REQ07_R49_VBI_DATA_TYPE_LINE13 0x49 +#define TM6010_REQ07_R4A_VBI_DATA_TYPE_LINE14 0x4A +#define TM6010_REQ07_R4B_VBI_DATA_TYPE_LINE15 0x4B +#define TM6010_REQ07_R4C_VBI_DATA_TYPE_LINE16 0x4C +#define TM6010_REQ07_R4D_VBI_DATA_TYPE_LINE17 0x4D +#define TM6010_REQ07_R4E_VBI_DATA_TYPE_LINE18 0x4E +#define TM6010_REQ07_R4F_VBI_DATA_TYPE_LINE19 0x4F +#define TM6010_REQ07_R50_VBI_DATA_TYPE_LINE20 0x50 +#define TM6010_REQ07_R51_VBI_DATA_TYPE_LINE21 0x51 +#define TM6010_REQ07_R52_VBI_DATA_TYPE_LINE22 0x52 +#define TM6010_REQ07_R53_VBI_DATA_TYPE_LINE23 0x53 +#define TM6010_REQ07_R54_VBI_DATA_TYPE_RLINES 0x54 +#define TM6010_REQ07_R55_VBI_LOOP_FILTER_GAIN 0x55 +#define TM6010_REQ07_R56_VBI_LOOP_FILTER_I_GAIN 0x56 +#define TM6010_REQ07_R57_VBI_LOOP_FILTER_P_GAIN 0x57 +#define TM6010_REQ07_R58_VBI_CAPTION_DTO1 0x58 +#define TM6010_REQ07_R59_VBI_CAPTION_DTO0 0x59 +#define TM6010_REQ07_R5A_VBI_TELETEXT_DTO1 0x5A +#define TM6010_REQ07_R5B_VBI_TELETEXT_DTO0 0x5B +#define TM6010_REQ07_R5C_VBI_WSS625_DTO1 0x5C +#define TM6010_REQ07_R5D_VBI_WSS625_DTO0 0x5D +#define TM6010_REQ07_R5E_VBI_CAPTION_FRAME_START 0x5E +#define TM6010_REQ07_R5F_VBI_WSS625_FRAME_START 0x5F +#define TM6010_REQ07_R60_TELETEXT_FRAME_START 0x60 +#define TM6010_REQ07_R61_VBI_CCDATA1 0x61 +#define TM6010_REQ07_R62_VBI_CCDATA2 0x62 +#define TM6010_REQ07_R63_VBI_WSS625_DATA1 0x63 +#define TM6010_REQ07_R64_VBI_WSS625_DATA2 0x64 +#define TM6010_REQ07_R65_VBI_DATA_STATUS 0x65 +#define TM6010_REQ07_R66_VBI_CAPTION_START 0x66 +#define TM6010_REQ07_R67_VBI_WSS625_START 0x67 +#define TM6010_REQ07_R68_VBI_TELETEXT_START 0x68 +#define TM6010_REQ07_R70_HSYNC_DTO_INC_STATUS3 0x70 +#define TM6010_REQ07_R71_HSYNC_DTO_INC_STATUS2 0x71 +#define TM6010_REQ07_R72_HSYNC_DTO_INC_STATUS1 0x72 +#define TM6010_REQ07_R73_HSYNC_DTO_INC_STATUS0 0x73 +#define TM6010_REQ07_R74_CHROMA_DTO_INC_STATUS3 0x74 +#define TM6010_REQ07_R75_CHROMA_DTO_INC_STATUS2 0x75 +#define TM6010_REQ07_R76_CHROMA_DTO_INC_STATUS1 0x76 +#define TM6010_REQ07_R77_CHROMA_DTO_INC_STATUS0 0x77 +#define TM6010_REQ07_R78_AGC_AGAIN_STATUS 0x78 +#define TM6010_REQ07_R79_AGC_DGAIN_STATUS 0x79 +#define TM6010_REQ07_R7A_CHROMA_MAG_STATUS 0x7A +#define TM6010_REQ07_R7B_CHROMA_GAIN_STATUS1 0x7B +#define TM6010_REQ07_R7C_CHROMA_GAIN_STATUS0 0x7C +#define TM6010_REQ07_R7D_CORDIC_FREQ_STATUS 0x7D +#define TM6010_REQ07_R7F_STATUS_NOISE 0x7F +#define TM6010_REQ07_R80_COMB_FILTER_TRESHOLD 0x80 +#define TM6010_REQ07_R82_COMB_FILTER_CONFIG 0x82 +#define TM6010_REQ07_R83_CHROMA_LOCK_CONFIG 0x83 +#define TM6010_REQ07_R84_NOISE_NTSC_C 0x84 +#define TM6010_REQ07_R85_NOISE_PAL_C 0x85 +#define TM6010_REQ07_R86_NOISE_PHASE_C 0x86 +#define TM6010_REQ07_R87_NOISE_PHASE_Y 0x87 +#define TM6010_REQ07_R8A_CHROMA_LOOPFILTER_STATE 0x8A +#define TM6010_REQ07_R8B_CHROMA_HRESAMPLER 0x8B +#define TM6010_REQ07_R8D_CPUMP_DELAY_ADJ 0x8D +#define TM6010_REQ07_R8E_CPUMP_ADJ 0x8E +#define TM6010_REQ07_R8F_CPUMP_DELAY 0x8F /* Define TM6000/TM6010 Miscellaneous registers */ -#define TM6000_ACTIVE_VIDEO_SOURCE 0xC0 -#define TM6000_TRESHOLD 0xC1 -#define TM6000_HSYNC_WIDTH 0xC2 -#define TM6000_HSTART1 0xC3 -#define TM6000_HSTART0 0xC4 -#define TM6000_HEND1 0xC5 -#define TM6000_HEND0 0xC6 -#define TM6000_VSTART1 0xC7 -#define TM6000_VSTART0 0xC8 -#define TM6000_VEND1 0xC9 -#define TM6000_VEND0 0xCA -#define TM6000_DELAY 0xCB -#define TM6000_ACTIVE_VIDEO_IF 0xCC -#define TM6000_USB_PERIPHERY_CONTROL 0xD0 -#define TM6000_ADDR_FOR_REQ1 0xD1 -#define TM6000_ADDR_FOR_REQ2 0xD2 -#define TM6000_ADDR_FOR_REQ3 0xD3 -#define TM6000_ADDR_FOR_REQ4 0xD4 -#define TM6000_POWERSAVE 0xD5 -#define TM6000_ENDP_REQ1_REQ2 0xD6 -#define TM6000_ENDP_REQ3_REQ4 0xD7 -#define TM6000_IR 0xD8 -#define TM6000_IR_BSIZE 0xD9 -#define TM6000_IR_WAKEUP_SEL 0xDA -#define TM6000_IR_WAKEUP_ADD 0xDB -#define TM6000_IR_LEADER1 0xDC -#define TM6000_IR_LEADER0 0xDD -#define TM6000_IR_PULSE_CNT1 0xDE -#define TM6000_IR_PULSE_CNT0 0xDF -#define TM6000_DVIDEO_SOURCE 0xE0 -#define TM6000_DVIDEO_SOURCE_IF 0xE1 -#define TM6000_OUT_SEL2 0xE2 -#define TM6000_OUT_SEL1 0xE3 -#define TM6000_OUT_SEL0 0xE4 -#define TM6000_REMOTE_WAKEUP 0xE5 -#define TM6000_PUB_GPIO 0xE7 -#define TM6000_TYPESEL_MOS_I2S 0xE8 -#define TM6000_TYPESEL_MOS_TS 0xE9 -#define TM6000_TYPESEL_MOS_CCIR 0xEA -#define TM6000_BIST_CRC_RESULT0 0xF0 -#define TM6000_BIST_CRC_RESULT1 0xF1 -#define TM6000_BIST_CRC_RESULT2 0xF2 -#define TM6000_BIST_CRC_RESULT3 0xF3 -#define TM6000_BIST_ERR_VST2 0xF4 -#define TM6000_BIST_ERR_VST1 0xF5 -#define TM6000_BIST_ERR_VST0 0xF6 -#define TM6000_BIST 0xF7 -#define TM6000_POWER_DOWN 0xFE -#define TM6000_SOFT_RESET 0xFF +#define TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE 0xC0 +#define TM6010_REQ07_RC1_TRESHOLD 0xC1 +#define TM6010_REQ07_RC2_HSYNC_WIDTH 0xC2 +#define TM6010_REQ07_RC3_HSTART1 0xC3 +#define TM6010_REQ07_RC4_HSTART0 0xC4 +#define TM6010_REQ07_RC5_HEND1 0xC5 +#define TM6010_REQ07_RC6_HEND0 0xC6 +#define TM6010_REQ07_RC7_VSTART1 0xC7 +#define TM6010_REQ07_RC8_VSTART0 0xC8 +#define TM6010_REQ07_RC9_VEND1 0xC9 +#define TM6010_REQ07_RCA_VEND0 0xCA +#define TM6010_REQ07_RCB_DELAY 0xCB +#define TM6010_REQ07_RCC_ACTIVE_VIDEO_IF 0xCC +#define TM6010_REQ07_RD0_USB_PERIPHERY_CONTROL 0xD0 +#define TM6010_REQ07_RD1_ADDR_FOR_REQ1 0xD1 +#define TM6010_REQ07_RD2_ADDR_FOR_REQ2 0xD2 +#define TM6010_REQ07_RD3_ADDR_FOR_REQ3 0xD3 +#define TM6010_REQ07_RD4_ADDR_FOR_REQ4 0xD4 +#define TM6010_REQ07_RD5_POWERSAVE 0xD5 +#define TM6010_REQ07_RD6_ENDP_REQ1_REQ2 0xD6 +#define TM6010_REQ07_RD7_ENDP_REQ3_REQ4 0xD7 +#define TM6010_REQ07_RD8_IR 0xD8 +#define TM6010_REQ07_RD8_IR_BSIZE 0xD9 +#define TM6010_REQ07_RD8_IR_WAKEUP_SEL 0xDA +#define TM6010_REQ07_RD8_IR_WAKEUP_ADD 0xDB +#define TM6010_REQ07_RD8_IR_LEADER1 0xDC +#define TM6010_REQ07_RD8_IR_LEADER0 0xDD +#define TM6010_REQ07_RD8_IR_PULSE_CNT1 0xDE +#define TM6010_REQ07_RD8_IR_PULSE_CNT0 0xDF +#define TM6010_REQ07_RE0_DVIDEO_SOURCE 0xE0 +#define TM6010_REQ07_RE0_DVIDEO_SOURCE_IF 0xE1 +#define TM6010_REQ07_RE2_OUT_SEL2 0xE2 +#define TM6010_REQ07_RE3_OUT_SEL1 0xE3 +#define TM6010_REQ07_RE4_OUT_SEL0 0xE4 +#define TM6010_REQ07_RE5_REMOTE_WAKEUP 0xE5 +#define TM6010_REQ07_RE7_PUB_GPIO 0xE7 +#define TM6010_REQ07_RE8_TYPESEL_MOS_I2S 0xE8 +#define TM6010_REQ07_RE9_TYPESEL_MOS_TS 0xE9 +#define TM6010_REQ07_REA_TYPESEL_MOS_CCIR 0xEA +#define TM6010_REQ07_RF0_BIST_CRC_RESULT0 0xF0 +#define TM6010_REQ07_RF1_BIST_CRC_RESULT1 0xF1 +#define TM6010_REQ07_RF2_BIST_CRC_RESULT2 0xF2 +#define TM6010_REQ07_RF3_BIST_CRC_RESULT3 0xF3 +#define TM6010_REQ07_RF4_BIST_ERR_VST2 0xF4 +#define TM6010_REQ07_RF5_BIST_ERR_VST1 0xF5 +#define TM6010_REQ07_RF6_BIST_ERR_VST0 0xF6 +#define TM6010_REQ07_RF7_BIST 0xF7 +#define TM6010_REQ07_RFE_POWER_DOWN 0xFE +#define TM6010_REQ07_RFF_SOFT_RESET 0xFF /* Define TM6000/TM6010 USB registers */ #define TM6000_U_MAIN_CTRL 0x00 -- 1.6.6.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
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[not found] <cover.1268311636.git.mchehab@redhat.com>
2010-03-11 13:26 ` [PATCH 6/7] V4L/DVB: tm6000: add request to registers of the group 05 Mauro Carvalho Chehab
2010-03-11 13:26 ` [PATCH 5/7] V4L/DVB: tm6000: Replace naming convention for registers of req 05 group Mauro Carvalho Chehab
2010-03-11 13:26 ` [PATCH 7/7] V4L/DVB: tm6000: replace occurences of req05 magic by a naming alias Mauro Carvalho Chehab
2010-03-11 13:26 ` [PATCH 4/7] V4L/DVB: tm6000: Replace all magic values by a register alias Mauro Carvalho Chehab
2010-03-11 13:26 ` [PATCH 3/7] V4L/DVB: tm6000: Add request at Req07/Req08 register definitions Mauro Carvalho Chehab
2010-03-11 13:26 ` [PATCH 2/7] V4L/DVB: tm6000: Replace all Req 8 group of regs with another naming convention Mauro Carvalho Chehab
2010-03-11 13:26 ` [PATCH 1/7] V4L/DVB: tm6000: Replace all Req 7 " Mauro Carvalho Chehab
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