Re: [PATCH] Fix wrong register mask in gspca/sonixj.c

[Jean-Francois Moine <moinejf@free.fr>]

On Thu, 21 Jul 2011 03:43:13 -0700 (PDT)
Luiz Ramos <lramos.prof@yahoo.com.br> wrote:

> Now my doubts. Unless I misunderstood something, it seems these are
> the our assumptions regarding reg01 and reg17:
> 
>   - reg01 bit 6 is set when bridge runs at 48 MHz; if reset, 24 MHz
>   - reg17 bits 0..4 is a mask for dividing a sensor clock of 48 MHz,
> so
>     - if reg17 = x | 01 then clock = 48 MHz
>     - if reg17 = x | 02 then clock = 24 MHz
>     - if reg17 = x | 04 then clock = 12 MHz
> 
> Putting some printk at the code version 2.13.3, the values of these
> registers at the last command are:
> 
>   - at 640x480 ........... reg01 = 0x66  reg17 = 0x64
>   - at 320x240/160x120 ... reg01 = 0x26  reg17 = 0x61
> 
> So, at 640x480 the bridge would be running at 48 MHz and the sensor
> at 12 MHz. At lower resolutions the bridge would be running at 24 MHz
> and the sensor at 48 MHz. It seems that this is not what we'd like to
> do.

>From the documentation, the register 17 contains a divide factor of the
bridge clock (the sensor has no clock). So:

- reg01 = 0x66  reg17 = 0x64 --> bridge 48 MHz sensor 12 MHz
- reg01 = 0x26  reg17 = 0x61 --> bridge 24 MHz sensor 24 MHz

> I made some experiences, and noticed that:
> 
>   - making reg17 = 0x62 (sensor clock at 24 MHz) and reg01 = 0x26
>     (bridge clock at 24 MHz) at 320x240 and lower makes it work again.
>     I think this reaches the goal of having both clocks at 24 MHz, but
>     at 10 fps

In fact, bridge 24 MHz and sensor 12 MHz. This seems the best
configuration.

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