From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: devicetree@vger.kernel.org, slongerbeam@gmail.com,
niklas.soderlund@ragnatech.se, jacopo@jmondi.org,
p.zabel@pengutronix.de, dri-devel@lists.freedesktop.org
Subject: [PATCH v3 10/23] v4l: fwnode: Read lane inversion information despite lane numbering
Date: Thu, 13 Sep 2018 00:29:29 +0300 [thread overview]
Message-ID: <20180912212942.19641-11-sakari.ailus@linux.intel.com> (raw)
In-Reply-To: <20180912212942.19641-1-sakari.ailus@linux.intel.com>
Read the lane inversion independently of whether the "data-lanes" property
exists. This makes sense since the caller may pass the number of lanes as
the default configuration while the lane inversion configuration may still
be available in firmware.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
drivers/media/v4l2-core/v4l2-fwnode.c | 65 +++++++++++++++++++----------------
1 file changed, 35 insertions(+), 30 deletions(-)
diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c
index 74c2f4e03e52..cb0b12eefe7f 100644
--- a/drivers/media/v4l2-core/v4l2-fwnode.c
+++ b/drivers/media/v4l2-core/v4l2-fwnode.c
@@ -43,26 +43,31 @@ enum v4l2_fwnode_bus_type {
};
static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
- struct v4l2_fwnode_endpoint *vep)
+ struct v4l2_fwnode_endpoint *vep,
+ enum v4l2_fwnode_bus_type bus_type)
{
struct v4l2_fwnode_bus_mipi_csi2 *bus = &vep->bus.mipi_csi2;
bool have_clk_lane = false;
unsigned int flags = 0, lanes_used = 0;
+ u32 array[1 + V4L2_FWNODE_CSI2_MAX_DATA_LANES];
+ unsigned int num_data_lanes = 0;
unsigned int i;
u32 v;
int rval;
+ if (bus_type == V4L2_FWNODE_BUS_TYPE_CSI2_DPHY)
+ num_data_lanes = min_t(u32, bus->num_data_lanes,
+ V4L2_FWNODE_CSI2_MAX_DATA_LANES);
+
rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
if (rval > 0) {
- u32 array[1 + V4L2_FWNODE_CSI2_MAX_DATA_LANES];
-
- bus->num_data_lanes =
+ num_data_lanes =
min_t(int, V4L2_FWNODE_CSI2_MAX_DATA_LANES, rval);
fwnode_property_read_u32_array(fwnode, "data-lanes", array,
- bus->num_data_lanes);
+ num_data_lanes);
- for (i = 0; i < bus->num_data_lanes; i++) {
+ for (i = 0; i < num_data_lanes; i++) {
if (lanes_used & BIT(array[i]))
pr_warn("duplicated lane %u in data-lanes\n",
array[i]);
@@ -71,30 +76,27 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
bus->data_lanes[i] = array[i];
pr_debug("lane %u position %u\n", i, array[i]);
}
+ }
- rval = fwnode_property_read_u32_array(fwnode,
- "lane-polarities", NULL,
- 0);
- if (rval > 0) {
- if (rval != 1 + bus->num_data_lanes /* clock+data */) {
- pr_warn("invalid number of lane-polarities entries (need %u, got %u)\n",
- 1 + bus->num_data_lanes, rval);
- return -EINVAL;
- }
+ rval = fwnode_property_read_u32_array(fwnode, "lane-polarities", NULL,
+ 0);
+ if (rval > 0) {
+ if (rval != 1 + num_data_lanes /* clock+data */) {
+ pr_warn("invalid number of lane-polarities entries (need %u, got %u)\n",
+ 1 + num_data_lanes, rval);
+ return -EINVAL;
+ }
- fwnode_property_read_u32_array(fwnode,
- "lane-polarities", array,
- 1 + bus->num_data_lanes);
+ fwnode_property_read_u32_array(fwnode, "lane-polarities", array,
+ 1 + num_data_lanes);
- for (i = 0; i < 1 + bus->num_data_lanes; i++) {
- bus->lane_polarities[i] = array[i];
- pr_debug("lane %u polarity %sinverted",
- i, array[i] ? "" : "not ");
- }
- } else {
- pr_debug("no lane polarities defined, assuming not inverted\n");
+ for (i = 0; i < 1 + num_data_lanes; i++) {
+ bus->lane_polarities[i] = array[i];
+ pr_debug("lane %u polarity %sinverted",
+ i, array[i] ? "" : "not ");
}
-
+ } else {
+ pr_debug("no lane polarities defined, assuming not inverted\n");
}
if (!fwnode_property_read_u32(fwnode, "clock-lanes", &v)) {
@@ -114,10 +116,11 @@ static int v4l2_fwnode_endpoint_parse_csi2_bus(struct fwnode_handle *fwnode,
flags |= V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
}
- if (lanes_used || have_clk_lane ||
- (flags & ~V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)) {
+ if (bus_type == V4L2_FWNODE_BUS_TYPE_CSI2_DPHY || lanes_used ||
+ have_clk_lane || (flags & ~V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)) {
bus->flags = flags;
vep->bus_type = V4L2_MBUS_CSI2_DPHY;
+ bus->num_data_lanes = num_data_lanes;
}
return 0;
@@ -273,7 +276,8 @@ static int __v4l2_fwnode_endpoint_parse(struct fwnode_handle *fwnode,
switch (bus_type) {
case V4L2_FWNODE_BUS_TYPE_GUESS:
- rval = v4l2_fwnode_endpoint_parse_csi2_bus(fwnode, vep);
+ rval = v4l2_fwnode_endpoint_parse_csi2_bus(fwnode, vep,
+ bus_type);
if (rval)
return rval;
@@ -289,7 +293,8 @@ static int __v4l2_fwnode_endpoint_parse(struct fwnode_handle *fwnode,
break;
case V4L2_FWNODE_BUS_TYPE_CSI2_DPHY:
vep->bus_type = V4L2_MBUS_CSI2_DPHY;
- rval = v4l2_fwnode_endpoint_parse_csi2_bus(fwnode, vep);
+ rval = v4l2_fwnode_endpoint_parse_csi2_bus(fwnode, vep,
+ bus_type);
if (rval)
return rval;
--
2.11.0
next prev parent reply other threads:[~2018-09-13 2:36 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-12 21:29 [PATCH v3 00/23] V4L2 fwnode rework; support for default configuration Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 01/23] v4l: fwnode: Add debug prints for V4L2 endpoint property parsing Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 02/23] v4l: fwnode: Use fwnode_graph_for_each_endpoint Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 03/23] v4l: fwnode: The CSI-2 clock is continuous if it's not non-continuous Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 04/23] dt-bindings: media: Specify bus type for MIPI D-PHY, others, explicitly Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 05/23] v4l: fwnode: Add definitions for CSI-2 D-PHY, parallel and Bt.656 busses Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 06/23] v4l: mediabus: Recognise CSI-2 D-PHY and C-PHY Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 07/23] v4l: fwnode: Let the caller provide V4L2 fwnode endpoint Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 08/23] v4l: fwnode: Detect bus type correctly Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 09/23] v4l: fwnode: Make use of newly specified bus types Sakari Ailus
2018-09-13 9:14 ` jacopo mondi
2018-09-13 9:43 ` [PATCH v3.1 " Sakari Ailus
2018-09-12 21:29 ` Sakari Ailus [this message]
2018-09-12 21:29 ` [PATCH v3 11/23] v4l: fwnode: Only assign configuration if there is no error Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 12/23] v4l: fwnode: Support driver-defined lane mapping defaults Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 13/23] v4l: fwnode: Support default CSI-2 lane mapping for drivers Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 14/23] v4l: fwnode: Parse the graph endpoint as last Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 15/23] v4l: fwnode: Use default parallel flags Sakari Ailus
2018-09-13 9:17 ` jacopo mondi
2018-09-12 21:29 ` [PATCH v3 16/23] v4l: fwnode: Initialise the V4L2 fwnode endpoints to zero Sakari Ailus
2018-09-13 9:46 ` jacopo mondi
2018-09-13 9:55 ` Sakari Ailus
2018-09-13 10:19 ` Sakari Ailus
2018-09-13 13:19 ` jacopo mondi
2018-09-12 21:29 ` [PATCH v3 17/23] v4l: fwnode: Only zero the struct if bus type is set to V4L2_MBUS_UNKNOWN Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 18/23] v4l: fwnode: Use media bus type for bus parser selection Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 19/23] v4l: fwnode: Print bus type Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 20/23] v4l: fwnode: Use V4L2 fwnode endpoint media bus type if set Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 21/23] v4l: fwnode: Support parsing of CSI-2 C-PHY endpoints Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 22/23] v4l: fwnode: Update V4L2 fwnode endpoint parsing documentation Sakari Ailus
2018-09-12 21:29 ` [PATCH v3 23/23] smiapp: Query the V4L2 endpoint for a specific bus type Sakari Ailus
2018-09-13 9:54 ` [PATCH v3 00/23] V4L2 fwnode rework; support for default configuration jacopo mondi
2018-09-13 10:00 ` Sakari Ailus
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