From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C1D2C282DD for ; Tue, 23 Apr 2019 10:45:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3637B218C3 for ; Tue, 23 Apr 2019 10:45:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727420AbfDWKp1 (ORCPT ); Tue, 23 Apr 2019 06:45:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:63166 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727409AbfDWKp1 (ORCPT ); Tue, 23 Apr 2019 06:45:27 -0400 X-UUID: 5f16cf0156bf4364bd2a78b55eef8fa0-20190423 X-UUID: 5f16cf0156bf4364bd2a78b55eef8fa0-20190423 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1995747627; Tue, 23 Apr 2019 18:45:14 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 23 Apr 2019 18:45:12 +0800 Received: from mtkslt306.mediatek.inc (10.21.14.136) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 23 Apr 2019 18:45:12 +0800 From: Jerry-ch Chen To: , , , , CC: , , , , , , , , , , , , , , , , , Jerry-ch Chen Subject: [RFC PATCH V1 3/6] dt-bindings: mt8183: Added FD dt-bindings Date: Tue, 23 Apr 2019 18:45:02 +0800 Message-ID: <20190423104505.38778-4-Jerry-Ch.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190423104505.38778-1-Jerry-Ch.chen@mediatek.com> References: <20190423104505.38778-1-Jerry-Ch.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 2A2DFFD1C8F982E18A8E5F0A1718B635D82E084AD24295AD2A68E8B94F73AF952000:8 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Jerry-ch Chen This patch adds DT binding documentation for the Face Detection (FD) unit of the camera system on Mediatek's SoCs. Signed-off-by: Jerry-ch Chen --- .../bindings/media/mediatek,mt8183-fd.txt | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt b/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt new file mode 100644 index 000000000000..97c12fd93e7e --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt @@ -0,0 +1,34 @@ +* Mediatek Face Detection Unit (FD) + +Face Detection (FD) unit is a typical memory-to-memory HW device. +It provides hardware accelerated face detection function, and it +is able to detect different poses of faces. FD will writre result +of detected face into memory as output. + +Required properties: +- compatible: "mediatek,mt8183-fd" +- reg: Physical base address and length of the function block register space +- interrupts: interrupt number to the cpu. +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. +- mediatek,larb: must contain the local arbiters in the current Socs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. +- clocks : must contain the FDVT clock +- clock-names: must contain FD_CLK_IMG_FD + +Example: + fd:fd@1502b000 { + compatible = "mediatek,mt8183-fd"; + mediatek,larb = <&larb5>; + mediatek,scp = <&scp>; + iommus = <&iommu M4U_PORT_CAM_FDVT_RP>, + <&iommu M4U_PORT_CAM_FDVT_WR>, + <&iommu M4U_PORT_CAM_FDVT_RB>; + reg = <0 0x1502b000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_FDVT>; + clock-names = "FD_CLK_IMG_FD"; + }; + -- 2.18.0