From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4749C4CEC9 for ; Wed, 18 Sep 2019 08:30:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A156F20640 for ; Wed, 18 Sep 2019 08:30:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729270AbfIRIaG (ORCPT ); Wed, 18 Sep 2019 04:30:06 -0400 Received: from retiisi.org.uk ([95.216.213.190]:40928 "EHLO hillosipuli.retiisi.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725866AbfIRIaG (ORCPT ); Wed, 18 Sep 2019 04:30:06 -0400 Received: from valkosipuli.localdomain (valkosipuli.retiisi.org.uk [IPv6:2a01:4f9:c010:4572::80:2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by hillosipuli.retiisi.org.uk (Postfix) with ESMTPS id 93398634C87; Wed, 18 Sep 2019 11:29:23 +0300 (EEST) Received: from sailus by valkosipuli.localdomain with local (Exim 4.92) (envelope-from ) id 1iAVL2-0001XN-GO; Wed, 18 Sep 2019 11:29:24 +0300 Date: Wed, 18 Sep 2019 11:29:24 +0300 From: Sakari Ailus To: Louis Kuo Cc: hans.verkuil@cisco.com, laurent.pinchart+renesas@ideasonboard.com, tfiga@chromium.org, keiichiw@chromium.org, matthias.bgg@gmail.com, mchehab@kernel.org, yuzhao@chromium.org, zwisler@chromium.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Sean.Cheng@mediatek.com, sj.huang@mediatek.com, christie.yu@mediatek.com, frederic.chen@mediatek.com, Jerry-ch.Chen@mediatek.com, jungo.lin@mediatek.com, Rynn.Wu@mediatek.com, linux-media@vger.kernel.org, srv_heupstream@mediatek.com, devicetree@vger.kernel.org Subject: Re: [RFC PATCH V4 3/4] dt-bindings: mt8183: Add sensor interface dt-bindings Message-ID: <20190918082924.GE5525@valkosipuli.retiisi.org.uk> References: <20190915065004.20257-1-louis.kuo@mediatek.com> <20190915065004.20257-4-louis.kuo@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190915065004.20257-4-louis.kuo@mediatek.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Hi Louis, On Sun, Sep 15, 2019 at 02:50:03PM +0800, Louis Kuo wrote: > This patch adds the DT binding documentation for the sensor interface > module in Mediatek SoCs. > > Signed-off-by: Louis Kuo > --- > .../bindings/media/mediatek-seninf.txt | 30 +++++++++++++++++++ > 1 file changed, 30 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek-seninf.txt > > diff --git a/Documentation/devicetree/bindings/media/mediatek-seninf.txt b/Documentation/devicetree/bindings/media/mediatek-seninf.txt > new file mode 100644 > index 000000000000..bf2eb801cb47 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek-seninf.txt > @@ -0,0 +1,30 @@ > +* Mediatek seninf MIPI-CSI2 host driver > + > +Seninf MIPI-CSI2 host driver is a HW camera interface controller. It support a widely adopted, > +simple, high-speed protocol primarily intended for point-to-point image and video > +transmission between cameras and host devices. Please wrap so it fits to 80 chars per line. You'll also need to document the graph nodes needed. Which ports correspond to which interfaces on the device, for instance? Please document which endpoint properties are required and whether there are any optional ones. > + > +Required properties: > + - compatible: "mediatek,mt8183-seninf" > + - reg: Must contain an entry for each entry in reg-names. > + - reg-names: Must include the following entries: > + "base_reg": seninf registers base > + "rx_reg": Rx analog registers base > + - interrupts: interrupt number to the cpu. > + - clocks : clock name from clock manager > + - clock-names: must be CLK_CAM_SENINF and CLK_TOP_MUX_SENINF. > + It is the clocks of seninf > + > +Example: > + seninf: seninf@1a040000 { > + compatible = "mediatek,mt8183-seninf"; > + reg = <0 0x1a040000 0 0x8000>, > + <0 0x11C80000 0 0x6000>; > + reg-names = "base_reg", "rx_reg"; > + interrupts = ; > + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>; > + clocks = <&camsys CLK_CAM_SENINF>, > + <&topckgen CLK_TOP_MUX_SENINF>; > + clock-names = "CLK_CAM_SENINF", "CLK_TOP_MUX_SENINF"; > + } > + -- Regards, Sakari Ailus