[PATCH v1 14/18] media: hantro: add G2 support to postproc

Benjamin Gaignard
2021-02-17T08:07:17Z

G2 doesn't have the same post processor feature than G1.
Adapt post processor code for G2 requirements.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Signed-off-by: Adrian Ratiu <adrian.ratiu@collabora.com>
---
.../staging/media/hantro/hantro_postproc.c | 35 ++++++++++++-------
1 file changed, 23 insertions(+), 12 deletions(-)

diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c
index 050880f720d6..64eee936285d 100644
--- a/drivers/staging/media/hantro/hantro_postproc.c
+++ b/drivers/staging/media/hantro/hantro_postproc.c
@@ -74,12 +74,6 @@ void hantro_postproc_enable(struct hantro_ctx *ctx)
u32 src_pp_fmt, dst_pp_fmt;
dma_addr_t dst_dma;

- if (!vpu->variant->postproc_regs)
- return;
-
- /* Turn on pipeline mode. Must be done first. */
- HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);
-
src_pp_fmt = VPU_PP_IN_NV12;

switch (ctx->vpu_dst_fmt->fourcc) {
@@ -93,13 +87,32 @@ void hantro_postproc_enable(struct hantro_ctx *ctx)
break;
}

+ if (!vpu->variant->postproc_regs)
+ return;
+
+ /* Turn on pipeline mode. Must be done first. */
+ HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);
+
+ switch (ctx->dev->core_hw_dec_rev) {
+ case HANTRO_G1_REV:
+ HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1);
+ HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1);
+ HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1);
+ HANTRO_PP_REG_WRITE(vpu, max_burst, 16);
+
+ HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width));
+ HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);
+ break;
+ default:
+ vpu_err("PP does not recognize HW revision: %x, disabling\n",
+ ctx->dev->core_hw_dec_rev);
+ hantro_postproc_disable(ctx);
+ return;
+ }
+
dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);

- HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1);
- HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1);
- HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1);
- HANTRO_PP_REG_WRITE(vpu, max_burst, 16);
HANTRO_PP_REG_WRITE(vpu, out_luma_base, dst_dma);
HANTRO_PP_REG_WRITE(vpu, input_width, MB_WIDTH(ctx->dst_fmt.width));
HANTRO_PP_REG_WRITE(vpu, input_height, MB_HEIGHT(ctx->dst_fmt.height));
@@ -107,8 +120,6 @@ void hantro_postproc_enable(struct hantro_ctx *ctx)
HANTRO_PP_REG_WRITE(vpu, output_fmt, dst_pp_fmt);
HANTRO_PP_REG_WRITE(vpu, output_width, ctx->dst_fmt.width);
HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height);
- HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width));
- HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);
}

void hantro_postproc_free(struct hantro_ctx *ctx)
--
2.25.1