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From: paul.elder@ideasonboard.com
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org,
	Dafna Hirschfeld <dafna@fastmail.com>,
	Florian Sylvestre <fsylvestre@baylibre.com>
Subject: Re: [PATCH 3/3] media: rockchip: rkisp1: Define macros for DPCC configurations in UAPI
Date: Fri, 15 Jul 2022 16:49:11 +0900	[thread overview]
Message-ID: <20220715074911.GF3411283@pyrite.rasen.tech> (raw)
In-Reply-To: <20220616160456.21549-4-laurent.pinchart@ideasonboard.com>

Hi Laurent,

On Thu, Jun 16, 2022 at 07:04:56PM +0300, Laurent Pinchart wrote:
> Extend the UAPI rkisp1-config.h header with macros for all DPCC
> configuration fields. While at it, clarify of fix issues in the DPCC
> documentation.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

Reviewed-by: Paul Elder <paul.elder@ideasonboard.com>

> ---
>  .../platform/rockchip/rkisp1/rkisp1-regs.h    |  1 -
>  include/uapi/linux/rkisp1-config.h            | 77 +++++++++++++++----
>  2 files changed, 61 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index dc01f968c19d..a931f7216e9b 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -620,7 +620,6 @@
>  /* DPCC */
>  #define RKISP1_CIF_ISP_DPCC_MODE_DPCC_ENABLE		BIT(0)
>  #define RKISP1_CIF_ISP_DPCC_MODE_GRAYSCALE_MODE		BIT(1)
> -#define RKISP1_CIF_ISP_DPCC_MODE_STAGE1_ENABLE		BIT(2)
>  #define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_MASK		GENMASK(3, 0)
>  #define RKISP1_CIF_ISP_DPCC_SET_USE_MASK		GENMASK(3, 0)
>  #define RKISP1_CIF_ISP_DPCC_METHODS_SET_MASK		0x00001f1f
> diff --git a/include/uapi/linux/rkisp1-config.h b/include/uapi/linux/rkisp1-config.h
> index 583ca0d9a79d..730673ecc63d 100644
> --- a/include/uapi/linux/rkisp1-config.h
> +++ b/include/uapi/linux/rkisp1-config.h
> @@ -117,7 +117,46 @@
>  /*
>   * Defect Pixel Cluster Correction
>   */
> -#define RKISP1_CIF_ISP_DPCC_METHODS_MAX       3
> +#define RKISP1_CIF_ISP_DPCC_METHODS_MAX				3
> +
> +#define RKISP1_CIF_ISP_DPCC_MODE_STAGE1_ENABLE			(1U << 2)
> +
> +#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_INCL_G_CENTER	(1U << 0)
> +#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_INCL_RB_CENTER	(1U << 1)
> +#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_G_3X3		(1U << 2)
> +#define RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_STAGE1_RB_3X3		(1U << 3)
> +
> +/* 0-2 for sets 1-3 */
> +#define RKISP1_CIF_ISP_DPCC_SET_USE_STAGE1_USE_SET(n)		((n) << 0)
> +#define RKISP1_CIF_ISP_DPCC_SET_USE_STAGE1_USE_FIX_SET		(1U << 3)
> +
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_PG_GREEN_ENABLE		(1U << 0)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_LC_GREEN_ENABLE		(1U << 1)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RO_GREEN_ENABLE		(1U << 2)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RND_GREEN_ENABLE	(1U << 3)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RG_GREEN_ENABLE		(1U << 4)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_PG_RED_BLUE_ENABLE	(1U << 8)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_LC_RED_BLUE_ENABLE	(1U << 9)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RO_RED_BLUE_ENABLE	(1U << 10)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RND_RED_BLUE_ENABLE	(1U << 11)
> +#define RKISP1_CIF_ISP_DPCC_METHODS_SET_RG_RED_BLUE_ENABLE	(1U << 12)
> +
> +#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_G(v)			((v) << 0)
> +#define RKISP1_CIF_ISP_DPCC_LINE_THRESH_RB(v)			((v) << 8)
> +#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_G(v)			((v) << 0)
> +#define RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_RB(v)			((v) << 8)
> +#define RKISP1_CIF_ISP_DPCC_PG_FAC_G(v)				((v) << 0)
> +#define RKISP1_CIF_ISP_DPCC_PG_FAC_RB(v)			((v) << 8)
> +#define RKISP1_CIF_ISP_DPCC_RND_THRESH_G(v)			((v) << 0)
> +#define RKISP1_CIF_ISP_DPCC_RND_THRESH_RB(v)			((v) << 8)
> +#define RKISP1_CIF_ISP_DPCC_RG_FAC_G(v)				((v) << 0)
> +#define RKISP1_CIF_ISP_DPCC_RG_FAC_RB(v)			((v) << 8)
> +
> +#define RKISP1_CIF_ISP_DPCC_RO_LIMITS_n_G(n, v)			((v) << ((n) * 4))
> +#define RKISP1_CIF_ISP_DPCC_RO_LIMITS_n_RB(n, v)		((v) << ((n) * 4 + 2))
> +
> +#define RKISP1_CIF_ISP_DPCC_RND_OFFS_n_G(n, v)			((v) << ((n) * 4))
> +#define RKISP1_CIF_ISP_DPCC_RND_OFFS_n_RB(n, v)			((v) << ((n) * 4 + 2))
>  
>  /*
>   * Denoising pre filter
> @@ -249,16 +288,20 @@ struct rkisp1_cif_isp_bls_config {
>  };
>  
>  /**
> - * struct rkisp1_cif_isp_dpcc_methods_config - Methods Configuration used by DPCC
> + * struct rkisp1_cif_isp_dpcc_methods_config - DPCC methods set configuration
>   *
> - * Methods Configuration used by Defect Pixel Cluster Correction
> + * This structure stores the configuration of one set of methods for the DPCC
> + * algorithm. Multiple methods can be selected in each set (independently for
> + * the Green and Red/Blue components) through the @method field, the result is
> + * the logical AND of all enabled methods. The remaining fields set thresholds
> + * and factors for each method.
>   *
> - * @method: Method enable bits
> - * @line_thresh: Line threshold
> - * @line_mad_fac: Line MAD factor
> - * @pg_fac: Peak gradient factor
> - * @rnd_thresh: Rank Neighbor Difference threshold
> - * @rg_fac: Rank gradient factor
> + * @method: Method enable bits (RKISP1_CIF_ISP_DPCC_METHODS_SET_*)
> + * @line_thresh: Line threshold (RKISP1_CIF_ISP_DPCC_LINE_THRESH_*)
> + * @line_mad_fac: Line Mean Absolute Difference factor (RKISP1_CIF_ISP_DPCC_LINE_MAD_FAC_*)
> + * @pg_fac: Peak gradient factor (RKISP1_CIF_ISP_DPCC_PG_FAC_*)
> + * @rnd_thresh: Rank Neighbor Difference threshold (RKISP1_CIF_ISP_DPCC_RND_THRESH_*)
> + * @rg_fac: Rank gradient factor (RKISP1_CIF_ISP_DPCC_RG_FAC_*)
>   */
>  struct rkisp1_cif_isp_dpcc_methods_config {
>  	__u32 method;
> @@ -272,14 +315,16 @@ struct rkisp1_cif_isp_dpcc_methods_config {
>  /**
>   * struct rkisp1_cif_isp_dpcc_config - Configuration used by DPCC
>   *
> - * Configuration used by Defect Pixel Cluster Correction
> + * Configuration used by Defect Pixel Cluster Correction. Three sets of methods
> + * can be configured and selected through the @set_use field. The result is the
> + * logical OR of all enabled sets.
>   *
> - * @mode: dpcc output mode
> - * @output_mode: whether use hard coded methods
> - * @set_use: stage1 methods set
> - * @methods: methods config
> - * @ro_limits: rank order limits
> - * @rnd_offs: differential rank offsets for rank neighbor difference
> + * @mode: DPCC mode (RKISP1_CIF_ISP_DPCC_MODE_*)
> + * @output_mode: Interpolation output mode (RKISP1_CIF_ISP_DPCC_OUTPUT_MODE_*)
> + * @set_use: Methods sets selection (RKISP1_CIF_ISP_DPCC_SET_USE_*)
> + * @methods: Methods sets configuration
> + * @ro_limits: Rank order limits (RKISP1_CIF_ISP_DPCC_RO_LIMITS_*)
> + * @rnd_offs: Differential rank offsets for rank neighbor difference (RKISP1_CIF_ISP_DPCC_RND_OFFS_*)
>   */
>  struct rkisp1_cif_isp_dpcc_config {
>  	__u32 mode;

  reply	other threads:[~2022-07-15  7:49 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-16 16:04 [PATCH 0/3] media: rkisp1: Improve DPCC configuration Laurent Pinchart
2022-06-16 16:04 ` [PATCH 1/3] media: rockchip: rkisp1: Set DPCC methods enable bits inside loop Laurent Pinchart
2022-07-15  7:44   ` paul.elder
2022-07-16  5:11   ` Dafna Hirschfeld
2022-06-16 16:04 ` [PATCH 2/3] media: rockchip: rkisp1: Mask invalid bits in DPCC parameters Laurent Pinchart
2022-07-15  7:56   ` paul.elder
2022-07-16  5:56   ` Dafna Hirschfeld
2022-07-16 11:47     ` Laurent Pinchart
2022-07-16  6:12   ` Dafna Hirschfeld
2022-07-16 11:49     ` Laurent Pinchart
2022-06-16 16:04 ` [PATCH 3/3] media: rockchip: rkisp1: Define macros for DPCC configurations in UAPI Laurent Pinchart
2022-07-15  7:49   ` paul.elder [this message]
2022-08-23 17:24   ` Laurent Pinchart
2022-08-26 19:04   ` Dafna Hirschfeld

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