From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Paul Elder <paul.elder@ideasonboard.com>
Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org,
kieran.bingham@ideasonboard.com, tomi.valkeinen@ideasonboard.com,
umang.jain@ideasonboard.com,
Dafna Hirschfeld <dafna@fastmail.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
"moderated list:ARM/Rockchip SoC support"
<linux-arm-kernel@lists.infradead.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/3] media: rkisp1: regs: Consolidate MI interrupt wrap fields
Date: Thu, 30 Nov 2023 15:45:50 +0200 [thread overview]
Message-ID: <20231130134550.GN8402@pendragon.ideasonboard.com> (raw)
In-Reply-To: <20231129092956.250129-2-paul.elder@ideasonboard.com>
Hi Paul,
Thank you for the patch.
On Wed, Nov 29, 2023 at 06:29:54PM +0900, Paul Elder wrote:
> Consolidate the wraparound fields in the memory interface interrupt
> status registers, so that it can be more succinctly expressed by taking
> the stream ID (main or self) as a parameter.
>
> Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h | 9 +++------
> 1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> index 350f452e676f..bea69a0d766a 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-regs.h
> @@ -172,12 +172,9 @@
> #define RKISP1_CIF_MI_FRAME(stream) BIT((stream)->id)
> #define RKISP1_CIF_MI_MBLK_LINE BIT(2)
> #define RKISP1_CIF_MI_FILL_MP_Y BIT(3)
> -#define RKISP1_CIF_MI_WRAP_MP_Y BIT(4)
> -#define RKISP1_CIF_MI_WRAP_MP_CB BIT(5)
> -#define RKISP1_CIF_MI_WRAP_MP_CR BIT(6)
> -#define RKISP1_CIF_MI_WRAP_SP_Y BIT(7)
> -#define RKISP1_CIF_MI_WRAP_SP_CB BIT(8)
> -#define RKISP1_CIF_MI_WRAP_SP_CR BIT(9)
> +#define RKISP1_CIF_MI_WRAP_Y(stream) BIT(4 + (stream)->id * 3)
> +#define RKISP1_CIF_MI_WRAP_CB(stream) BIT(5 + (stream)->id * 3)
> +#define RKISP1_CIF_MI_WRAP_CR(stream) BIT(6 + (stream)->id * 3)
> #define RKISP1_CIF_MI_DMA_READY BIT(11)
>
> /* MI_STATUS */
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2023-11-30 13:45 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-29 9:29 [PATCH 0/3] media: rkisp1: Misc fixes and debug Paul Elder
2023-11-29 9:29 ` [PATCH 1/3] media: rkisp1: regs: Consolidate MI interrupt wrap fields Paul Elder
2023-11-29 20:03 ` Kieran Bingham
2023-11-30 13:45 ` Laurent Pinchart [this message]
2023-11-29 9:29 ` [PATCH 2/3] media: rkisp1: debug: Add register dump for IS Paul Elder
2023-11-29 11:00 ` Alexander Stein
2023-11-29 20:05 ` Kieran Bingham
2023-11-30 9:47 ` Paul Elder
2023-11-30 9:54 ` Alexander Stein
2023-11-30 10:18 ` Tommaso Merciai
2023-11-30 11:33 ` Paul Elder
2023-11-30 13:42 ` Laurent Pinchart
2023-11-29 9:29 ` [PATCH 3/3] media: rkisp1: debug: Count completed frame interrupts Paul Elder
2023-11-29 11:01 ` Alexander Stein
2023-11-29 20:06 ` Kieran Bingham
2023-11-30 13:54 ` Laurent Pinchart
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