[PATCH 0/3] media: imx415: Add more modes

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* [PATCH 0/3] media: imx415: Add more modes
@ 2023-12-05  9:05 Alexander Stein
  2023-12-05  9:05 ` [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers Alexander Stein
                   ` (2 more replies)
  0 siblings, 3 replies; 15+ messages in thread
From: Alexander Stein @ 2023-12-05  9:05 UTC (permalink / raw)
  To: Mauro Carvalho Chehab, Michael Riesch, Sakari Ailus,
	Laurent Pinchart, Gerald Loacker
  Cc: Alexander Stein, linux-media

Hi,

this small series converts the driver to using CCI helpers.
On top of that more clock setups and modes are added to the driver.
These are all taken from the datasheet. I suspect they all can be calculated
dynamically later on.
Tested on TQMa8MPxL + MBa8MPxL + ISP + Vision Components IMX415 camera.

While working on the driver I notived that imx415 sets mbus code to
MEDIA_BUS_FMT_SGBRG10_1X10, while imx290 uses MEDIA_BUS_FMT_SRGGB10_1X10.
But the datasheets show the same color coding pattern. But both settings seem
to be correct, e.g. the resulting image has correct colors.

I had to remove the identity check locally. I suspect that Vision Components
interjects reading some registers.

Best regards,
Alexander

Alexander Stein (3):
  media: i2c: imx415: Convert to new CCI register access helpers
  media: i2c: imx415: Add more clock configurations
  media: i2c: imx415: Add more supported modes

 drivers/media/i2c/Kconfig  |    2 +
 drivers/media/i2c/imx415.c | 1013 +++++++++++++++++++++++++++---------
 2 files changed, 779 insertions(+), 236 deletions(-)

-- 
2.34.1

^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers
  2023-12-05  9:05 [PATCH 0/3] media: imx415: Add more modes Alexander Stein
@ 2023-12-05  9:05 ` Alexander Stein
  2023-12-05 19:24   ` kernel test robot
                     ` (2 more replies)
  2023-12-05  9:05 ` [PATCH 2/3] media: i2c: imx415: Add more clock configurations Alexander Stein
  2023-12-05  9:05 ` [PATCH 3/3] media: i2c: imx415: Add more supported modes Alexander Stein
  2 siblings, 3 replies; 15+ messages in thread
From: Alexander Stein @ 2023-12-05  9:05 UTC (permalink / raw)
  To: Mauro Carvalho Chehab, Michael Riesch, Sakari Ailus,
	Laurent Pinchart, Gerald Loacker
  Cc: Alexander Stein, linux-media

Use the new common CCI register access helpers to replace the private
register access helpers in the imx415 driver.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 drivers/media/i2c/Kconfig  |   2 +
 drivers/media/i2c/imx415.c | 396 +++++++++++++++----------------------
 2 files changed, 162 insertions(+), 236 deletions(-)

diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 59356eded339..71f8128f2df9 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -194,6 +194,8 @@ config VIDEO_IMX412
 config VIDEO_IMX415
 	tristate "Sony IMX415 sensor support"
 	depends on OF_GPIO
+	select REGMAP_I2C
+	select V4L2_CCI_I2C
 	help
 	  This is a Video4Linux2 sensor driver for the Sony
 	  IMX415 camera.
diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
index 6436a32c4025..bb1a779defab 100644
--- a/drivers/media/i2c/imx415.c
+++ b/drivers/media/i2c/imx415.c
@@ -16,6 +16,7 @@
 #include <linux/slab.h>
 #include <linux/videodev2.h>
 
+#include <media/v4l2-cci.h>
 #include <media/v4l2-ctrls.h>
 #include <media/v4l2-fwnode.h>
 #include <media/v4l2-subdev.h>
@@ -28,76 +29,65 @@
 
 #define IMX415_NUM_CLK_PARAM_REGS 11
 
-#define IMX415_REG_8BIT(n)	  ((1 << 16) | (n))
-#define IMX415_REG_16BIT(n)	  ((2 << 16) | (n))
-#define IMX415_REG_24BIT(n)	  ((3 << 16) | (n))
-#define IMX415_REG_SIZE_SHIFT	  16
-#define IMX415_REG_ADDR_MASK	  0xffff
-
-#define IMX415_MODE		  IMX415_REG_8BIT(0x3000)
+#define IMX415_MODE		  CCI_REG8(0x3000)
 #define IMX415_MODE_OPERATING	  (0)
 #define IMX415_MODE_STANDBY	  BIT(0)
-#define IMX415_REGHOLD		  IMX415_REG_8BIT(0x3001)
+#define IMX415_REGHOLD		  CCI_REG8(0x3001)
 #define IMX415_REGHOLD_INVALID	  (0)
 #define IMX415_REGHOLD_VALID	  BIT(0)
-#define IMX415_XMSTA		  IMX415_REG_8BIT(0x3002)
+#define IMX415_XMSTA		  CCI_REG8(0x3002)
 #define IMX415_XMSTA_START	  (0)
 #define IMX415_XMSTA_STOP	  BIT(0)
-#define IMX415_BCWAIT_TIME	  IMX415_REG_16BIT(0x3008)
-#define IMX415_CPWAIT_TIME	  IMX415_REG_16BIT(0x300A)
-#define IMX415_WINMODE		  IMX415_REG_8BIT(0x301C)
-#define IMX415_ADDMODE		  IMX415_REG_8BIT(0x3022)
-#define IMX415_REVERSE		  IMX415_REG_8BIT(0x3030)
+#define IMX415_BCWAIT_TIME	  CCI_REG16_LE(0x3008)
+#define IMX415_CPWAIT_TIME	  CCI_REG16_LE(0x300A)
+#define IMX415_WINMODE		  CCI_REG8(0x301C)
+#define IMX415_ADDMODE		  CCI_REG8(0x3022)
+#define IMX415_REVERSE		  CCI_REG8(0x3030)
 #define IMX415_HREVERSE_SHIFT	  (0)
 #define IMX415_VREVERSE_SHIFT	  BIT(0)
-#define IMX415_ADBIT		  IMX415_REG_8BIT(0x3031)
-#define IMX415_MDBIT		  IMX415_REG_8BIT(0x3032)
-#define IMX415_SYS_MODE		  IMX415_REG_8BIT(0x3033)
-#define IMX415_OUTSEL		  IMX415_REG_8BIT(0x30C0)
-#define IMX415_DRV		  IMX415_REG_8BIT(0x30C1)
-#define IMX415_VMAX		  IMX415_REG_24BIT(0x3024)
-#define IMX415_HMAX		  IMX415_REG_16BIT(0x3028)
-#define IMX415_SHR0		  IMX415_REG_24BIT(0x3050)
-#define IMX415_GAIN_PCG_0	  IMX415_REG_16BIT(0x3090)
+#define IMX415_ADBIT		  CCI_REG8(0x3031)
+#define IMX415_MDBIT		  CCI_REG8(0x3032)
+#define IMX415_SYS_MODE		  CCI_REG8(0x3033)
+#define IMX415_OUTSEL		  CCI_REG8(0x30C0)
+#define IMX415_DRV		  CCI_REG8(0x30C1)
+#define IMX415_VMAX		  CCI_REG24_LE(0x3024)
+#define IMX415_HMAX		  CCI_REG16_LE(0x3028)
+#define IMX415_SHR0		  CCI_REG24_LE(0x3050)
+#define IMX415_GAIN_PCG_0	  CCI_REG16_LE(0x3090)
 #define IMX415_AGAIN_MIN	  0
 #define IMX415_AGAIN_MAX	  100
 #define IMX415_AGAIN_STEP	  1
-#define IMX415_BLKLEVEL		  IMX415_REG_16BIT(0x30E2)
+#define IMX415_BLKLEVEL		  CCI_REG16_LE(0x30E2)
 #define IMX415_BLKLEVEL_DEFAULT	  50
-#define IMX415_TPG_EN_DUOUT	  IMX415_REG_8BIT(0x30E4)
-#define IMX415_TPG_PATSEL_DUOUT	  IMX415_REG_8BIT(0x30E6)
-#define IMX415_TPG_COLORWIDTH	  IMX415_REG_8BIT(0x30E8)
-#define IMX415_TESTCLKEN_MIPI	  IMX415_REG_8BIT(0x3110)
-#define IMX415_INCKSEL1		  IMX415_REG_8BIT(0x3115)
-#define IMX415_INCKSEL2		  IMX415_REG_8BIT(0x3116)
-#define IMX415_INCKSEL3		  IMX415_REG_16BIT(0x3118)
-#define IMX415_INCKSEL4		  IMX415_REG_16BIT(0x311A)
-#define IMX415_INCKSEL5		  IMX415_REG_8BIT(0x311E)
-#define IMX415_DIG_CLP_MODE	  IMX415_REG_8BIT(0x32C8)
-#define IMX415_WRJ_OPEN		  IMX415_REG_8BIT(0x3390)
-#define IMX415_SENSOR_INFO	  IMX415_REG_16BIT(0x3F12)
+#define IMX415_TPG_EN_DUOUT	  CCI_REG8(0x30E4)
+#define IMX415_TPG_PATSEL_DUOUT	  CCI_REG8(0x30E6)
+#define IMX415_TPG_COLORWIDTH	  CCI_REG8(0x30E8)
+#define IMX415_TESTCLKEN_MIPI	  CCI_REG8(0x3110)
+#define IMX415_INCKSEL1		  CCI_REG8(0x3115)
+#define IMX415_INCKSEL2		  CCI_REG8(0x3116)
+#define IMX415_INCKSEL3		  CCI_REG16_LE(0x3118)
+#define IMX415_INCKSEL4		  CCI_REG16_LE(0x311A)
+#define IMX415_INCKSEL5		  CCI_REG8(0x311E)
+#define IMX415_DIG_CLP_MODE	  CCI_REG8(0x32C8)
+#define IMX415_WRJ_OPEN		  CCI_REG8(0x3390)
+#define IMX415_SENSOR_INFO	  CCI_REG16_LE(0x3F12)
 #define IMX415_SENSOR_INFO_MASK	  0xFFF
 #define IMX415_CHIP_ID		  0x514
-#define IMX415_LANEMODE		  IMX415_REG_16BIT(0x4001)
+#define IMX415_LANEMODE		  CCI_REG16_LE(0x4001)
 #define IMX415_LANEMODE_2	  1
 #define IMX415_LANEMODE_4	  3
-#define IMX415_TXCLKESC_FREQ	  IMX415_REG_16BIT(0x4004)
-#define IMX415_INCKSEL6		  IMX415_REG_8BIT(0x400C)
-#define IMX415_TCLKPOST		  IMX415_REG_16BIT(0x4018)
-#define IMX415_TCLKPREPARE	  IMX415_REG_16BIT(0x401A)
-#define IMX415_TCLKTRAIL	  IMX415_REG_16BIT(0x401C)
-#define IMX415_TCLKZERO		  IMX415_REG_16BIT(0x401E)
-#define IMX415_THSPREPARE	  IMX415_REG_16BIT(0x4020)
-#define IMX415_THSZERO		  IMX415_REG_16BIT(0x4022)
-#define IMX415_THSTRAIL		  IMX415_REG_16BIT(0x4024)
-#define IMX415_THSEXIT		  IMX415_REG_16BIT(0x4026)
-#define IMX415_TLPX		  IMX415_REG_16BIT(0x4028)
-#define IMX415_INCKSEL7		  IMX415_REG_8BIT(0x4074)
-
-struct imx415_reg {
-	u32 address;
-	u32 val;
-};
+#define IMX415_TXCLKESC_FREQ	  CCI_REG16_LE(0x4004)
+#define IMX415_INCKSEL6		  CCI_REG8(0x400C)
+#define IMX415_TCLKPOST		  CCI_REG16_LE(0x4018)
+#define IMX415_TCLKPREPARE	  CCI_REG16_LE(0x401A)
+#define IMX415_TCLKTRAIL	  CCI_REG16_LE(0x401C)
+#define IMX415_TCLKZERO		  CCI_REG16_LE(0x401E)
+#define IMX415_THSPREPARE	  CCI_REG16_LE(0x4020)
+#define IMX415_THSZERO		  CCI_REG16_LE(0x4022)
+#define IMX415_THSTRAIL		  CCI_REG16_LE(0x4024)
+#define IMX415_THSEXIT		  CCI_REG16_LE(0x4026)
+#define IMX415_TLPX		  CCI_REG16_LE(0x4028)
+#define IMX415_INCKSEL7		  CCI_REG8(0x4074)
 
 static const char *const imx415_supply_names[] = {
 	"dvdd",
@@ -118,7 +108,7 @@ static const s64 link_freq_menu_items[] = {
 struct imx415_clk_params {
 	u64 lane_rate;
 	u64 inck;
-	struct imx415_reg regs[IMX415_NUM_CLK_PARAM_REGS];
+	struct cci_reg_sequence regs[IMX415_NUM_CLK_PARAM_REGS];
 };
 
 /* INCK Settings - includes all lane rate and INCK dependent registers */
@@ -201,7 +191,7 @@ static const struct imx415_clk_params imx415_clk_params[] = {
 };
 
 /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
-static const struct imx415_reg imx415_mode_2_720[] = {
+static const struct cci_reg_sequence imx415_mode_2_720[] = {
 	{ IMX415_VMAX, 0x08CA },
 	{ IMX415_HMAX, 0x07F0 },
 	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
@@ -217,7 +207,7 @@ static const struct imx415_reg imx415_mode_2_720[] = {
 };
 
 /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
-static const struct imx415_reg imx415_mode_2_1440[] = {
+static const struct cci_reg_sequence imx415_mode_2_1440[] = {
 	{ IMX415_VMAX, 0x08CA },
 	{ IMX415_HMAX, 0x042A },
 	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
@@ -233,7 +223,7 @@ static const struct imx415_reg imx415_mode_2_1440[] = {
 };
 
 /* all-pixel 4-lane 891 Mbps 30 Hz mode */
-static const struct imx415_reg imx415_mode_4_891[] = {
+static const struct cci_reg_sequence imx415_mode_4_891[] = {
 	{ IMX415_VMAX, 0x08CA },
 	{ IMX415_HMAX, 0x044C },
 	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
@@ -250,7 +240,7 @@ static const struct imx415_reg imx415_mode_4_891[] = {
 
 struct imx415_mode_reg_list {
 	u32 num_of_regs;
-	const struct imx415_reg *regs;
+	const struct cci_reg_sequence *regs;
 };
 
 /*
@@ -323,11 +313,6 @@ static const struct imx415_mode supported_modes[] = {
 	},
 };
 
-static const struct regmap_config imx415_regmap_config = {
-	.reg_bits = 16,
-	.val_bits = 8,
-};
-
 static const char *const imx415_test_pattern_menu[] = {
 	"disabled",
 	"solid black",
@@ -369,7 +354,7 @@ struct imx415 {
  * This table includes fixed register settings and a bunch of undocumented
  * registers that have to be set to another value than default.
  */
-static const struct imx415_reg imx415_init_table[] = {
+static const struct cci_reg_sequence imx415_init_table[] = {
 	/* use all-pixel readout mode, no flip */
 	{ IMX415_WINMODE, 0x00 },
 	{ IMX415_ADDMODE, 0x00 },
@@ -382,77 +367,77 @@ static const struct imx415_reg imx415_init_table[] = {
 	{ IMX415_DRV, 0x00 },
 
 	/* SONY magic registers */
-	{ IMX415_REG_8BIT(0x32D4), 0x21 },
-	{ IMX415_REG_8BIT(0x32EC), 0xA1 },
-	{ IMX415_REG_8BIT(0x3452), 0x7F },
-	{ IMX415_REG_8BIT(0x3453), 0x03 },
-	{ IMX415_REG_8BIT(0x358A), 0x04 },
-	{ IMX415_REG_8BIT(0x35A1), 0x02 },
-	{ IMX415_REG_8BIT(0x36BC), 0x0C },
-	{ IMX415_REG_8BIT(0x36CC), 0x53 },
-	{ IMX415_REG_8BIT(0x36CD), 0x00 },
-	{ IMX415_REG_8BIT(0x36CE), 0x3C },
-	{ IMX415_REG_8BIT(0x36D0), 0x8C },
-	{ IMX415_REG_8BIT(0x36D1), 0x00 },
-	{ IMX415_REG_8BIT(0x36D2), 0x71 },
-	{ IMX415_REG_8BIT(0x36D4), 0x3C },
-	{ IMX415_REG_8BIT(0x36D6), 0x53 },
-	{ IMX415_REG_8BIT(0x36D7), 0x00 },
-	{ IMX415_REG_8BIT(0x36D8), 0x71 },
-	{ IMX415_REG_8BIT(0x36DA), 0x8C },
-	{ IMX415_REG_8BIT(0x36DB), 0x00 },
-	{ IMX415_REG_8BIT(0x3724), 0x02 },
-	{ IMX415_REG_8BIT(0x3726), 0x02 },
-	{ IMX415_REG_8BIT(0x3732), 0x02 },
-	{ IMX415_REG_8BIT(0x3734), 0x03 },
-	{ IMX415_REG_8BIT(0x3736), 0x03 },
-	{ IMX415_REG_8BIT(0x3742), 0x03 },
-	{ IMX415_REG_8BIT(0x3862), 0xE0 },
-	{ IMX415_REG_8BIT(0x38CC), 0x30 },
-	{ IMX415_REG_8BIT(0x38CD), 0x2F },
-	{ IMX415_REG_8BIT(0x395C), 0x0C },
-	{ IMX415_REG_8BIT(0x3A42), 0xD1 },
-	{ IMX415_REG_8BIT(0x3A4C), 0x77 },
-	{ IMX415_REG_8BIT(0x3AE0), 0x02 },
-	{ IMX415_REG_8BIT(0x3AEC), 0x0C },
-	{ IMX415_REG_8BIT(0x3B00), 0x2E },
-	{ IMX415_REG_8BIT(0x3B06), 0x29 },
-	{ IMX415_REG_8BIT(0x3B98), 0x25 },
-	{ IMX415_REG_8BIT(0x3B99), 0x21 },
-	{ IMX415_REG_8BIT(0x3B9B), 0x13 },
-	{ IMX415_REG_8BIT(0x3B9C), 0x13 },
-	{ IMX415_REG_8BIT(0x3B9D), 0x13 },
-	{ IMX415_REG_8BIT(0x3B9E), 0x13 },
-	{ IMX415_REG_8BIT(0x3BA1), 0x00 },
-	{ IMX415_REG_8BIT(0x3BA2), 0x06 },
-	{ IMX415_REG_8BIT(0x3BA3), 0x0B },
-	{ IMX415_REG_8BIT(0x3BA4), 0x10 },
-	{ IMX415_REG_8BIT(0x3BA5), 0x14 },
-	{ IMX415_REG_8BIT(0x3BA6), 0x18 },
-	{ IMX415_REG_8BIT(0x3BA7), 0x1A },
-	{ IMX415_REG_8BIT(0x3BA8), 0x1A },
-	{ IMX415_REG_8BIT(0x3BA9), 0x1A },
-	{ IMX415_REG_8BIT(0x3BAC), 0xED },
-	{ IMX415_REG_8BIT(0x3BAD), 0x01 },
-	{ IMX415_REG_8BIT(0x3BAE), 0xF6 },
-	{ IMX415_REG_8BIT(0x3BAF), 0x02 },
-	{ IMX415_REG_8BIT(0x3BB0), 0xA2 },
-	{ IMX415_REG_8BIT(0x3BB1), 0x03 },
-	{ IMX415_REG_8BIT(0x3BB2), 0xE0 },
-	{ IMX415_REG_8BIT(0x3BB3), 0x03 },
-	{ IMX415_REG_8BIT(0x3BB4), 0xE0 },
-	{ IMX415_REG_8BIT(0x3BB5), 0x03 },
-	{ IMX415_REG_8BIT(0x3BB6), 0xE0 },
-	{ IMX415_REG_8BIT(0x3BB7), 0x03 },
-	{ IMX415_REG_8BIT(0x3BB8), 0xE0 },
-	{ IMX415_REG_8BIT(0x3BBA), 0xE0 },
-	{ IMX415_REG_8BIT(0x3BBC), 0xDA },
-	{ IMX415_REG_8BIT(0x3BBE), 0x88 },
-	{ IMX415_REG_8BIT(0x3BC0), 0x44 },
-	{ IMX415_REG_8BIT(0x3BC2), 0x7B },
-	{ IMX415_REG_8BIT(0x3BC4), 0xA2 },
-	{ IMX415_REG_8BIT(0x3BC8), 0xBD },
-	{ IMX415_REG_8BIT(0x3BCA), 0xBD },
+	{ CCI_REG8(0x32D4), 0x21 },
+	{ CCI_REG8(0x32EC), 0xA1 },
+	{ CCI_REG8(0x3452), 0x7F },
+	{ CCI_REG8(0x3453), 0x03 },
+	{ CCI_REG8(0x358A), 0x04 },
+	{ CCI_REG8(0x35A1), 0x02 },
+	{ CCI_REG8(0x36BC), 0x0C },
+	{ CCI_REG8(0x36CC), 0x53 },
+	{ CCI_REG8(0x36CD), 0x00 },
+	{ CCI_REG8(0x36CE), 0x3C },
+	{ CCI_REG8(0x36D0), 0x8C },
+	{ CCI_REG8(0x36D1), 0x00 },
+	{ CCI_REG8(0x36D2), 0x71 },
+	{ CCI_REG8(0x36D4), 0x3C },
+	{ CCI_REG8(0x36D6), 0x53 },
+	{ CCI_REG8(0x36D7), 0x00 },
+	{ CCI_REG8(0x36D8), 0x71 },
+	{ CCI_REG8(0x36DA), 0x8C },
+	{ CCI_REG8(0x36DB), 0x00 },
+	{ CCI_REG8(0x3724), 0x02 },
+	{ CCI_REG8(0x3726), 0x02 },
+	{ CCI_REG8(0x3732), 0x02 },
+	{ CCI_REG8(0x3734), 0x03 },
+	{ CCI_REG8(0x3736), 0x03 },
+	{ CCI_REG8(0x3742), 0x03 },
+	{ CCI_REG8(0x3862), 0xE0 },
+	{ CCI_REG8(0x38CC), 0x30 },
+	{ CCI_REG8(0x38CD), 0x2F },
+	{ CCI_REG8(0x395C), 0x0C },
+	{ CCI_REG8(0x3A42), 0xD1 },
+	{ CCI_REG8(0x3A4C), 0x77 },
+	{ CCI_REG8(0x3AE0), 0x02 },
+	{ CCI_REG8(0x3AEC), 0x0C },
+	{ CCI_REG8(0x3B00), 0x2E },
+	{ CCI_REG8(0x3B06), 0x29 },
+	{ CCI_REG8(0x3B98), 0x25 },
+	{ CCI_REG8(0x3B99), 0x21 },
+	{ CCI_REG8(0x3B9B), 0x13 },
+	{ CCI_REG8(0x3B9C), 0x13 },
+	{ CCI_REG8(0x3B9D), 0x13 },
+	{ CCI_REG8(0x3B9E), 0x13 },
+	{ CCI_REG8(0x3BA1), 0x00 },
+	{ CCI_REG8(0x3BA2), 0x06 },
+	{ CCI_REG8(0x3BA3), 0x0B },
+	{ CCI_REG8(0x3BA4), 0x10 },
+	{ CCI_REG8(0x3BA5), 0x14 },
+	{ CCI_REG8(0x3BA6), 0x18 },
+	{ CCI_REG8(0x3BA7), 0x1A },
+	{ CCI_REG8(0x3BA8), 0x1A },
+	{ CCI_REG8(0x3BA9), 0x1A },
+	{ CCI_REG8(0x3BAC), 0xED },
+	{ CCI_REG8(0x3BAD), 0x01 },
+	{ CCI_REG8(0x3BAE), 0xF6 },
+	{ CCI_REG8(0x3BAF), 0x02 },
+	{ CCI_REG8(0x3BB0), 0xA2 },
+	{ CCI_REG8(0x3BB1), 0x03 },
+	{ CCI_REG8(0x3BB2), 0xE0 },
+	{ CCI_REG8(0x3BB3), 0x03 },
+	{ CCI_REG8(0x3BB4), 0xE0 },
+	{ CCI_REG8(0x3BB5), 0x03 },
+	{ CCI_REG8(0x3BB6), 0xE0 },
+	{ CCI_REG8(0x3BB7), 0x03 },
+	{ CCI_REG8(0x3BB8), 0xE0 },
+	{ CCI_REG8(0x3BBA), 0xE0 },
+	{ CCI_REG8(0x3BBC), 0xDA },
+	{ CCI_REG8(0x3BBE), 0x88 },
+	{ CCI_REG8(0x3BC0), 0x44 },
+	{ CCI_REG8(0x3BC2), 0x7B },
+	{ CCI_REG8(0x3BC4), 0xA2 },
+	{ CCI_REG8(0x3BC8), 0xBD },
+	{ CCI_REG8(0x3BCA), 0xBD },
 };
 
 static inline struct imx415 *to_imx415(struct v4l2_subdev *sd)
@@ -460,74 +445,25 @@ static inline struct imx415 *to_imx415(struct v4l2_subdev *sd)
 	return container_of(sd, struct imx415, subdev);
 }
 
-static int imx415_read(struct imx415 *sensor, u32 addr)
-{
-	u8 data[3] = { 0 };
-	int ret;
-
-	ret = regmap_raw_read(sensor->regmap, addr & IMX415_REG_ADDR_MASK, data,
-			      (addr >> IMX415_REG_SIZE_SHIFT) & 3);
-	if (ret < 0)
-		return ret;
-
-	return (data[2] << 16) | (data[1] << 8) | data[0];
-}
-
-static int imx415_write(struct imx415 *sensor, u32 addr, u32 value)
-{
-	u8 data[3] = { value & 0xff, (value >> 8) & 0xff, value >> 16 };
-	int ret;
-
-	ret = regmap_raw_write(sensor->regmap, addr & IMX415_REG_ADDR_MASK,
-			       data, (addr >> IMX415_REG_SIZE_SHIFT) & 3);
-	if (ret < 0)
-		dev_err_ratelimited(sensor->dev,
-				    "%u-bit write to 0x%04x failed: %d\n",
-				    ((addr >> IMX415_REG_SIZE_SHIFT) & 3) * 8,
-				    addr & IMX415_REG_ADDR_MASK, ret);
-
-	return 0;
-}
-
 static int imx415_set_testpattern(struct imx415 *sensor, int val)
 {
 	int ret;
 
 	if (val) {
-		ret = imx415_write(sensor, IMX415_BLKLEVEL, 0x00);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_TPG_EN_DUOUT, 0x01);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_TPG_PATSEL_DUOUT, val - 1);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_TPG_COLORWIDTH, 0x01);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_TESTCLKEN_MIPI, 0x20);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_DIG_CLP_MODE, 0x00);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_WRJ_OPEN, 0x00);
+		cci_write(sensor->regmap, IMX415_BLKLEVEL, 0x00, &ret);
+		cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x01, &ret);
+		cci_write(sensor->regmap, IMX415_TPG_PATSEL_DUOUT, val - 1, &ret);
+		cci_write(sensor->regmap, IMX415_TPG_COLORWIDTH, 0x01, &ret);
+		cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x20, &ret);
+		cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x00, &ret);
+		cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x00, &ret);
 	} else {
-		ret = imx415_write(sensor, IMX415_BLKLEVEL,
-				   IMX415_BLKLEVEL_DEFAULT);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_TPG_EN_DUOUT, 0x00);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_TESTCLKEN_MIPI, 0x00);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_DIG_CLP_MODE, 0x01);
-		if (ret)
-			return ret;
-		ret = imx415_write(sensor, IMX415_WRJ_OPEN, 0x01);
+		cci_write(sensor->regmap, IMX415_BLKLEVEL,
+				   IMX415_BLKLEVEL_DEFAULT, &ret);
+		cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x00, &ret);
+		cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x00, &ret);
+		cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x01, &ret);
+		cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x01, &ret);
 	}
 	return 0;
 }
@@ -540,7 +476,7 @@ static int imx415_s_ctrl(struct v4l2_ctrl *ctrl)
 	struct v4l2_subdev_state *state;
 	unsigned int vmax;
 	unsigned int flip;
-	int ret;
+	int ret = 0;
 
 	if (!pm_runtime_get_if_in_use(sensor->dev))
 		return 0;
@@ -553,19 +489,19 @@ static int imx415_s_ctrl(struct v4l2_ctrl *ctrl)
 		/* clamp the exposure value to VMAX. */
 		vmax = format->height + sensor->vblank->cur.val;
 		ctrl->val = min_t(int, ctrl->val, vmax);
-		ret = imx415_write(sensor, IMX415_SHR0, vmax - ctrl->val);
+		ret = cci_write(sensor->regmap, IMX415_SHR0, vmax - ctrl->val, &ret);
 		break;
 
 	case V4L2_CID_ANALOGUE_GAIN:
 		/* analogue gain in 0.3 dB step size */
-		ret = imx415_write(sensor, IMX415_GAIN_PCG_0, ctrl->val);
+		ret = cci_write(sensor->regmap, IMX415_GAIN_PCG_0, ctrl->val, &ret);
 		break;
 
 	case V4L2_CID_HFLIP:
 	case V4L2_CID_VFLIP:
 		flip = (sensor->hflip->val << IMX415_HREVERSE_SHIFT) |
 		       (sensor->vflip->val << IMX415_VREVERSE_SHIFT);
-		ret = imx415_write(sensor, IMX415_REVERSE, flip);
+		ret = cci_write(sensor->regmap, IMX415_REVERSE, flip, &ret);
 		break;
 
 	case V4L2_CID_TEST_PATTERN:
@@ -679,8 +615,6 @@ static int imx415_ctrls_init(struct imx415 *sensor)
 
 static int imx415_set_mode(struct imx415 *sensor, int mode)
 {
-	const struct imx415_reg *reg;
-	unsigned int i;
 	int ret = 0;
 
 	if (mode >= ARRAY_SIZE(supported_modes)) {
@@ -688,34 +622,29 @@ static int imx415_set_mode(struct imx415 *sensor, int mode)
 		return -EINVAL;
 	}
 
-	for (i = 0; i < supported_modes[mode].reg_list.num_of_regs; ++i) {
-		reg = &supported_modes[mode].reg_list.regs[i];
-		ret = imx415_write(sensor, reg->address, reg->val);
-		if (ret)
-			return ret;
-	}
+	cci_multi_reg_write(sensor->regmap,
+			    supported_modes[mode].reg_list.regs,
+			    supported_modes[mode].reg_list.num_of_regs,
+			    &ret);
 
-	for (i = 0; i < IMX415_NUM_CLK_PARAM_REGS; ++i) {
-		reg = &sensor->clk_params->regs[i];
-		ret = imx415_write(sensor, reg->address, reg->val);
-		if (ret)
-			return ret;
-	}
+	cci_multi_reg_write(sensor->regmap,
+			    sensor->clk_params->regs,
+			    IMX415_NUM_CLK_PARAM_REGS,
+			    &ret);
 
 	return 0;
 }
 
 static int imx415_setup(struct imx415 *sensor, struct v4l2_subdev_state *state)
 {
-	unsigned int i;
 	int ret;
 
-	for (i = 0; i < ARRAY_SIZE(imx415_init_table); ++i) {
-		ret = imx415_write(sensor, imx415_init_table[i].address,
-				   imx415_init_table[i].val);
-		if (ret)
-			return ret;
-	}
+	ret = cci_multi_reg_write(sensor->regmap,
+				  imx415_init_table,
+				  ARRAY_SIZE(imx415_init_table),
+				  NULL);
+	if (ret)
+		return ret;
 
 	return imx415_set_mode(sensor, sensor->cur_mode);
 }
@@ -724,7 +653,7 @@ static int imx415_wakeup(struct imx415 *sensor)
 {
 	int ret;
 
-	ret = imx415_write(sensor, IMX415_MODE, IMX415_MODE_OPERATING);
+	ret = cci_write(sensor->regmap, IMX415_MODE, IMX415_MODE_OPERATING, NULL);
 	if (ret)
 		return ret;
 
@@ -743,21 +672,15 @@ static int imx415_stream_on(struct imx415 *sensor)
 	int ret;
 
 	ret = imx415_wakeup(sensor);
-	if (ret)
-		return ret;
-
-	return imx415_write(sensor, IMX415_XMSTA, IMX415_XMSTA_START);
+	return cci_write(sensor->regmap, IMX415_XMSTA, IMX415_XMSTA_START, &ret);
 }
 
 static int imx415_stream_off(struct imx415 *sensor)
 {
 	int ret;
 
-	ret = imx415_write(sensor, IMX415_XMSTA, IMX415_XMSTA_STOP);
-	if (ret)
-		return ret;
-
-	return imx415_write(sensor, IMX415_MODE, IMX415_MODE_STANDBY);
+	ret = cci_write(sensor->regmap, IMX415_XMSTA, IMX415_XMSTA_STOP, NULL);
+	return cci_write(sensor->regmap, IMX415_MODE, IMX415_MODE_STANDBY, &ret);
 }
 
 static int imx415_s_stream(struct v4l2_subdev *sd, int enable)
@@ -988,6 +911,7 @@ static void imx415_power_off(struct imx415 *sensor)
 static int imx415_identify_model(struct imx415 *sensor)
 {
 	int model, ret;
+	u64 chip_id;
 
 	/*
 	 * While most registers can be read when the sensor is in standby, this
@@ -998,7 +922,7 @@ static int imx415_identify_model(struct imx415 *sensor)
 		return dev_err_probe(sensor->dev, ret,
 				     "failed to get sensor out of standby\n");
 
-	ret = imx415_read(sensor, IMX415_SENSOR_INFO);
+	ret = cci_read(sensor->regmap, IMX415_SENSOR_INFO, &chip_id, NULL);
 	if (ret < 0) {
 		dev_err_probe(sensor->dev, ret,
 			      "failed to read sensor information\n");
@@ -1020,7 +944,7 @@ static int imx415_identify_model(struct imx415 *sensor)
 	ret = 0;
 
 done:
-	imx415_write(sensor, IMX415_MODE, IMX415_MODE_STANDBY);
+	cci_write(sensor->regmap, IMX415_MODE, IMX415_MODE_STANDBY, &ret);
 	return ret;
 }
 
@@ -1169,7 +1093,7 @@ static int imx415_probe(struct i2c_client *client)
 	if (ret)
 		return ret;
 
-	sensor->regmap = devm_regmap_init_i2c(client, &imx415_regmap_config);
+	sensor->regmap = devm_cci_regmap_init_i2c(client, 16);
 	if (IS_ERR(sensor->regmap))
 		return PTR_ERR(sensor->regmap);
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 2/3] media: i2c: imx415: Add more clock configurations
  2023-12-05  9:05 [PATCH 0/3] media: imx415: Add more modes Alexander Stein
  2023-12-05  9:05 ` [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers Alexander Stein
@ 2023-12-05  9:05 ` Alexander Stein
  2023-12-12 11:37   ` Sakari Ailus
  2023-12-05  9:05 ` [PATCH 3/3] media: i2c: imx415: Add more supported modes Alexander Stein
  2 siblings, 1 reply; 15+ messages in thread
From: Alexander Stein @ 2023-12-05  9:05 UTC (permalink / raw)
  To: Mauro Carvalho Chehab, Michael Riesch, Sakari Ailus,
	Laurent Pinchart, Gerald Loacker
  Cc: Alexander Stein, linux-media

Complete the list from "INCK Setting" section in IMX415-AAQR-C
(Rev. E19504, 2019/05/21)

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 drivers/media/i2c/imx415.c | 255 +++++++++++++++++++++++++++++++++++++
 1 file changed, 255 insertions(+)

diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
index bb1a779defab..a222b9134aa2 100644
--- a/drivers/media/i2c/imx415.c
+++ b/drivers/media/i2c/imx415.c
@@ -128,6 +128,36 @@ static const struct imx415_clk_params imx415_clk_params[] = {
 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
 	},
+	{
+		.lane_rate = 594000000,
+		.inck = 37125000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
+		.regs[2] = { IMX415_SYS_MODE, 0x7 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x24 },
+		.regs[5] = { IMX415_INCKSEL3, 0x080 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x24 },
+		.regs[8] = { IMX415_INCKSEL6, 0x0 },
+		.regs[9] = { IMX415_INCKSEL7, 0x1 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0984 },
+	},
+	{
+		.lane_rate = 594000000,
+		.inck = 74250000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
+		.regs[2] = { IMX415_SYS_MODE, 0x7 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x28 },
+		.regs[5] = { IMX415_INCKSEL3, 0x080 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x28 },
+		.regs[8] = { IMX415_INCKSEL6, 0x0 },
+		.regs[9] = { IMX415_INCKSEL7, 0x1 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
+	},
 	{
 		.lane_rate = 720000000,
 		.inck = 24000000,
@@ -143,6 +173,21 @@ static const struct imx415_clk_params imx415_clk_params[] = {
 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
 	},
+	{
+		.lane_rate = 720000000,
+		.inck = 72000000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
+		.regs[2] = { IMX415_SYS_MODE, 0x9 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x28 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x28 },
+		.regs[8] = { IMX415_INCKSEL6, 0x0 },
+		.regs[9] = { IMX415_INCKSEL7, 0x1 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
+	},
 	{
 		.lane_rate = 891000000,
 		.inck = 27000000,
@@ -158,6 +203,36 @@ static const struct imx415_clk_params imx415_clk_params[] = {
 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
 	},
+	{
+		.lane_rate = 891000000,
+		.inck = 37125000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
+		.regs[2] = { IMX415_SYS_MODE, 0x5 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x24 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x24 },
+		.regs[8] = { IMX415_INCKSEL6, 0x0 },
+		.regs[9] = { IMX415_INCKSEL7, 0x1 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
+	},
+	{
+		.lane_rate = 891000000,
+		.inck = 74250000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
+		.regs[2] = { IMX415_SYS_MODE, 0x5 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x28 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x28 },
+		.regs[8] = { IMX415_INCKSEL6, 0x0 },
+		.regs[9] = { IMX415_INCKSEL7, 0x1 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
+	},
 	{
 		.lane_rate = 1440000000,
 		.inck = 24000000,
@@ -173,6 +248,21 @@ static const struct imx415_clk_params imx415_clk_params[] = {
 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
 	},
+	{
+		.lane_rate = 1440000000,
+		.inck = 72000000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
+		.regs[2] = { IMX415_SYS_MODE, 0x8 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x28 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x28 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
+	},
 	{
 		.lane_rate = 1485000000,
 		.inck = 27000000,
@@ -188,6 +278,171 @@ static const struct imx415_clk_params imx415_clk_params[] = {
 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
 	},
+	{
+		.lane_rate = 1485000000,
+		.inck = 37125000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
+		.regs[2] = { IMX415_SYS_MODE, 0x8 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x24 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x24 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
+	},
+	{
+		.lane_rate = 1485000000,
+		.inck = 74250000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
+		.regs[2] = { IMX415_SYS_MODE, 0x8 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x28 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x28 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
+	},
+	{
+		.lane_rate = 1782000000,
+		.inck = 27000000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
+		.regs[2] = { IMX415_SYS_MODE, 0x4 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x23 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
+		.regs[7] = { IMX415_INCKSEL5, 0x23 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
+	},
+	{
+		.lane_rate = 1782000000,
+		.inck = 37125000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
+		.regs[2] = { IMX415_SYS_MODE, 0x4 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x24 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x24 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
+	},
+	{
+		.lane_rate = 1782000000,
+		.inck = 74250000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
+		.regs[2] = { IMX415_SYS_MODE, 0x4 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x28 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x28 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
+	},
+	{
+		.lane_rate = 2079000000,
+		.inck = 27000000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
+		.regs[2] = { IMX415_SYS_MODE, 0x2 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x23 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0E7 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
+		.regs[7] = { IMX415_INCKSEL5, 0x23 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
+	},
+	{
+		.lane_rate = 2079000000,
+		.inck = 37125000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
+		.regs[2] = { IMX415_SYS_MODE, 0x2 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x24 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x24 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
+	},
+	{
+		.lane_rate = 2079000000,
+		.inck = 74250000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
+		.regs[2] = { IMX415_SYS_MODE, 0x2 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x28 },
+		.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x28 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
+	},
+	{
+		.lane_rate = 2376000000,
+		.inck = 27000000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
+		.regs[2] = { IMX415_SYS_MODE, 0x0 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x23 },
+		.regs[5] = { IMX415_INCKSEL3, 0x108 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
+		.regs[7] = { IMX415_INCKSEL5, 0x23 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
+	},
+	{
+		.lane_rate = 2376000000,
+		.inck = 37125000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
+		.regs[2] = { IMX415_SYS_MODE, 0x0 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x24 },
+		.regs[5] = { IMX415_INCKSEL3, 0x100 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x24 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
+	},
+	{
+		.lane_rate = 2376000000,
+		.inck = 74250000,
+		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
+		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
+		.regs[2] = { IMX415_SYS_MODE, 0x0 },
+		.regs[3] = { IMX415_INCKSEL1, 0x00 },
+		.regs[4] = { IMX415_INCKSEL2, 0x28 },
+		.regs[5] = { IMX415_INCKSEL3, 0x100 },
+		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
+		.regs[7] = { IMX415_INCKSEL5, 0x28 },
+		.regs[8] = { IMX415_INCKSEL6, 0x1 },
+		.regs[9] = { IMX415_INCKSEL7, 0x0 },
+		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
+	},
 };
 
 /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH 3/3] media: i2c: imx415: Add more supported modes
  2023-12-05  9:05 [PATCH 0/3] media: imx415: Add more modes Alexander Stein
  2023-12-05  9:05 ` [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers Alexander Stein
  2023-12-05  9:05 ` [PATCH 2/3] media: i2c: imx415: Add more clock configurations Alexander Stein
@ 2023-12-05  9:05 ` Alexander Stein
  2023-12-05 10:45   ` Laurent Pinchart
  2 siblings, 1 reply; 15+ messages in thread
From: Alexander Stein @ 2023-12-05  9:05 UTC (permalink / raw)
  To: Mauro Carvalho Chehab, Michael Riesch, Sakari Ailus,
	Laurent Pinchart, Gerald Loacker
  Cc: Alexander Stein, linux-media

These modes are listed in section "All-pixel mode" of the datasheet
IMX415-AAQR-C (Rev. E19504, 2019/05/21).
hmax_pix and pixel_rate are taken from the comment above the mode list.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
 drivers/media/i2c/imx415.c | 362 +++++++++++++++++++++++++++++++++++++
 1 file changed, 362 insertions(+)

diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
index a222b9134aa2..48b8ae6d790d 100644
--- a/drivers/media/i2c/imx415.c
+++ b/drivers/media/i2c/imx415.c
@@ -445,6 +445,38 @@ static const struct imx415_clk_params imx415_clk_params[] = {
 	},
 };
 
+/* all-pixel 2-lane 594 Mbps 10 Hz mode */
+static const struct cci_reg_sequence imx415_mode_2_594[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0CE4 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
+	{ IMX415_TCLKPOST, 0x0067 },
+	{ IMX415_TCLKPREPARE, 0x0027 },
+	{ IMX415_TCLKTRAIL, 0x0027 },
+	{ IMX415_TCLKZERO, 0x00B7 },
+	{ IMX415_THSPREPARE, 0x002F },
+	{ IMX415_THSZERO, 0x004F },
+	{ IMX415_THSTRAIL, 0x002F },
+	{ IMX415_THSEXIT, 0x0047 },
+	{ IMX415_TLPX, 0x0027 },
+};
+
+/* all-pixel 2-lane 891 Mbps 15 Hz mode */
+static const struct cci_reg_sequence imx415_mode_2_891[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0898 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
+	{ IMX415_TCLKPOST, 0x007F },
+	{ IMX415_TCLKPREPARE, 0x0037 },
+	{ IMX415_TCLKTRAIL, 0x0037 },
+	{ IMX415_TCLKZERO, 0x00F7 },
+	{ IMX415_THSPREPARE, 0x003F },
+	{ IMX415_THSZERO, 0x006F },
+	{ IMX415_THSTRAIL, 0x003F },
+	{ IMX415_THSEXIT, 0x005F },
+	{ IMX415_TLPX, 0x002F },
+};
+
 /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
 static const struct cci_reg_sequence imx415_mode_2_720[] = {
 	{ IMX415_VMAX, 0x08CA },
@@ -461,6 +493,38 @@ static const struct cci_reg_sequence imx415_mode_2_720[] = {
 	{ IMX415_TLPX, 0x0027 },
 };
 
+/* all-pixel 2-lane 1782 Mbps 30 Hz mode */
+static const struct cci_reg_sequence imx415_mode_2_1782[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x044C },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
+	{ IMX415_TCLKPOST, 0x00B7 },
+	{ IMX415_TCLKPREPARE, 0x0067 },
+	{ IMX415_TCLKTRAIL, 0x006F },
+	{ IMX415_TCLKZERO, 0x01DF },
+	{ IMX415_THSPREPARE, 0x006F },
+	{ IMX415_THSZERO, 0x00CF },
+	{ IMX415_THSTRAIL, 0x006F },
+	{ IMX415_THSEXIT, 0x00B7 },
+	{ IMX415_TLPX, 0x005F },
+};
+
+/* all-pixel 2-lane 2079 Mbps 30 Hz mode */
+static const struct cci_reg_sequence imx415_mode_2_2079[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x044C },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
+	{ IMX415_TCLKPOST, 0x00D7 },
+	{ IMX415_TCLKPREPARE, 0x007F },
+	{ IMX415_TCLKTRAIL, 0x007F },
+	{ IMX415_TCLKZERO, 0x0237 },
+	{ IMX415_THSPREPARE, 0x0087 },
+	{ IMX415_THSZERO, 0x00EF },
+	{ IMX415_THSTRAIL, 0x0087 },
+	{ IMX415_THSEXIT, 0x00DF },
+	{ IMX415_TLPX, 0x006F },
+};
+
 /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
 static const struct cci_reg_sequence imx415_mode_2_1440[] = {
 	{ IMX415_VMAX, 0x08CA },
@@ -477,6 +541,70 @@ static const struct cci_reg_sequence imx415_mode_2_1440[] = {
 	{ IMX415_TLPX, 0x004F },
 };
 
+/* all-pixel 4-lane 594 Mbps 20 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_594_20fps[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0672 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x0067 },
+	{ IMX415_TCLKPREPARE, 0x0027 },
+	{ IMX415_TCLKTRAIL, 0x0027 },
+	{ IMX415_TCLKZERO, 0x00B7 },
+	{ IMX415_THSPREPARE, 0x002F },
+	{ IMX415_THSZERO, 0x004F },
+	{ IMX415_THSTRAIL, 0x002F },
+	{ IMX415_THSEXIT, 0x0047 },
+	{ IMX415_TLPX, 0x0027 },
+};
+
+/* all-pixel 4-lane 594 Mbps 25 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_594_25fps[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0528 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x0067 },
+	{ IMX415_TCLKPREPARE, 0x0027 },
+	{ IMX415_TCLKTRAIL, 0x0027 },
+	{ IMX415_TCLKZERO, 0x00B7 },
+	{ IMX415_THSPREPARE, 0x002F },
+	{ IMX415_THSZERO, 0x004F },
+	{ IMX415_THSTRAIL, 0x002F },
+	{ IMX415_THSEXIT, 0x0047 },
+	{ IMX415_TLPX, 0x0027 },
+};
+
+/* all-pixel 4-lane 720 Mbps 25 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_720_25fps[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0500 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x006F },
+	{ IMX415_TCLKPREPARE, 0x002F },
+	{ IMX415_TCLKTRAIL, 0x002F },
+	{ IMX415_TCLKZERO, 0x00BF },
+	{ IMX415_THSPREPARE, 0x002F },
+	{ IMX415_THSZERO, 0x0057 },
+	{ IMX415_THSTRAIL, 0x002F },
+	{ IMX415_THSEXIT, 0x004F },
+	{ IMX415_TLPX, 0x0027 },
+};
+
+/* all-pixel 4-lane 720 Mbps 30.01 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_720_30fps[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x042A },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x006F },
+	{ IMX415_TCLKPREPARE, 0x002F },
+	{ IMX415_TCLKTRAIL, 0x002F },
+	{ IMX415_TCLKZERO, 0x00BF },
+	{ IMX415_THSPREPARE, 0x002F },
+	{ IMX415_THSZERO, 0x0057 },
+	{ IMX415_THSTRAIL, 0x002F },
+	{ IMX415_THSEXIT, 0x004F },
+	{ IMX415_TLPX, 0x0027 },
+};
+
 /* all-pixel 4-lane 891 Mbps 30 Hz mode */
 static const struct cci_reg_sequence imx415_mode_4_891[] = {
 	{ IMX415_VMAX, 0x08CA },
@@ -493,6 +621,102 @@ static const struct cci_reg_sequence imx415_mode_4_891[] = {
 	{ IMX415_TLPX, 0x002F },
 };
 
+/* all-pixel 4-lane 1440 Mbps 30.01 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_1440_30fps[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x042A },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x009F },
+	{ IMX415_TCLKPREPARE, 0x0057 },
+	{ IMX415_TCLKTRAIL, 0x0057 },
+	{ IMX415_TCLKZERO, 0x0187 },
+	{ IMX415_THSPREPARE, 0x005F },
+	{ IMX415_THSZERO, 0x00A7 },
+	{ IMX415_THSTRAIL, 0x005F },
+	{ IMX415_THSEXIT, 0x0097 },
+	{ IMX415_TLPX, 0x004F },
+};
+
+/* all-pixel 4-lane 1440 Mbps 60.03 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_1440_60fps[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0215 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x009F },
+	{ IMX415_TCLKPREPARE, 0x0057 },
+	{ IMX415_TCLKTRAIL, 0x0057 },
+	{ IMX415_TCLKZERO, 0x0187 },
+	{ IMX415_THSPREPARE, 0x005F },
+	{ IMX415_THSZERO, 0x00A7 },
+	{ IMX415_THSTRAIL, 0x005F },
+	{ IMX415_THSEXIT, 0x0097 },
+	{ IMX415_TLPX, 0x004F },
+};
+
+/* all-pixel 4-lane 1485 Mbps 60 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_1485[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0226 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x00A7 },
+	{ IMX415_TCLKPREPARE, 0x0057 },
+	{ IMX415_TCLKTRAIL, 0x005F },
+	{ IMX415_TCLKZERO, 0x0197 },
+	{ IMX415_THSPREPARE, 0x005F },
+	{ IMX415_THSZERO, 0x00AF },
+	{ IMX415_THSTRAIL, 0x005F },
+	{ IMX415_THSEXIT, 0x009F },
+	{ IMX415_TLPX, 0x004F },
+};
+
+/* all-pixel 4-lane 1782 Mbps 60 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_1782[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0226 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x00B7 },
+	{ IMX415_TCLKPREPARE, 0x0067 },
+	{ IMX415_TCLKTRAIL, 0x006F },
+	{ IMX415_TCLKZERO, 0x01DF },
+	{ IMX415_THSPREPARE, 0x006F },
+	{ IMX415_THSZERO, 0x00CF },
+	{ IMX415_THSTRAIL, 0x006F },
+	{ IMX415_THSEXIT, 0x00B7 },
+	{ IMX415_TLPX, 0x005F },
+};
+
+/* all-pixel 4-lane 2079 Mbps 60 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_2079[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x0226 },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x00D7 },
+	{ IMX415_TCLKPREPARE, 0x007F },
+	{ IMX415_TCLKTRAIL, 0x007F },
+	{ IMX415_TCLKZERO, 0x0237 },
+	{ IMX415_THSPREPARE, 0x0087 },
+	{ IMX415_THSZERO, 0x00EF },
+	{ IMX415_THSTRAIL, 0x0087 },
+	{ IMX415_THSEXIT, 0x00DF },
+	{ IMX415_TLPX, 0x006F },
+};
+
+/* all-pixel 4-lane 2376 Mbps 60 Hz mode */
+static const struct cci_reg_sequence imx415_mode_4_2376[] = {
+	{ IMX415_VMAX, 0x08CA },
+	{ IMX415_HMAX, 0x016E },
+	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
+	{ IMX415_TCLKPOST, 0x00E7 },
+	{ IMX415_TCLKPREPARE, 0x008F },
+	{ IMX415_TCLKTRAIL, 0x008F },
+	{ IMX415_TCLKZERO, 0x027F },
+	{ IMX415_THSPREPARE, 0x0097 },
+	{ IMX415_THSZERO, 0x010F },
+	{ IMX415_THSTRAIL, 0x0097 },
+	{ IMX415_THSEXIT, 0x00F7 },
+	{ IMX415_TLPX, 0x007F },
+};
+
 struct imx415_mode_reg_list {
 	u32 num_of_regs;
 	const struct cci_reg_sequence *regs;
@@ -536,6 +760,26 @@ struct imx415_mode {
 
 /* mode configs */
 static const struct imx415_mode supported_modes[] = {
+	{
+		.lane_rate = 594000000,
+		.lanes = 2,
+		.hmax_pix = 4400,
+		.pixel_rate = 99000000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_2_594),
+			.regs = imx415_mode_2_594,
+		},
+	},
+	{
+		.lane_rate = 891000000,
+		.lanes = 2,
+		.hmax_pix = 4400,
+		.pixel_rate = 148500000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_2_891),
+			.regs = imx415_mode_2_891,
+		},
+	},
 	{
 		.lane_rate = 720000000,
 		.lanes = 2,
@@ -547,6 +791,24 @@ static const struct imx415_mode supported_modes[] = {
 		},
 	},
 	{
+		.lane_rate = 1782000000,
+		.lanes = 2,
+		.hmax_pix = 4400,
+		.pixel_rate = 297000000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_2_1782),
+			.regs = imx415_mode_2_1782,
+		},
+	},	{
+		.lane_rate = 2079000000,
+		.lanes = 2,
+		.hmax_pix = 4400,
+		.pixel_rate = 304615385,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_2_2079),
+			.regs = imx415_mode_2_2079,
+		},
+	},	{
 		.lane_rate = 1440000000,
 		.lanes = 2,
 		.hmax_pix = 4510,
@@ -556,6 +818,46 @@ static const struct imx415_mode supported_modes[] = {
 			.regs = imx415_mode_2_1440,
 		},
 	},
+	{
+		.lane_rate = 594000000,
+		.lanes = 4,
+		.hmax_pix = 5500,
+		.pixel_rate = 247500000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_594_20fps),
+			.regs = imx415_mode_4_594_20fps,
+		},
+	},
+	{
+		.lane_rate = 594000000,
+		.lanes = 4,
+		.hmax_pix = 4400,
+		.pixel_rate = 247500000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_594_25fps),
+			.regs = imx415_mode_4_594_25fps,
+		},
+	},
+	{
+		.lane_rate = 720000000,
+		.lanes = 4,
+		.hmax_pix = 4400,
+		.pixel_rate = 247500000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_720_25fps),
+			.regs = imx415_mode_4_720_25fps,
+		},
+	},
+	{
+		.lane_rate = 720000000,
+		.lanes = 4,
+		.hmax_pix = 4510,
+		.pixel_rate = 304615385,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_720_30fps),
+			.regs = imx415_mode_4_720_30fps,
+		},
+	},
 	{
 		.lane_rate = 891000000,
 		.lanes = 4,
@@ -566,6 +868,66 @@ static const struct imx415_mode supported_modes[] = {
 			.regs = imx415_mode_4_891,
 		},
 	},
+	{
+		.lane_rate = 1440000000,
+		.lanes = 4,
+		.hmax_pix = 4510,
+		.pixel_rate = 304615385,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1440_30fps),
+			.regs = imx415_mode_4_1440_30fps,
+		},
+	},
+	{
+		.lane_rate = 1440000000,
+		.lanes = 4,
+		.hmax_pix = 4510,
+		.pixel_rate = 609230769,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1440_60fps),
+			.regs = imx415_mode_4_1440_60fps,
+		},
+	},
+	{
+		.lane_rate = 1485000000,
+		.lanes = 4,
+		.hmax_pix = 4400,
+		.pixel_rate = 594000000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1485),
+			.regs = imx415_mode_4_1485,
+		},
+	},
+	{
+		.lane_rate = 1782000000,
+		.lanes = 4,
+		.hmax_pix = 4400,
+		.pixel_rate = 594000000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1782),
+			.regs = imx415_mode_4_1782,
+		},
+	},
+	{
+		.lane_rate = 2079000000,
+		.lanes = 4,
+		.hmax_pix = 4400,
+		.pixel_rate = 594000000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2079),
+			.regs = imx415_mode_4_2079,
+		},
+	},
+	{
+		.lane_rate = 12376000000,
+		.lanes = 4,
+		.hmax_pix = 4392,
+		.pixel_rate = 891000000,
+		.reg_list = {
+			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2376),
+			.regs = imx415_mode_4_2376,
+		},
+	},
 };
 
 static const char *const imx415_test_pattern_menu[] = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [PATCH 3/3] media: i2c: imx415: Add more supported modes
  2023-12-05  9:05 ` [PATCH 3/3] media: i2c: imx415: Add more supported modes Alexander Stein
@ 2023-12-05 10:45   ` Laurent Pinchart
  2023-12-05 11:12     ` Alexander Stein
  0 siblings, 1 reply; 15+ messages in thread
From: Laurent Pinchart @ 2023-12-05 10:45 UTC (permalink / raw)
  To: Alexander Stein
  Cc: Mauro Carvalho Chehab, Michael Riesch, Sakari Ailus,
	Gerald Loacker, linux-media

Hi Alexander,

Thank you for the patch.

On Tue, Dec 05, 2023 at 10:05:57AM +0100, Alexander Stein wrote:
> These modes are listed in section "All-pixel mode" of the datasheet
> IMX415-AAQR-C (Rev. E19504, 2019/05/21).
> hmax_pix and pixel_rate are taken from the comment above the mode list.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  drivers/media/i2c/imx415.c | 362 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 362 insertions(+)
> 
> diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
> index a222b9134aa2..48b8ae6d790d 100644
> --- a/drivers/media/i2c/imx415.c
> +++ b/drivers/media/i2c/imx415.c
> @@ -445,6 +445,38 @@ static const struct imx415_clk_params imx415_clk_params[] = {
>  	},
>  };
>  
> +/* all-pixel 2-lane 594 Mbps 10 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_2_594[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0CE4 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> +	{ IMX415_TCLKPOST, 0x0067 },
> +	{ IMX415_TCLKPREPARE, 0x0027 },
> +	{ IMX415_TCLKTRAIL, 0x0027 },
> +	{ IMX415_TCLKZERO, 0x00B7 },
> +	{ IMX415_THSPREPARE, 0x002F },
> +	{ IMX415_THSZERO, 0x004F },
> +	{ IMX415_THSTRAIL, 0x002F },
> +	{ IMX415_THSEXIT, 0x0047 },
> +	{ IMX415_TLPX, 0x0027 },
> +};
> +
> +/* all-pixel 2-lane 891 Mbps 15 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_2_891[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0898 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> +	{ IMX415_TCLKPOST, 0x007F },
> +	{ IMX415_TCLKPREPARE, 0x0037 },
> +	{ IMX415_TCLKTRAIL, 0x0037 },
> +	{ IMX415_TCLKZERO, 0x00F7 },
> +	{ IMX415_THSPREPARE, 0x003F },
> +	{ IMX415_THSZERO, 0x006F },
> +	{ IMX415_THSTRAIL, 0x003F },
> +	{ IMX415_THSEXIT, 0x005F },
> +	{ IMX415_TLPX, 0x002F },
> +};
> +
>  /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
>  static const struct cci_reg_sequence imx415_mode_2_720[] = {
>  	{ IMX415_VMAX, 0x08CA },
> @@ -461,6 +493,38 @@ static const struct cci_reg_sequence imx415_mode_2_720[] = {
>  	{ IMX415_TLPX, 0x0027 },
>  };
>  
> +/* all-pixel 2-lane 1782 Mbps 30 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_2_1782[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x044C },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> +	{ IMX415_TCLKPOST, 0x00B7 },
> +	{ IMX415_TCLKPREPARE, 0x0067 },
> +	{ IMX415_TCLKTRAIL, 0x006F },
> +	{ IMX415_TCLKZERO, 0x01DF },
> +	{ IMX415_THSPREPARE, 0x006F },
> +	{ IMX415_THSZERO, 0x00CF },
> +	{ IMX415_THSTRAIL, 0x006F },
> +	{ IMX415_THSEXIT, 0x00B7 },
> +	{ IMX415_TLPX, 0x005F },
> +};
> +
> +/* all-pixel 2-lane 2079 Mbps 30 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_2_2079[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x044C },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> +	{ IMX415_TCLKPOST, 0x00D7 },
> +	{ IMX415_TCLKPREPARE, 0x007F },
> +	{ IMX415_TCLKTRAIL, 0x007F },
> +	{ IMX415_TCLKZERO, 0x0237 },
> +	{ IMX415_THSPREPARE, 0x0087 },
> +	{ IMX415_THSZERO, 0x00EF },
> +	{ IMX415_THSTRAIL, 0x0087 },
> +	{ IMX415_THSEXIT, 0x00DF },
> +	{ IMX415_TLPX, 0x006F },
> +};
> +
>  /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
>  static const struct cci_reg_sequence imx415_mode_2_1440[] = {
>  	{ IMX415_VMAX, 0x08CA },
> @@ -477,6 +541,70 @@ static const struct cci_reg_sequence imx415_mode_2_1440[] = {
>  	{ IMX415_TLPX, 0x004F },
>  };
>  
> +/* all-pixel 4-lane 594 Mbps 20 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_594_20fps[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0672 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x0067 },
> +	{ IMX415_TCLKPREPARE, 0x0027 },
> +	{ IMX415_TCLKTRAIL, 0x0027 },
> +	{ IMX415_TCLKZERO, 0x00B7 },
> +	{ IMX415_THSPREPARE, 0x002F },
> +	{ IMX415_THSZERO, 0x004F },
> +	{ IMX415_THSTRAIL, 0x002F },
> +	{ IMX415_THSEXIT, 0x0047 },
> +	{ IMX415_TLPX, 0x0027 },
> +};
> +
> +/* all-pixel 4-lane 594 Mbps 25 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_594_25fps[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0528 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x0067 },
> +	{ IMX415_TCLKPREPARE, 0x0027 },
> +	{ IMX415_TCLKTRAIL, 0x0027 },
> +	{ IMX415_TCLKZERO, 0x00B7 },
> +	{ IMX415_THSPREPARE, 0x002F },
> +	{ IMX415_THSZERO, 0x004F },
> +	{ IMX415_THSTRAIL, 0x002F },
> +	{ IMX415_THSEXIT, 0x0047 },
> +	{ IMX415_TLPX, 0x0027 },
> +};
> +
> +/* all-pixel 4-lane 720 Mbps 25 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_720_25fps[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0500 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x006F },
> +	{ IMX415_TCLKPREPARE, 0x002F },
> +	{ IMX415_TCLKTRAIL, 0x002F },
> +	{ IMX415_TCLKZERO, 0x00BF },
> +	{ IMX415_THSPREPARE, 0x002F },
> +	{ IMX415_THSZERO, 0x0057 },
> +	{ IMX415_THSTRAIL, 0x002F },
> +	{ IMX415_THSEXIT, 0x004F },
> +	{ IMX415_TLPX, 0x0027 },
> +};
> +
> +/* all-pixel 4-lane 720 Mbps 30.01 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_720_30fps[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x042A },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x006F },
> +	{ IMX415_TCLKPREPARE, 0x002F },
> +	{ IMX415_TCLKTRAIL, 0x002F },
> +	{ IMX415_TCLKZERO, 0x00BF },
> +	{ IMX415_THSPREPARE, 0x002F },
> +	{ IMX415_THSZERO, 0x0057 },
> +	{ IMX415_THSTRAIL, 0x002F },
> +	{ IMX415_THSEXIT, 0x004F },
> +	{ IMX415_TLPX, 0x0027 },
> +};
> +
>  /* all-pixel 4-lane 891 Mbps 30 Hz mode */
>  static const struct cci_reg_sequence imx415_mode_4_891[] = {
>  	{ IMX415_VMAX, 0x08CA },
> @@ -493,6 +621,102 @@ static const struct cci_reg_sequence imx415_mode_4_891[] = {
>  	{ IMX415_TLPX, 0x002F },
>  };
>  
> +/* all-pixel 4-lane 1440 Mbps 30.01 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_1440_30fps[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x042A },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x009F },
> +	{ IMX415_TCLKPREPARE, 0x0057 },
> +	{ IMX415_TCLKTRAIL, 0x0057 },
> +	{ IMX415_TCLKZERO, 0x0187 },
> +	{ IMX415_THSPREPARE, 0x005F },
> +	{ IMX415_THSZERO, 0x00A7 },
> +	{ IMX415_THSTRAIL, 0x005F },
> +	{ IMX415_THSEXIT, 0x0097 },
> +	{ IMX415_TLPX, 0x004F },
> +};
> +
> +/* all-pixel 4-lane 1440 Mbps 60.03 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_1440_60fps[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0215 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x009F },
> +	{ IMX415_TCLKPREPARE, 0x0057 },
> +	{ IMX415_TCLKTRAIL, 0x0057 },
> +	{ IMX415_TCLKZERO, 0x0187 },
> +	{ IMX415_THSPREPARE, 0x005F },
> +	{ IMX415_THSZERO, 0x00A7 },
> +	{ IMX415_THSTRAIL, 0x005F },
> +	{ IMX415_THSEXIT, 0x0097 },
> +	{ IMX415_TLPX, 0x004F },
> +};
> +
> +/* all-pixel 4-lane 1485 Mbps 60 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_1485[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0226 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x00A7 },
> +	{ IMX415_TCLKPREPARE, 0x0057 },
> +	{ IMX415_TCLKTRAIL, 0x005F },
> +	{ IMX415_TCLKZERO, 0x0197 },
> +	{ IMX415_THSPREPARE, 0x005F },
> +	{ IMX415_THSZERO, 0x00AF },
> +	{ IMX415_THSTRAIL, 0x005F },
> +	{ IMX415_THSEXIT, 0x009F },
> +	{ IMX415_TLPX, 0x004F },
> +};
> +
> +/* all-pixel 4-lane 1782 Mbps 60 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_1782[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0226 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x00B7 },
> +	{ IMX415_TCLKPREPARE, 0x0067 },
> +	{ IMX415_TCLKTRAIL, 0x006F },
> +	{ IMX415_TCLKZERO, 0x01DF },
> +	{ IMX415_THSPREPARE, 0x006F },
> +	{ IMX415_THSZERO, 0x00CF },
> +	{ IMX415_THSTRAIL, 0x006F },
> +	{ IMX415_THSEXIT, 0x00B7 },
> +	{ IMX415_TLPX, 0x005F },
> +};
> +
> +/* all-pixel 4-lane 2079 Mbps 60 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_2079[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x0226 },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x00D7 },
> +	{ IMX415_TCLKPREPARE, 0x007F },
> +	{ IMX415_TCLKTRAIL, 0x007F },
> +	{ IMX415_TCLKZERO, 0x0237 },
> +	{ IMX415_THSPREPARE, 0x0087 },
> +	{ IMX415_THSZERO, 0x00EF },
> +	{ IMX415_THSTRAIL, 0x0087 },
> +	{ IMX415_THSEXIT, 0x00DF },
> +	{ IMX415_TLPX, 0x006F },
> +};
> +
> +/* all-pixel 4-lane 2376 Mbps 60 Hz mode */
> +static const struct cci_reg_sequence imx415_mode_4_2376[] = {
> +	{ IMX415_VMAX, 0x08CA },
> +	{ IMX415_HMAX, 0x016E },
> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> +	{ IMX415_TCLKPOST, 0x00E7 },
> +	{ IMX415_TCLKPREPARE, 0x008F },
> +	{ IMX415_TCLKTRAIL, 0x008F },
> +	{ IMX415_TCLKZERO, 0x027F },
> +	{ IMX415_THSPREPARE, 0x0097 },
> +	{ IMX415_THSZERO, 0x010F },
> +	{ IMX415_THSTRAIL, 0x0097 },
> +	{ IMX415_THSEXIT, 0x00F7 },
> +	{ IMX415_TLPX, 0x007F },
> +};
> +
>  struct imx415_mode_reg_list {
>  	u32 num_of_regs;
>  	const struct cci_reg_sequence *regs;
> @@ -536,6 +760,26 @@ struct imx415_mode {
>  
>  /* mode configs */
>  static const struct imx415_mode supported_modes[] = {
> +	{
> +		.lane_rate = 594000000,
> +		.lanes = 2,
> +		.hmax_pix = 4400,
> +		.pixel_rate = 99000000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_594),
> +			.regs = imx415_mode_2_594,
> +		},
> +	},
> +	{
> +		.lane_rate = 891000000,
> +		.lanes = 2,
> +		.hmax_pix = 4400,
> +		.pixel_rate = 148500000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_891),
> +			.regs = imx415_mode_2_891,
> +		},
> +	},
>  	{
>  		.lane_rate = 720000000,
>  		.lanes = 2,
> @@ -547,6 +791,24 @@ static const struct imx415_mode supported_modes[] = {
>  		},
>  	},
>  	{
> +		.lane_rate = 1782000000,
> +		.lanes = 2,
> +		.hmax_pix = 4400,
> +		.pixel_rate = 297000000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_1782),
> +			.regs = imx415_mode_2_1782,
> +		},
> +	},	{
> +		.lane_rate = 2079000000,
> +		.lanes = 2,
> +		.hmax_pix = 4400,
> +		.pixel_rate = 304615385,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_2079),
> +			.regs = imx415_mode_2_2079,
> +		},
> +	},	{
>  		.lane_rate = 1440000000,
>  		.lanes = 2,
>  		.hmax_pix = 4510,
> @@ -556,6 +818,46 @@ static const struct imx415_mode supported_modes[] = {
>  			.regs = imx415_mode_2_1440,
>  		},
>  	},
> +	{
> +		.lane_rate = 594000000,
> +		.lanes = 4,
> +		.hmax_pix = 5500,
> +		.pixel_rate = 247500000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_594_20fps),
> +			.regs = imx415_mode_4_594_20fps,
> +		},
> +	},
> +	{
> +		.lane_rate = 594000000,
> +		.lanes = 4,

The mode is selected from the number of data lanes and the lane rate.
They're the same as the previous entry, so this entry will never be
selected. Same below.

> +		.hmax_pix = 4400,
> +		.pixel_rate = 247500000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_594_25fps),
> +			.regs = imx415_mode_4_594_25fps,
> +		},
> +	},
> +	{
> +		.lane_rate = 720000000,
> +		.lanes = 4,
> +		.hmax_pix = 4400,
> +		.pixel_rate = 247500000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_720_25fps),
> +			.regs = imx415_mode_4_720_25fps,
> +		},
> +	},
> +	{
> +		.lane_rate = 720000000,
> +		.lanes = 4,
> +		.hmax_pix = 4510,
> +		.pixel_rate = 304615385,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_720_30fps),
> +			.regs = imx415_mode_4_720_30fps,
> +		},
> +	},
>  	{
>  		.lane_rate = 891000000,
>  		.lanes = 4,
> @@ -566,6 +868,66 @@ static const struct imx415_mode supported_modes[] = {
>  			.regs = imx415_mode_4_891,
>  		},
>  	},
> +	{
> +		.lane_rate = 1440000000,
> +		.lanes = 4,
> +		.hmax_pix = 4510,
> +		.pixel_rate = 304615385,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1440_30fps),
> +			.regs = imx415_mode_4_1440_30fps,
> +		},
> +	},
> +	{
> +		.lane_rate = 1440000000,
> +		.lanes = 4,
> +		.hmax_pix = 4510,
> +		.pixel_rate = 609230769,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1440_60fps),
> +			.regs = imx415_mode_4_1440_60fps,
> +		},
> +	},
> +	{
> +		.lane_rate = 1485000000,
> +		.lanes = 4,
> +		.hmax_pix = 4400,
> +		.pixel_rate = 594000000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1485),
> +			.regs = imx415_mode_4_1485,
> +		},
> +	},
> +	{
> +		.lane_rate = 1782000000,
> +		.lanes = 4,
> +		.hmax_pix = 4400,
> +		.pixel_rate = 594000000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1782),
> +			.regs = imx415_mode_4_1782,
> +		},
> +	},
> +	{
> +		.lane_rate = 2079000000,
> +		.lanes = 4,
> +		.hmax_pix = 4400,
> +		.pixel_rate = 594000000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2079),
> +			.regs = imx415_mode_4_2079,
> +		},
> +	},
> +	{
> +		.lane_rate = 12376000000,
> +		.lanes = 4,
> +		.hmax_pix = 4392,
> +		.pixel_rate = 891000000,
> +		.reg_list = {
> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2376),
> +			.regs = imx415_mode_4_2376,
> +		},
> +	},
>  };
>  
>  static const char *const imx415_test_pattern_menu[] = {

-- 
Regards,

Laurent Pinchart

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 3/3] media: i2c: imx415: Add more supported modes
  2023-12-05 10:45   ` Laurent Pinchart
@ 2023-12-05 11:12     ` Alexander Stein
  2023-12-05 14:47       ` Gerald Loacker
  0 siblings, 1 reply; 15+ messages in thread
From: Alexander Stein @ 2023-12-05 11:12 UTC (permalink / raw)
  To: Laurent Pinchart
  Cc: Mauro Carvalho Chehab, Michael Riesch, Sakari Ailus,
	Gerald Loacker, linux-media

Hi Laurent,

Am Dienstag, 5. Dezember 2023, 11:45:09 CET schrieb Laurent Pinchart:
> Hi Alexander,
> 
> Thank you for the patch.
> 
> On Tue, Dec 05, 2023 at 10:05:57AM +0100, Alexander Stein wrote:
> > These modes are listed in section "All-pixel mode" of the datasheet
> > IMX415-AAQR-C (Rev. E19504, 2019/05/21).
> > hmax_pix and pixel_rate are taken from the comment above the mode list.
> > 
> > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> > 
> >  drivers/media/i2c/imx415.c | 362 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 362 insertions(+)
> > 
> > diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
> > index a222b9134aa2..48b8ae6d790d 100644
> > --- a/drivers/media/i2c/imx415.c
> > +++ b/drivers/media/i2c/imx415.c
> > @@ -445,6 +445,38 @@ static const struct imx415_clk_params
> > imx415_clk_params[] = {> 
> >  	},
> >  
> >  };
> > 
> > +/* all-pixel 2-lane 594 Mbps 10 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_2_594[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0CE4 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> > +	{ IMX415_TCLKPOST, 0x0067 },
> > +	{ IMX415_TCLKPREPARE, 0x0027 },
> > +	{ IMX415_TCLKTRAIL, 0x0027 },
> > +	{ IMX415_TCLKZERO, 0x00B7 },
> > +	{ IMX415_THSPREPARE, 0x002F },
> > +	{ IMX415_THSZERO, 0x004F },
> > +	{ IMX415_THSTRAIL, 0x002F },
> > +	{ IMX415_THSEXIT, 0x0047 },
> > +	{ IMX415_TLPX, 0x0027 },
> > +};
> > +
> > +/* all-pixel 2-lane 891 Mbps 15 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_2_891[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0898 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> > +	{ IMX415_TCLKPOST, 0x007F },
> > +	{ IMX415_TCLKPREPARE, 0x0037 },
> > +	{ IMX415_TCLKTRAIL, 0x0037 },
> > +	{ IMX415_TCLKZERO, 0x00F7 },
> > +	{ IMX415_THSPREPARE, 0x003F },
> > +	{ IMX415_THSZERO, 0x006F },
> > +	{ IMX415_THSTRAIL, 0x003F },
> > +	{ IMX415_THSEXIT, 0x005F },
> > +	{ IMX415_TLPX, 0x002F },
> > +};
> > +
> > 
> >  /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
> >  static const struct cci_reg_sequence imx415_mode_2_720[] = {
> >  
> >  	{ IMX415_VMAX, 0x08CA },
> > 
> > @@ -461,6 +493,38 @@ static const struct cci_reg_sequence
> > imx415_mode_2_720[] = {> 
> >  	{ IMX415_TLPX, 0x0027 },
> >  
> >  };
> > 
> > +/* all-pixel 2-lane 1782 Mbps 30 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_2_1782[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x044C },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> > +	{ IMX415_TCLKPOST, 0x00B7 },
> > +	{ IMX415_TCLKPREPARE, 0x0067 },
> > +	{ IMX415_TCLKTRAIL, 0x006F },
> > +	{ IMX415_TCLKZERO, 0x01DF },
> > +	{ IMX415_THSPREPARE, 0x006F },
> > +	{ IMX415_THSZERO, 0x00CF },
> > +	{ IMX415_THSTRAIL, 0x006F },
> > +	{ IMX415_THSEXIT, 0x00B7 },
> > +	{ IMX415_TLPX, 0x005F },
> > +};
> > +
> > +/* all-pixel 2-lane 2079 Mbps 30 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_2_2079[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x044C },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> > +	{ IMX415_TCLKPOST, 0x00D7 },
> > +	{ IMX415_TCLKPREPARE, 0x007F },
> > +	{ IMX415_TCLKTRAIL, 0x007F },
> > +	{ IMX415_TCLKZERO, 0x0237 },
> > +	{ IMX415_THSPREPARE, 0x0087 },
> > +	{ IMX415_THSZERO, 0x00EF },
> > +	{ IMX415_THSTRAIL, 0x0087 },
> > +	{ IMX415_THSEXIT, 0x00DF },
> > +	{ IMX415_TLPX, 0x006F },
> > +};
> > +
> > 
> >  /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
> >  static const struct cci_reg_sequence imx415_mode_2_1440[] = {
> >  
> >  	{ IMX415_VMAX, 0x08CA },
> > 
> > @@ -477,6 +541,70 @@ static const struct cci_reg_sequence
> > imx415_mode_2_1440[] = {> 
> >  	{ IMX415_TLPX, 0x004F },
> >  
> >  };
> > 
> > +/* all-pixel 4-lane 594 Mbps 20 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_594_20fps[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0672 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x0067 },
> > +	{ IMX415_TCLKPREPARE, 0x0027 },
> > +	{ IMX415_TCLKTRAIL, 0x0027 },
> > +	{ IMX415_TCLKZERO, 0x00B7 },
> > +	{ IMX415_THSPREPARE, 0x002F },
> > +	{ IMX415_THSZERO, 0x004F },
> > +	{ IMX415_THSTRAIL, 0x002F },
> > +	{ IMX415_THSEXIT, 0x0047 },
> > +	{ IMX415_TLPX, 0x0027 },
> > +};
> > +
> > +/* all-pixel 4-lane 594 Mbps 25 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_594_25fps[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0528 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x0067 },
> > +	{ IMX415_TCLKPREPARE, 0x0027 },
> > +	{ IMX415_TCLKTRAIL, 0x0027 },
> > +	{ IMX415_TCLKZERO, 0x00B7 },
> > +	{ IMX415_THSPREPARE, 0x002F },
> > +	{ IMX415_THSZERO, 0x004F },
> > +	{ IMX415_THSTRAIL, 0x002F },
> > +	{ IMX415_THSEXIT, 0x0047 },
> > +	{ IMX415_TLPX, 0x0027 },
> > +};
> > +
> > +/* all-pixel 4-lane 720 Mbps 25 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_720_25fps[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0500 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x006F },
> > +	{ IMX415_TCLKPREPARE, 0x002F },
> > +	{ IMX415_TCLKTRAIL, 0x002F },
> > +	{ IMX415_TCLKZERO, 0x00BF },
> > +	{ IMX415_THSPREPARE, 0x002F },
> > +	{ IMX415_THSZERO, 0x0057 },
> > +	{ IMX415_THSTRAIL, 0x002F },
> > +	{ IMX415_THSEXIT, 0x004F },
> > +	{ IMX415_TLPX, 0x0027 },
> > +};
> > +
> > +/* all-pixel 4-lane 720 Mbps 30.01 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_720_30fps[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x042A },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x006F },
> > +	{ IMX415_TCLKPREPARE, 0x002F },
> > +	{ IMX415_TCLKTRAIL, 0x002F },
> > +	{ IMX415_TCLKZERO, 0x00BF },
> > +	{ IMX415_THSPREPARE, 0x002F },
> > +	{ IMX415_THSZERO, 0x0057 },
> > +	{ IMX415_THSTRAIL, 0x002F },
> > +	{ IMX415_THSEXIT, 0x004F },
> > +	{ IMX415_TLPX, 0x0027 },
> > +};
> > +
> > 
> >  /* all-pixel 4-lane 891 Mbps 30 Hz mode */
> >  static const struct cci_reg_sequence imx415_mode_4_891[] = {
> >  
> >  	{ IMX415_VMAX, 0x08CA },
> > 
> > @@ -493,6 +621,102 @@ static const struct cci_reg_sequence
> > imx415_mode_4_891[] = {> 
> >  	{ IMX415_TLPX, 0x002F },
> >  
> >  };
> > 
> > +/* all-pixel 4-lane 1440 Mbps 30.01 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_1440_30fps[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x042A },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x009F },
> > +	{ IMX415_TCLKPREPARE, 0x0057 },
> > +	{ IMX415_TCLKTRAIL, 0x0057 },
> > +	{ IMX415_TCLKZERO, 0x0187 },
> > +	{ IMX415_THSPREPARE, 0x005F },
> > +	{ IMX415_THSZERO, 0x00A7 },
> > +	{ IMX415_THSTRAIL, 0x005F },
> > +	{ IMX415_THSEXIT, 0x0097 },
> > +	{ IMX415_TLPX, 0x004F },
> > +};
> > +
> > +/* all-pixel 4-lane 1440 Mbps 60.03 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_1440_60fps[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0215 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x009F },
> > +	{ IMX415_TCLKPREPARE, 0x0057 },
> > +	{ IMX415_TCLKTRAIL, 0x0057 },
> > +	{ IMX415_TCLKZERO, 0x0187 },
> > +	{ IMX415_THSPREPARE, 0x005F },
> > +	{ IMX415_THSZERO, 0x00A7 },
> > +	{ IMX415_THSTRAIL, 0x005F },
> > +	{ IMX415_THSEXIT, 0x0097 },
> > +	{ IMX415_TLPX, 0x004F },
> > +};
> > +
> > +/* all-pixel 4-lane 1485 Mbps 60 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_1485[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0226 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x00A7 },
> > +	{ IMX415_TCLKPREPARE, 0x0057 },
> > +	{ IMX415_TCLKTRAIL, 0x005F },
> > +	{ IMX415_TCLKZERO, 0x0197 },
> > +	{ IMX415_THSPREPARE, 0x005F },
> > +	{ IMX415_THSZERO, 0x00AF },
> > +	{ IMX415_THSTRAIL, 0x005F },
> > +	{ IMX415_THSEXIT, 0x009F },
> > +	{ IMX415_TLPX, 0x004F },
> > +};
> > +
> > +/* all-pixel 4-lane 1782 Mbps 60 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_1782[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0226 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x00B7 },
> > +	{ IMX415_TCLKPREPARE, 0x0067 },
> > +	{ IMX415_TCLKTRAIL, 0x006F },
> > +	{ IMX415_TCLKZERO, 0x01DF },
> > +	{ IMX415_THSPREPARE, 0x006F },
> > +	{ IMX415_THSZERO, 0x00CF },
> > +	{ IMX415_THSTRAIL, 0x006F },
> > +	{ IMX415_THSEXIT, 0x00B7 },
> > +	{ IMX415_TLPX, 0x005F },
> > +};
> > +
> > +/* all-pixel 4-lane 2079 Mbps 60 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_2079[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x0226 },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x00D7 },
> > +	{ IMX415_TCLKPREPARE, 0x007F },
> > +	{ IMX415_TCLKTRAIL, 0x007F },
> > +	{ IMX415_TCLKZERO, 0x0237 },
> > +	{ IMX415_THSPREPARE, 0x0087 },
> > +	{ IMX415_THSZERO, 0x00EF },
> > +	{ IMX415_THSTRAIL, 0x0087 },
> > +	{ IMX415_THSEXIT, 0x00DF },
> > +	{ IMX415_TLPX, 0x006F },
> > +};
> > +
> > +/* all-pixel 4-lane 2376 Mbps 60 Hz mode */
> > +static const struct cci_reg_sequence imx415_mode_4_2376[] = {
> > +	{ IMX415_VMAX, 0x08CA },
> > +	{ IMX415_HMAX, 0x016E },
> > +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > +	{ IMX415_TCLKPOST, 0x00E7 },
> > +	{ IMX415_TCLKPREPARE, 0x008F },
> > +	{ IMX415_TCLKTRAIL, 0x008F },
> > +	{ IMX415_TCLKZERO, 0x027F },
> > +	{ IMX415_THSPREPARE, 0x0097 },
> > +	{ IMX415_THSZERO, 0x010F },
> > +	{ IMX415_THSTRAIL, 0x0097 },
> > +	{ IMX415_THSEXIT, 0x00F7 },
> > +	{ IMX415_TLPX, 0x007F },
> > +};
> > +
> > 
> >  struct imx415_mode_reg_list {
> >  
> >  	u32 num_of_regs;
> >  	const struct cci_reg_sequence *regs;
> > 
> > @@ -536,6 +760,26 @@ struct imx415_mode {
> > 
> >  /* mode configs */
> >  static const struct imx415_mode supported_modes[] = {
> > 
> > +	{
> > +		.lane_rate = 594000000,
> > +		.lanes = 2,
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 99000000,
> > +		.reg_list = {
> > +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_594),
> > +			.regs = imx415_mode_2_594,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 891000000,
> > +		.lanes = 2,
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 148500000,
> > +		.reg_list = {
> > +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_891),
> > +			.regs = imx415_mode_2_891,
> > +		},
> > +	},
> > 
> >  	{
> >  	
> >  		.lane_rate = 720000000,
> >  		.lanes = 2,
> > 
> > @@ -547,6 +791,24 @@ static const struct imx415_mode supported_modes[] = {
> > 
> >  		},
> >  	
> >  	},
> >  	{
> > 
> > +		.lane_rate = 1782000000,
> > +		.lanes = 2,
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 297000000,
> > +		.reg_list = {
> > +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_1782),
> > +			.regs = imx415_mode_2_1782,
> > +		},
> > +	},	{
> > +		.lane_rate = 2079000000,
> > +		.lanes = 2,
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 304615385,
> > +		.reg_list = {
> > +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_2079),
> > +			.regs = imx415_mode_2_2079,
> > +		},
> > +	},	{
> > 
> >  		.lane_rate = 1440000000,
> >  		.lanes = 2,
> >  		.hmax_pix = 4510,
> > 
> > @@ -556,6 +818,46 @@ static const struct imx415_mode supported_modes[] = {
> > 
> >  			.regs = imx415_mode_2_1440,
> >  		
> >  		},
> >  	
> >  	},
> > 
> > +	{
> > +		.lane_rate = 594000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 5500,
> > +		.pixel_rate = 247500000,
> > +		.reg_list = {
> > +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_594_20fps),
> > +			.regs = imx415_mode_4_594_20fps,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 594000000,
> > +		.lanes = 4,
> 
> The mode is selected from the number of data lanes and the lane rate.
> They're the same as the previous entry, so this entry will never be
> selected. Same below.

I noticed that as well. The datasheet lists different FPS for the same link 
frequency / lane combination, only HMAX being different. Right now HMAX/VMAX 
is fixed, so is FPS.
I am aware there is no way to select between these modes, but I added them for 
completeness.

Best regards
Alexander

> 
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 247500000,
> > +		.reg_list = {
> > +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_594_25fps),
> > +			.regs = imx415_mode_4_594_25fps,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 720000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 247500000,
> > +		.reg_list = {
> > +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_720_25fps),
> > +			.regs = imx415_mode_4_720_25fps,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 720000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 4510,
> > +		.pixel_rate = 304615385,
> > +		.reg_list = {
> > +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_720_30fps),
> > +			.regs = imx415_mode_4_720_30fps,
> > +		},
> > +	},
> > 
> >  	{
> >  	
> >  		.lane_rate = 891000000,
> >  		.lanes = 4,
> > 
> > @@ -566,6 +868,66 @@ static const struct imx415_mode supported_modes[] = {
> > 
> >  			.regs = imx415_mode_4_891,
> >  		
> >  		},
> >  	
> >  	},
> > 
> > +	{
> > +		.lane_rate = 1440000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 4510,
> > +		.pixel_rate = 304615385,
> > +		.reg_list = {
> > +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_1440_30fps),
> > +			.regs = imx415_mode_4_1440_30fps,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 1440000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 4510,
> > +		.pixel_rate = 609230769,
> > +		.reg_list = {
> > +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_1440_60fps),
> > +			.regs = imx415_mode_4_1440_60fps,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 1485000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 594000000,
> > +		.reg_list = {
> > +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1485),
> > +			.regs = imx415_mode_4_1485,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 1782000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 594000000,
> > +		.reg_list = {
> > +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1782),
> > +			.regs = imx415_mode_4_1782,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 2079000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 4400,
> > +		.pixel_rate = 594000000,
> > +		.reg_list = {
> > +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2079),
> > +			.regs = imx415_mode_4_2079,
> > +		},
> > +	},
> > +	{
> > +		.lane_rate = 12376000000,
> > +		.lanes = 4,
> > +		.hmax_pix = 4392,
> > +		.pixel_rate = 891000000,
> > +		.reg_list = {
> > +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2376),
> > +			.regs = imx415_mode_4_2376,
> > +		},
> > +	},
> > 
> >  };
> >  
> >  static const char *const imx415_test_pattern_menu[] = {


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/



^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 3/3] media: i2c: imx415: Add more supported modes
  2023-12-05 11:12     ` Alexander Stein
@ 2023-12-05 14:47       ` Gerald Loacker
  2023-12-05 14:54         ` Laurent Pinchart
  0 siblings, 1 reply; 15+ messages in thread
From: Gerald Loacker @ 2023-12-05 14:47 UTC (permalink / raw)
  To: Alexander Stein, Laurent Pinchart
  Cc: Mauro Carvalho Chehab, Michael Riesch, Sakari Ailus, linux-media

Hi Alexander,

thanks for updating this driver.

Am 05.12.2023 um 12:12 schrieb Alexander Stein:
> Hi Laurent,
> 
> Am Dienstag, 5. Dezember 2023, 11:45:09 CET schrieb Laurent Pinchart:
>> Hi Alexander,
>>
>> Thank you for the patch.
>>
>> On Tue, Dec 05, 2023 at 10:05:57AM +0100, Alexander Stein wrote:
>>> These modes are listed in section "All-pixel mode" of the datasheet
>>> IMX415-AAQR-C (Rev. E19504, 2019/05/21).
>>> hmax_pix and pixel_rate are taken from the comment above the mode list.
>>>
>>> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
>>> ---
>>>
>>>  drivers/media/i2c/imx415.c | 362 +++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 362 insertions(+)
>>>
>>> diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
>>> index a222b9134aa2..48b8ae6d790d 100644
>>> --- a/drivers/media/i2c/imx415.c
>>> +++ b/drivers/media/i2c/imx415.c
>>> @@ -445,6 +445,38 @@ static const struct imx415_clk_params
>>> imx415_clk_params[] = {> 
>>>  	},
>>>  
>>>  };
>>>
>>> +/* all-pixel 2-lane 594 Mbps 10 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_2_594[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0CE4 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
>>> +	{ IMX415_TCLKPOST, 0x0067 },
>>> +	{ IMX415_TCLKPREPARE, 0x0027 },
>>> +	{ IMX415_TCLKTRAIL, 0x0027 },
>>> +	{ IMX415_TCLKZERO, 0x00B7 },
>>> +	{ IMX415_THSPREPARE, 0x002F },
>>> +	{ IMX415_THSZERO, 0x004F },
>>> +	{ IMX415_THSTRAIL, 0x002F },
>>> +	{ IMX415_THSEXIT, 0x0047 },
>>> +	{ IMX415_TLPX, 0x0027 },
>>> +};
>>> +
>>> +/* all-pixel 2-lane 891 Mbps 15 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_2_891[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0898 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
>>> +	{ IMX415_TCLKPOST, 0x007F },
>>> +	{ IMX415_TCLKPREPARE, 0x0037 },
>>> +	{ IMX415_TCLKTRAIL, 0x0037 },
>>> +	{ IMX415_TCLKZERO, 0x00F7 },
>>> +	{ IMX415_THSPREPARE, 0x003F },
>>> +	{ IMX415_THSZERO, 0x006F },
>>> +	{ IMX415_THSTRAIL, 0x003F },
>>> +	{ IMX415_THSEXIT, 0x005F },
>>> +	{ IMX415_TLPX, 0x002F },
>>> +};
>>> +
>>>
>>>  /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
>>>  static const struct cci_reg_sequence imx415_mode_2_720[] = {
>>>  
>>>  	{ IMX415_VMAX, 0x08CA },
>>>
>>> @@ -461,6 +493,38 @@ static const struct cci_reg_sequence
>>> imx415_mode_2_720[] = {> 
>>>  	{ IMX415_TLPX, 0x0027 },
>>>  
>>>  };
>>>
>>> +/* all-pixel 2-lane 1782 Mbps 30 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_2_1782[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x044C },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
>>> +	{ IMX415_TCLKPOST, 0x00B7 },
>>> +	{ IMX415_TCLKPREPARE, 0x0067 },
>>> +	{ IMX415_TCLKTRAIL, 0x006F },
>>> +	{ IMX415_TCLKZERO, 0x01DF },
>>> +	{ IMX415_THSPREPARE, 0x006F },
>>> +	{ IMX415_THSZERO, 0x00CF },
>>> +	{ IMX415_THSTRAIL, 0x006F },
>>> +	{ IMX415_THSEXIT, 0x00B7 },
>>> +	{ IMX415_TLPX, 0x005F },
>>> +};
>>> +
>>> +/* all-pixel 2-lane 2079 Mbps 30 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_2_2079[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x044C },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
>>> +	{ IMX415_TCLKPOST, 0x00D7 },
>>> +	{ IMX415_TCLKPREPARE, 0x007F },
>>> +	{ IMX415_TCLKTRAIL, 0x007F },
>>> +	{ IMX415_TCLKZERO, 0x0237 },
>>> +	{ IMX415_THSPREPARE, 0x0087 },
>>> +	{ IMX415_THSZERO, 0x00EF },
>>> +	{ IMX415_THSTRAIL, 0x0087 },
>>> +	{ IMX415_THSEXIT, 0x00DF },
>>> +	{ IMX415_TLPX, 0x006F },
>>> +};
>>> +
>>>
>>>  /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
>>>  static const struct cci_reg_sequence imx415_mode_2_1440[] = {
>>>  
>>>  	{ IMX415_VMAX, 0x08CA },
>>>
>>> @@ -477,6 +541,70 @@ static const struct cci_reg_sequence
>>> imx415_mode_2_1440[] = {> 
>>>  	{ IMX415_TLPX, 0x004F },
>>>  
>>>  };
>>>
>>> +/* all-pixel 4-lane 594 Mbps 20 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_594_20fps[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0672 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x0067 },
>>> +	{ IMX415_TCLKPREPARE, 0x0027 },
>>> +	{ IMX415_TCLKTRAIL, 0x0027 },
>>> +	{ IMX415_TCLKZERO, 0x00B7 },
>>> +	{ IMX415_THSPREPARE, 0x002F },
>>> +	{ IMX415_THSZERO, 0x004F },
>>> +	{ IMX415_THSTRAIL, 0x002F },
>>> +	{ IMX415_THSEXIT, 0x0047 },
>>> +	{ IMX415_TLPX, 0x0027 },
>>> +};
>>> +
>>> +/* all-pixel 4-lane 594 Mbps 25 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_594_25fps[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0528 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x0067 },
>>> +	{ IMX415_TCLKPREPARE, 0x0027 },
>>> +	{ IMX415_TCLKTRAIL, 0x0027 },
>>> +	{ IMX415_TCLKZERO, 0x00B7 },
>>> +	{ IMX415_THSPREPARE, 0x002F },
>>> +	{ IMX415_THSZERO, 0x004F },
>>> +	{ IMX415_THSTRAIL, 0x002F },
>>> +	{ IMX415_THSEXIT, 0x0047 },
>>> +	{ IMX415_TLPX, 0x0027 },
>>> +};
>>> +
>>> +/* all-pixel 4-lane 720 Mbps 25 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_720_25fps[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0500 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x006F },
>>> +	{ IMX415_TCLKPREPARE, 0x002F },
>>> +	{ IMX415_TCLKTRAIL, 0x002F },
>>> +	{ IMX415_TCLKZERO, 0x00BF },
>>> +	{ IMX415_THSPREPARE, 0x002F },
>>> +	{ IMX415_THSZERO, 0x0057 },
>>> +	{ IMX415_THSTRAIL, 0x002F },
>>> +	{ IMX415_THSEXIT, 0x004F },
>>> +	{ IMX415_TLPX, 0x0027 },
>>> +};
>>> +
>>> +/* all-pixel 4-lane 720 Mbps 30.01 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_720_30fps[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x042A },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x006F },
>>> +	{ IMX415_TCLKPREPARE, 0x002F },
>>> +	{ IMX415_TCLKTRAIL, 0x002F },
>>> +	{ IMX415_TCLKZERO, 0x00BF },
>>> +	{ IMX415_THSPREPARE, 0x002F },
>>> +	{ IMX415_THSZERO, 0x0057 },
>>> +	{ IMX415_THSTRAIL, 0x002F },
>>> +	{ IMX415_THSEXIT, 0x004F },
>>> +	{ IMX415_TLPX, 0x0027 },
>>> +};
>>> +
>>>
>>>  /* all-pixel 4-lane 891 Mbps 30 Hz mode */
>>>  static const struct cci_reg_sequence imx415_mode_4_891[] = {
>>>  
>>>  	{ IMX415_VMAX, 0x08CA },
>>>
>>> @@ -493,6 +621,102 @@ static const struct cci_reg_sequence
>>> imx415_mode_4_891[] = {> 
>>>  	{ IMX415_TLPX, 0x002F },
>>>  
>>>  };
>>>
>>> +/* all-pixel 4-lane 1440 Mbps 30.01 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_1440_30fps[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x042A },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x009F },
>>> +	{ IMX415_TCLKPREPARE, 0x0057 },
>>> +	{ IMX415_TCLKTRAIL, 0x0057 },
>>> +	{ IMX415_TCLKZERO, 0x0187 },
>>> +	{ IMX415_THSPREPARE, 0x005F },
>>> +	{ IMX415_THSZERO, 0x00A7 },
>>> +	{ IMX415_THSTRAIL, 0x005F },
>>> +	{ IMX415_THSEXIT, 0x0097 },
>>> +	{ IMX415_TLPX, 0x004F },
>>> +};
>>> +
>>> +/* all-pixel 4-lane 1440 Mbps 60.03 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_1440_60fps[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0215 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x009F },
>>> +	{ IMX415_TCLKPREPARE, 0x0057 },
>>> +	{ IMX415_TCLKTRAIL, 0x0057 },
>>> +	{ IMX415_TCLKZERO, 0x0187 },
>>> +	{ IMX415_THSPREPARE, 0x005F },
>>> +	{ IMX415_THSZERO, 0x00A7 },
>>> +	{ IMX415_THSTRAIL, 0x005F },
>>> +	{ IMX415_THSEXIT, 0x0097 },
>>> +	{ IMX415_TLPX, 0x004F },
>>> +};
>>> +
>>> +/* all-pixel 4-lane 1485 Mbps 60 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_1485[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0226 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x00A7 },
>>> +	{ IMX415_TCLKPREPARE, 0x0057 },
>>> +	{ IMX415_TCLKTRAIL, 0x005F },
>>> +	{ IMX415_TCLKZERO, 0x0197 },
>>> +	{ IMX415_THSPREPARE, 0x005F },
>>> +	{ IMX415_THSZERO, 0x00AF },
>>> +	{ IMX415_THSTRAIL, 0x005F },
>>> +	{ IMX415_THSEXIT, 0x009F },
>>> +	{ IMX415_TLPX, 0x004F },
>>> +};
>>> +
>>> +/* all-pixel 4-lane 1782 Mbps 60 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_1782[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0226 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x00B7 },
>>> +	{ IMX415_TCLKPREPARE, 0x0067 },
>>> +	{ IMX415_TCLKTRAIL, 0x006F },
>>> +	{ IMX415_TCLKZERO, 0x01DF },
>>> +	{ IMX415_THSPREPARE, 0x006F },
>>> +	{ IMX415_THSZERO, 0x00CF },
>>> +	{ IMX415_THSTRAIL, 0x006F },
>>> +	{ IMX415_THSEXIT, 0x00B7 },
>>> +	{ IMX415_TLPX, 0x005F },
>>> +};
>>> +
>>> +/* all-pixel 4-lane 2079 Mbps 60 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_2079[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x0226 },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x00D7 },
>>> +	{ IMX415_TCLKPREPARE, 0x007F },
>>> +	{ IMX415_TCLKTRAIL, 0x007F },
>>> +	{ IMX415_TCLKZERO, 0x0237 },
>>> +	{ IMX415_THSPREPARE, 0x0087 },
>>> +	{ IMX415_THSZERO, 0x00EF },
>>> +	{ IMX415_THSTRAIL, 0x0087 },
>>> +	{ IMX415_THSEXIT, 0x00DF },
>>> +	{ IMX415_TLPX, 0x006F },
>>> +};
>>> +
>>> +/* all-pixel 4-lane 2376 Mbps 60 Hz mode */
>>> +static const struct cci_reg_sequence imx415_mode_4_2376[] = {
>>> +	{ IMX415_VMAX, 0x08CA },
>>> +	{ IMX415_HMAX, 0x016E },
>>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
>>> +	{ IMX415_TCLKPOST, 0x00E7 },
>>> +	{ IMX415_TCLKPREPARE, 0x008F },
>>> +	{ IMX415_TCLKTRAIL, 0x008F },
>>> +	{ IMX415_TCLKZERO, 0x027F },
>>> +	{ IMX415_THSPREPARE, 0x0097 },
>>> +	{ IMX415_THSZERO, 0x010F },
>>> +	{ IMX415_THSTRAIL, 0x0097 },
>>> +	{ IMX415_THSEXIT, 0x00F7 },
>>> +	{ IMX415_TLPX, 0x007F },
>>> +};
>>> +
>>>
>>>  struct imx415_mode_reg_list {
>>>  
>>>  	u32 num_of_regs;
>>>  	const struct cci_reg_sequence *regs;
>>>
>>> @@ -536,6 +760,26 @@ struct imx415_mode {
>>>
>>>  /* mode configs */
>>>  static const struct imx415_mode supported_modes[] = {
>>>
>>> +	{
>>> +		.lane_rate = 594000000,
>>> +		.lanes = 2,
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 99000000,
>>> +		.reg_list = {
>>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_594),
>>> +			.regs = imx415_mode_2_594,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 891000000,
>>> +		.lanes = 2,
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 148500000,
>>> +		.reg_list = {
>>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_891),
>>> +			.regs = imx415_mode_2_891,
>>> +		},
>>> +	},
>>>
>>>  	{
>>>  	
>>>  		.lane_rate = 720000000,
>>>  		.lanes = 2,
>>>
>>> @@ -547,6 +791,24 @@ static const struct imx415_mode supported_modes[] = {
>>>
>>>  		},
>>>  	
>>>  	},
>>>  	{
>>>
>>> +		.lane_rate = 1782000000,
>>> +		.lanes = 2,
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 297000000,
>>> +		.reg_list = {
>>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_1782),
>>> +			.regs = imx415_mode_2_1782,
>>> +		},
>>> +	},	{
>>> +		.lane_rate = 2079000000,
>>> +		.lanes = 2,
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 304615385,
>>> +		.reg_list = {
>>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_2079),
>>> +			.regs = imx415_mode_2_2079,
>>> +		},
>>> +	},	{
>>>
>>>  		.lane_rate = 1440000000,
>>>  		.lanes = 2,
>>>  		.hmax_pix = 4510,
>>>
>>> @@ -556,6 +818,46 @@ static const struct imx415_mode supported_modes[] = {
>>>
>>>  			.regs = imx415_mode_2_1440,
>>>  		
>>>  		},
>>>  	
>>>  	},
>>>
>>> +	{
>>> +		.lane_rate = 594000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 5500,
>>> +		.pixel_rate = 247500000,
>>> +		.reg_list = {
>>> +			.num_of_regs = 
> ARRAY_SIZE(imx415_mode_4_594_20fps),
>>> +			.regs = imx415_mode_4_594_20fps,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 594000000,
>>> +		.lanes = 4,
>>
>> The mode is selected from the number of data lanes and the lane rate.
>> They're the same as the previous entry, so this entry will never be
>> selected. Same below.
> 
> I noticed that as well. The datasheet lists different FPS for the same link 
> frequency / lane combination, only HMAX being different. Right now HMAX/VMAX 
> is fixed, so is FPS.
> I am aware there is no way to select between these modes, but I added them for 
> completeness.
> 
> Best regards
> Alexander
> 

I'd prefer to only add common and tested modes. We have to keep in mind
that in future we may want to add more features as 12 bit support or
HDR. Adding all modes could make this more complex.

Regards,
Gerald

>>
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 247500000,
>>> +		.reg_list = {
>>> +			.num_of_regs = 
> ARRAY_SIZE(imx415_mode_4_594_25fps),
>>> +			.regs = imx415_mode_4_594_25fps,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 720000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 247500000,
>>> +		.reg_list = {
>>> +			.num_of_regs = 
> ARRAY_SIZE(imx415_mode_4_720_25fps),
>>> +			.regs = imx415_mode_4_720_25fps,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 720000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 4510,
>>> +		.pixel_rate = 304615385,
>>> +		.reg_list = {
>>> +			.num_of_regs = 
> ARRAY_SIZE(imx415_mode_4_720_30fps),
>>> +			.regs = imx415_mode_4_720_30fps,
>>> +		},
>>> +	},
>>>
>>>  	{
>>>  	
>>>  		.lane_rate = 891000000,
>>>  		.lanes = 4,
>>>
>>> @@ -566,6 +868,66 @@ static const struct imx415_mode supported_modes[] = {
>>>
>>>  			.regs = imx415_mode_4_891,
>>>  		
>>>  		},
>>>  	
>>>  	},
>>>
>>> +	{
>>> +		.lane_rate = 1440000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 4510,
>>> +		.pixel_rate = 304615385,
>>> +		.reg_list = {
>>> +			.num_of_regs = 
> ARRAY_SIZE(imx415_mode_4_1440_30fps),
>>> +			.regs = imx415_mode_4_1440_30fps,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 1440000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 4510,
>>> +		.pixel_rate = 609230769,
>>> +		.reg_list = {
>>> +			.num_of_regs = 
> ARRAY_SIZE(imx415_mode_4_1440_60fps),
>>> +			.regs = imx415_mode_4_1440_60fps,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 1485000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 594000000,
>>> +		.reg_list = {
>>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1485),
>>> +			.regs = imx415_mode_4_1485,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 1782000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 594000000,
>>> +		.reg_list = {
>>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1782),
>>> +			.regs = imx415_mode_4_1782,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 2079000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 4400,
>>> +		.pixel_rate = 594000000,
>>> +		.reg_list = {
>>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2079),
>>> +			.regs = imx415_mode_4_2079,
>>> +		},
>>> +	},
>>> +	{
>>> +		.lane_rate = 12376000000,
>>> +		.lanes = 4,
>>> +		.hmax_pix = 4392,
>>> +		.pixel_rate = 891000000,
>>> +		.reg_list = {
>>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2376),
>>> +			.regs = imx415_mode_4_2376,
>>> +		},
>>> +	},
>>>
>>>  };
>>>  
>>>  static const char *const imx415_test_pattern_menu[] = {
> 
> 

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 3/3] media: i2c: imx415: Add more supported modes
  2023-12-05 14:47       ` Gerald Loacker
@ 2023-12-05 14:54         ` Laurent Pinchart
  2023-12-06  7:38           ` Alexander Stein
  0 siblings, 1 reply; 15+ messages in thread
From: Laurent Pinchart @ 2023-12-05 14:54 UTC (permalink / raw)
  To: Gerald Loacker
  Cc: Alexander Stein, Mauro Carvalho Chehab, Michael Riesch,
	Sakari Ailus, linux-media

Hello,

On Tue, Dec 05, 2023 at 03:47:15PM +0100, Gerald Loacker wrote:
> Am 05.12.2023 um 12:12 schrieb Alexander Stein:
> > Am Dienstag, 5. Dezember 2023, 11:45:09 CET schrieb Laurent Pinchart:
> >> On Tue, Dec 05, 2023 at 10:05:57AM +0100, Alexander Stein wrote:
> >>> These modes are listed in section "All-pixel mode" of the datasheet
> >>> IMX415-AAQR-C (Rev. E19504, 2019/05/21).
> >>> hmax_pix and pixel_rate are taken from the comment above the mode list.
> >>>
> >>> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> >>> ---
> >>>
> >>>  drivers/media/i2c/imx415.c | 362 +++++++++++++++++++++++++++++++++++++
> >>>  1 file changed, 362 insertions(+)
> >>>
> >>> diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
> >>> index a222b9134aa2..48b8ae6d790d 100644
> >>> --- a/drivers/media/i2c/imx415.c
> >>> +++ b/drivers/media/i2c/imx415.c
> >>> @@ -445,6 +445,38 @@ static const struct imx415_clk_params imx415_clk_params[] = {
> >>>  	},
> >>>  };
> >>>
> >>> +/* all-pixel 2-lane 594 Mbps 10 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_2_594[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0CE4 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> >>> +	{ IMX415_TCLKPOST, 0x0067 },
> >>> +	{ IMX415_TCLKPREPARE, 0x0027 },
> >>> +	{ IMX415_TCLKTRAIL, 0x0027 },
> >>> +	{ IMX415_TCLKZERO, 0x00B7 },
> >>> +	{ IMX415_THSPREPARE, 0x002F },
> >>> +	{ IMX415_THSZERO, 0x004F },
> >>> +	{ IMX415_THSTRAIL, 0x002F },
> >>> +	{ IMX415_THSEXIT, 0x0047 },
> >>> +	{ IMX415_TLPX, 0x0027 },
> >>> +};
> >>> +
> >>> +/* all-pixel 2-lane 891 Mbps 15 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_2_891[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0898 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> >>> +	{ IMX415_TCLKPOST, 0x007F },
> >>> +	{ IMX415_TCLKPREPARE, 0x0037 },
> >>> +	{ IMX415_TCLKTRAIL, 0x0037 },
> >>> +	{ IMX415_TCLKZERO, 0x00F7 },
> >>> +	{ IMX415_THSPREPARE, 0x003F },
> >>> +	{ IMX415_THSZERO, 0x006F },
> >>> +	{ IMX415_THSTRAIL, 0x003F },
> >>> +	{ IMX415_THSEXIT, 0x005F },
> >>> +	{ IMX415_TLPX, 0x002F },
> >>> +};
> >>> +
> >>>  /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
> >>>  static const struct cci_reg_sequence imx415_mode_2_720[] = {
> >>>  	{ IMX415_VMAX, 0x08CA },
> >>> @@ -461,6 +493,38 @@ static const struct cci_reg_sequence imx415_mode_2_720[] = {
> >>>  	{ IMX415_TLPX, 0x0027 },
> >>>  };
> >>>
> >>> +/* all-pixel 2-lane 1782 Mbps 30 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_2_1782[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x044C },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> >>> +	{ IMX415_TCLKPOST, 0x00B7 },
> >>> +	{ IMX415_TCLKPREPARE, 0x0067 },
> >>> +	{ IMX415_TCLKTRAIL, 0x006F },
> >>> +	{ IMX415_TCLKZERO, 0x01DF },
> >>> +	{ IMX415_THSPREPARE, 0x006F },
> >>> +	{ IMX415_THSZERO, 0x00CF },
> >>> +	{ IMX415_THSTRAIL, 0x006F },
> >>> +	{ IMX415_THSEXIT, 0x00B7 },
> >>> +	{ IMX415_TLPX, 0x005F },
> >>> +};
> >>> +
> >>> +/* all-pixel 2-lane 2079 Mbps 30 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_2_2079[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x044C },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> >>> +	{ IMX415_TCLKPOST, 0x00D7 },
> >>> +	{ IMX415_TCLKPREPARE, 0x007F },
> >>> +	{ IMX415_TCLKTRAIL, 0x007F },
> >>> +	{ IMX415_TCLKZERO, 0x0237 },
> >>> +	{ IMX415_THSPREPARE, 0x0087 },
> >>> +	{ IMX415_THSZERO, 0x00EF },
> >>> +	{ IMX415_THSTRAIL, 0x0087 },
> >>> +	{ IMX415_THSEXIT, 0x00DF },
> >>> +	{ IMX415_TLPX, 0x006F },
> >>> +};
> >>> +
> >>>  /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
> >>>  static const struct cci_reg_sequence imx415_mode_2_1440[] = {
> >>>  	{ IMX415_VMAX, 0x08CA },
> >>> @@ -477,6 +541,70 @@ static const struct cci_reg_sequence imx415_mode_2_1440[] = {
> >>>  	{ IMX415_TLPX, 0x004F },
> >>>  };
> >>>
> >>> +/* all-pixel 4-lane 594 Mbps 20 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_594_20fps[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0672 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x0067 },
> >>> +	{ IMX415_TCLKPREPARE, 0x0027 },
> >>> +	{ IMX415_TCLKTRAIL, 0x0027 },
> >>> +	{ IMX415_TCLKZERO, 0x00B7 },
> >>> +	{ IMX415_THSPREPARE, 0x002F },
> >>> +	{ IMX415_THSZERO, 0x004F },
> >>> +	{ IMX415_THSTRAIL, 0x002F },
> >>> +	{ IMX415_THSEXIT, 0x0047 },
> >>> +	{ IMX415_TLPX, 0x0027 },
> >>> +};
> >>> +
> >>> +/* all-pixel 4-lane 594 Mbps 25 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_594_25fps[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0528 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x0067 },
> >>> +	{ IMX415_TCLKPREPARE, 0x0027 },
> >>> +	{ IMX415_TCLKTRAIL, 0x0027 },
> >>> +	{ IMX415_TCLKZERO, 0x00B7 },
> >>> +	{ IMX415_THSPREPARE, 0x002F },
> >>> +	{ IMX415_THSZERO, 0x004F },
> >>> +	{ IMX415_THSTRAIL, 0x002F },
> >>> +	{ IMX415_THSEXIT, 0x0047 },
> >>> +	{ IMX415_TLPX, 0x0027 },
> >>> +};
> >>> +
> >>> +/* all-pixel 4-lane 720 Mbps 25 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_720_25fps[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0500 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x006F },
> >>> +	{ IMX415_TCLKPREPARE, 0x002F },
> >>> +	{ IMX415_TCLKTRAIL, 0x002F },
> >>> +	{ IMX415_TCLKZERO, 0x00BF },
> >>> +	{ IMX415_THSPREPARE, 0x002F },
> >>> +	{ IMX415_THSZERO, 0x0057 },
> >>> +	{ IMX415_THSTRAIL, 0x002F },
> >>> +	{ IMX415_THSEXIT, 0x004F },
> >>> +	{ IMX415_TLPX, 0x0027 },
> >>> +};
> >>> +
> >>> +/* all-pixel 4-lane 720 Mbps 30.01 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_720_30fps[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x042A },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x006F },
> >>> +	{ IMX415_TCLKPREPARE, 0x002F },
> >>> +	{ IMX415_TCLKTRAIL, 0x002F },
> >>> +	{ IMX415_TCLKZERO, 0x00BF },
> >>> +	{ IMX415_THSPREPARE, 0x002F },
> >>> +	{ IMX415_THSZERO, 0x0057 },
> >>> +	{ IMX415_THSTRAIL, 0x002F },
> >>> +	{ IMX415_THSEXIT, 0x004F },
> >>> +	{ IMX415_TLPX, 0x0027 },
> >>> +};
> >>> +
> >>>  /* all-pixel 4-lane 891 Mbps 30 Hz mode */
> >>>  static const struct cci_reg_sequence imx415_mode_4_891[] = {
> >>>  	{ IMX415_VMAX, 0x08CA },
> >>> @@ -493,6 +621,102 @@ static const struct cci_reg_sequence imx415_mode_4_891[] = {
> >>>  	{ IMX415_TLPX, 0x002F },
> >>>  };
> >>>
> >>> +/* all-pixel 4-lane 1440 Mbps 30.01 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_1440_30fps[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x042A },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x009F },
> >>> +	{ IMX415_TCLKPREPARE, 0x0057 },
> >>> +	{ IMX415_TCLKTRAIL, 0x0057 },
> >>> +	{ IMX415_TCLKZERO, 0x0187 },
> >>> +	{ IMX415_THSPREPARE, 0x005F },
> >>> +	{ IMX415_THSZERO, 0x00A7 },
> >>> +	{ IMX415_THSTRAIL, 0x005F },
> >>> +	{ IMX415_THSEXIT, 0x0097 },
> >>> +	{ IMX415_TLPX, 0x004F },
> >>> +};
> >>> +
> >>> +/* all-pixel 4-lane 1440 Mbps 60.03 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_1440_60fps[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0215 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x009F },
> >>> +	{ IMX415_TCLKPREPARE, 0x0057 },
> >>> +	{ IMX415_TCLKTRAIL, 0x0057 },
> >>> +	{ IMX415_TCLKZERO, 0x0187 },
> >>> +	{ IMX415_THSPREPARE, 0x005F },
> >>> +	{ IMX415_THSZERO, 0x00A7 },
> >>> +	{ IMX415_THSTRAIL, 0x005F },
> >>> +	{ IMX415_THSEXIT, 0x0097 },
> >>> +	{ IMX415_TLPX, 0x004F },
> >>> +};
> >>> +
> >>> +/* all-pixel 4-lane 1485 Mbps 60 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_1485[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0226 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x00A7 },
> >>> +	{ IMX415_TCLKPREPARE, 0x0057 },
> >>> +	{ IMX415_TCLKTRAIL, 0x005F },
> >>> +	{ IMX415_TCLKZERO, 0x0197 },
> >>> +	{ IMX415_THSPREPARE, 0x005F },
> >>> +	{ IMX415_THSZERO, 0x00AF },
> >>> +	{ IMX415_THSTRAIL, 0x005F },
> >>> +	{ IMX415_THSEXIT, 0x009F },
> >>> +	{ IMX415_TLPX, 0x004F },
> >>> +};
> >>> +
> >>> +/* all-pixel 4-lane 1782 Mbps 60 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_1782[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0226 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x00B7 },
> >>> +	{ IMX415_TCLKPREPARE, 0x0067 },
> >>> +	{ IMX415_TCLKTRAIL, 0x006F },
> >>> +	{ IMX415_TCLKZERO, 0x01DF },
> >>> +	{ IMX415_THSPREPARE, 0x006F },
> >>> +	{ IMX415_THSZERO, 0x00CF },
> >>> +	{ IMX415_THSTRAIL, 0x006F },
> >>> +	{ IMX415_THSEXIT, 0x00B7 },
> >>> +	{ IMX415_TLPX, 0x005F },
> >>> +};
> >>> +
> >>> +/* all-pixel 4-lane 2079 Mbps 60 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_2079[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x0226 },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x00D7 },
> >>> +	{ IMX415_TCLKPREPARE, 0x007F },
> >>> +	{ IMX415_TCLKTRAIL, 0x007F },
> >>> +	{ IMX415_TCLKZERO, 0x0237 },
> >>> +	{ IMX415_THSPREPARE, 0x0087 },
> >>> +	{ IMX415_THSZERO, 0x00EF },
> >>> +	{ IMX415_THSTRAIL, 0x0087 },
> >>> +	{ IMX415_THSEXIT, 0x00DF },
> >>> +	{ IMX415_TLPX, 0x006F },
> >>> +};
> >>> +
> >>> +/* all-pixel 4-lane 2376 Mbps 60 Hz mode */
> >>> +static const struct cci_reg_sequence imx415_mode_4_2376[] = {
> >>> +	{ IMX415_VMAX, 0x08CA },
> >>> +	{ IMX415_HMAX, 0x016E },
> >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> >>> +	{ IMX415_TCLKPOST, 0x00E7 },
> >>> +	{ IMX415_TCLKPREPARE, 0x008F },
> >>> +	{ IMX415_TCLKTRAIL, 0x008F },
> >>> +	{ IMX415_TCLKZERO, 0x027F },
> >>> +	{ IMX415_THSPREPARE, 0x0097 },
> >>> +	{ IMX415_THSZERO, 0x010F },
> >>> +	{ IMX415_THSTRAIL, 0x0097 },
> >>> +	{ IMX415_THSEXIT, 0x00F7 },
> >>> +	{ IMX415_TLPX, 0x007F },
> >>> +};
> >>> +
> >>>  struct imx415_mode_reg_list {
> >>>  	u32 num_of_regs;
> >>>  	const struct cci_reg_sequence *regs;
> >>> @@ -536,6 +760,26 @@ struct imx415_mode {
> >>>
> >>>  /* mode configs */
> >>>  static const struct imx415_mode supported_modes[] = {
> >>> +	{
> >>> +		.lane_rate = 594000000,
> >>> +		.lanes = 2,
> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 99000000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_594),
> >>> +			.regs = imx415_mode_2_594,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 891000000,
> >>> +		.lanes = 2,
> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 148500000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_891),
> >>> +			.regs = imx415_mode_2_891,
> >>> +		},
> >>> +	},
> >>>  	{
> >>>  		.lane_rate = 720000000,
> >>>  		.lanes = 2,
> >>> @@ -547,6 +791,24 @@ static const struct imx415_mode supported_modes[] = {
> >>>  		},
> >>>  	},
> >>>  	{
> >>> +		.lane_rate = 1782000000,
> >>> +		.lanes = 2,
> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 297000000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_1782),
> >>> +			.regs = imx415_mode_2_1782,
> >>> +		},
> >>> +	},	{
> >>> +		.lane_rate = 2079000000,
> >>> +		.lanes = 2,
> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 304615385,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_2079),
> >>> +			.regs = imx415_mode_2_2079,
> >>> +		},
> >>> +	},	{
> >>>  		.lane_rate = 1440000000,
> >>>  		.lanes = 2,
> >>>  		.hmax_pix = 4510,
> >>> @@ -556,6 +818,46 @@ static const struct imx415_mode supported_modes[] = {
> >>>  			.regs = imx415_mode_2_1440,
> >>>  		},
> >>>  	},
> >>> +	{
> >>> +		.lane_rate = 594000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 5500,
> >>> +		.pixel_rate = 247500000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_594_20fps),
> >>> +			.regs = imx415_mode_4_594_20fps,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 594000000,
> >>> +		.lanes = 4,
> >>
> >> The mode is selected from the number of data lanes and the lane rate.
> >> They're the same as the previous entry, so this entry will never be
> >> selected. Same below.
> > 
> > I noticed that as well. The datasheet lists different FPS for the same link 
> > frequency / lane combination, only HMAX being different. Right now HMAX/VMAX 
> > is fixed, so is FPS.
> > I am aware there is no way to select between these modes, but I added them for 
> > completeness.
> 
> I'd prefer to only add common and tested modes. We have to keep in mind
> that in future we may want to add more features as 12 bit support or
> HDR. Adding all modes could make this more complex.

More than that, it would also be good to start computing parameters
dynamically instead of adding lots of hardcoded values. The
IMX415_LANEMODE register value in the cci_reg_sequence arrays is a
low-hanging fruit, the register can be programmed from the number of
lanes. The CSI-2 timings would also benefit from being computed
dynamically based on the lane rate. Dynamic calculation of the HMAX and
VMAX values to achieve a particular default frame rate should be
possible too, but more importantly, they should be configurable from
userspace too.

> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 247500000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_594_25fps),
> >>> +			.regs = imx415_mode_4_594_25fps,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 720000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 247500000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_720_25fps),
> >>> +			.regs = imx415_mode_4_720_25fps,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 720000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 4510,
> >>> +		.pixel_rate = 304615385,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_720_30fps),
> >>> +			.regs = imx415_mode_4_720_30fps,
> >>> +		},
> >>> +	},
> >>>  	{
> >>>  		.lane_rate = 891000000,
> >>>  		.lanes = 4,
> >>> @@ -566,6 +868,66 @@ static const struct imx415_mode supported_modes[] = {
> >>>  			.regs = imx415_mode_4_891,
> >>>  		},
> >>>  	},
> >>> +	{
> >>> +		.lane_rate = 1440000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 4510,
> >>> +		.pixel_rate = 304615385,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1440_30fps),
> >>> +			.regs = imx415_mode_4_1440_30fps,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 1440000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 4510,
> >>> +		.pixel_rate = 609230769,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1440_60fps),
> >>> +			.regs = imx415_mode_4_1440_60fps,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 1485000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 594000000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1485),
> >>> +			.regs = imx415_mode_4_1485,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 1782000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 594000000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1782),
> >>> +			.regs = imx415_mode_4_1782,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 2079000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 4400,
> >>> +		.pixel_rate = 594000000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2079),
> >>> +			.regs = imx415_mode_4_2079,
> >>> +		},
> >>> +	},
> >>> +	{
> >>> +		.lane_rate = 12376000000,
> >>> +		.lanes = 4,
> >>> +		.hmax_pix = 4392,
> >>> +		.pixel_rate = 891000000,
> >>> +		.reg_list = {
> >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2376),
> >>> +			.regs = imx415_mode_4_2376,
> >>> +		},
> >>> +	},
> >>>  };
> >>>  
> >>>  static const char *const imx415_test_pattern_menu[] = {

-- 
Regards,

Laurent Pinchart

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers
  2023-12-05  9:05 ` [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers Alexander Stein
@ 2023-12-05 19:24   ` kernel test robot
  2023-12-07 19:30   ` kernel test robot
  2023-12-07 21:02   ` Sakari Ailus
  2 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2023-12-05 19:24 UTC (permalink / raw)
  To: Alexander Stein, Mauro Carvalho Chehab, Michael Riesch,
	Sakari Ailus, Laurent Pinchart, Gerald Loacker
  Cc: llvm, oe-kbuild-all, linux-media, Alexander Stein

Hi Alexander,

kernel test robot noticed the following build errors:

[auto build test ERROR on media-tree/master]
[also build test ERROR on linuxtv-media-stage/master linus/master v6.7-rc4 next-20231205]
[cannot apply to sailus-media-tree/streams]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Alexander-Stein/media-i2c-imx415-Convert-to-new-CCI-register-access-helpers/20231205-170736
base:   git://linuxtv.org/media_tree.git master
patch link:    https://lore.kernel.org/r/20231205090557.298680-2-alexander.stein%40ew.tq-group.com
patch subject: [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers
config: arm-randconfig-002-20231206 (https://download.01.org/0day-ci/archive/20231206/202312060301.eWnbiFAk-lkp@intel.com/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project.git 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231206/202312060301.eWnbiFAk-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312060301.eWnbiFAk-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/media/i2c/imx415.c:119:16: error: call to undeclared function 'CCI_REG16_LE'; ISO C99 and later do not support implicit function declarations [-Werror,-Wimplicit-function-declaration]
                   .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
                                ^
   drivers/media/i2c/imx415.c:41:30: note: expanded from macro 'IMX415_BCWAIT_TIME'
   #define IMX415_BCWAIT_TIME        CCI_REG16_LE(0x3008)
                                     ^
   drivers/media/i2c/imx415.c:119:16: error: initializer element is not a compile-time constant
                   .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
                                ^~~~~~~~~~~~~~~~~~
   drivers/media/i2c/imx415.c:41:30: note: expanded from macro 'IMX415_BCWAIT_TIME'
   #define IMX415_BCWAIT_TIME        CCI_REG16_LE(0x3008)
                                     ^~~~~~~~~~~~~~~~~~~~
>> drivers/media/i2c/imx415.c:195:4: error: call to undeclared function 'CCI_REG24_LE'; ISO C99 and later do not support implicit function declarations [-Werror,-Wimplicit-function-declaration]
           { IMX415_VMAX, 0x08CA },
             ^
   drivers/media/i2c/imx415.c:53:24: note: expanded from macro 'IMX415_VMAX'
   #define IMX415_VMAX               CCI_REG24_LE(0x3024)
                                     ^
   drivers/media/i2c/imx415.c:195:4: error: initializer element is not a compile-time constant
           { IMX415_VMAX, 0x08CA },
             ^~~~~~~~~~~
   drivers/media/i2c/imx415.c:53:24: note: expanded from macro 'IMX415_VMAX'
   #define IMX415_VMAX               CCI_REG24_LE(0x3024)
                                     ^~~~~~~~~~~~~~~~~~~~
   drivers/media/i2c/imx415.c:211:4: error: initializer element is not a compile-time constant
           { IMX415_VMAX, 0x08CA },
             ^~~~~~~~~~~
   drivers/media/i2c/imx415.c:53:24: note: expanded from macro 'IMX415_VMAX'
   #define IMX415_VMAX               CCI_REG24_LE(0x3024)
                                     ^~~~~~~~~~~~~~~~~~~~
   drivers/media/i2c/imx415.c:227:4: error: initializer element is not a compile-time constant
           { IMX415_VMAX, 0x08CA },
             ^~~~~~~~~~~
   drivers/media/i2c/imx415.c:53:24: note: expanded from macro 'IMX415_VMAX'
   #define IMX415_VMAX               CCI_REG24_LE(0x3024)
                                     ^~~~~~~~~~~~~~~~~~~~
   6 errors generated.


vim +/CCI_REG16_LE +119 drivers/media/i2c/imx415.c

14cd15e7a1e2a3 Gerald Loacker  2023-01-30   31  
a13751ef748a7a Alexander Stein 2023-12-05   32  #define IMX415_MODE		  CCI_REG8(0x3000)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   33  #define IMX415_MODE_OPERATING	  (0)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   34  #define IMX415_MODE_STANDBY	  BIT(0)
a13751ef748a7a Alexander Stein 2023-12-05   35  #define IMX415_REGHOLD		  CCI_REG8(0x3001)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   36  #define IMX415_REGHOLD_INVALID	  (0)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   37  #define IMX415_REGHOLD_VALID	  BIT(0)
a13751ef748a7a Alexander Stein 2023-12-05   38  #define IMX415_XMSTA		  CCI_REG8(0x3002)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   39  #define IMX415_XMSTA_START	  (0)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   40  #define IMX415_XMSTA_STOP	  BIT(0)
a13751ef748a7a Alexander Stein 2023-12-05  @41  #define IMX415_BCWAIT_TIME	  CCI_REG16_LE(0x3008)
a13751ef748a7a Alexander Stein 2023-12-05   42  #define IMX415_CPWAIT_TIME	  CCI_REG16_LE(0x300A)
a13751ef748a7a Alexander Stein 2023-12-05   43  #define IMX415_WINMODE		  CCI_REG8(0x301C)
a13751ef748a7a Alexander Stein 2023-12-05   44  #define IMX415_ADDMODE		  CCI_REG8(0x3022)
a13751ef748a7a Alexander Stein 2023-12-05   45  #define IMX415_REVERSE		  CCI_REG8(0x3030)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   46  #define IMX415_HREVERSE_SHIFT	  (0)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   47  #define IMX415_VREVERSE_SHIFT	  BIT(0)
a13751ef748a7a Alexander Stein 2023-12-05   48  #define IMX415_ADBIT		  CCI_REG8(0x3031)
a13751ef748a7a Alexander Stein 2023-12-05   49  #define IMX415_MDBIT		  CCI_REG8(0x3032)
a13751ef748a7a Alexander Stein 2023-12-05   50  #define IMX415_SYS_MODE		  CCI_REG8(0x3033)
a13751ef748a7a Alexander Stein 2023-12-05   51  #define IMX415_OUTSEL		  CCI_REG8(0x30C0)
a13751ef748a7a Alexander Stein 2023-12-05   52  #define IMX415_DRV		  CCI_REG8(0x30C1)
a13751ef748a7a Alexander Stein 2023-12-05   53  #define IMX415_VMAX		  CCI_REG24_LE(0x3024)
a13751ef748a7a Alexander Stein 2023-12-05   54  #define IMX415_HMAX		  CCI_REG16_LE(0x3028)
a13751ef748a7a Alexander Stein 2023-12-05   55  #define IMX415_SHR0		  CCI_REG24_LE(0x3050)
a13751ef748a7a Alexander Stein 2023-12-05   56  #define IMX415_GAIN_PCG_0	  CCI_REG16_LE(0x3090)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   57  #define IMX415_AGAIN_MIN	  0
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   58  #define IMX415_AGAIN_MAX	  100
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   59  #define IMX415_AGAIN_STEP	  1
a13751ef748a7a Alexander Stein 2023-12-05   60  #define IMX415_BLKLEVEL		  CCI_REG16_LE(0x30E2)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   61  #define IMX415_BLKLEVEL_DEFAULT	  50
a13751ef748a7a Alexander Stein 2023-12-05   62  #define IMX415_TPG_EN_DUOUT	  CCI_REG8(0x30E4)
a13751ef748a7a Alexander Stein 2023-12-05   63  #define IMX415_TPG_PATSEL_DUOUT	  CCI_REG8(0x30E6)
a13751ef748a7a Alexander Stein 2023-12-05   64  #define IMX415_TPG_COLORWIDTH	  CCI_REG8(0x30E8)
a13751ef748a7a Alexander Stein 2023-12-05   65  #define IMX415_TESTCLKEN_MIPI	  CCI_REG8(0x3110)
a13751ef748a7a Alexander Stein 2023-12-05   66  #define IMX415_INCKSEL1		  CCI_REG8(0x3115)
a13751ef748a7a Alexander Stein 2023-12-05   67  #define IMX415_INCKSEL2		  CCI_REG8(0x3116)
a13751ef748a7a Alexander Stein 2023-12-05   68  #define IMX415_INCKSEL3		  CCI_REG16_LE(0x3118)
a13751ef748a7a Alexander Stein 2023-12-05   69  #define IMX415_INCKSEL4		  CCI_REG16_LE(0x311A)
a13751ef748a7a Alexander Stein 2023-12-05   70  #define IMX415_INCKSEL5		  CCI_REG8(0x311E)
a13751ef748a7a Alexander Stein 2023-12-05   71  #define IMX415_DIG_CLP_MODE	  CCI_REG8(0x32C8)
a13751ef748a7a Alexander Stein 2023-12-05   72  #define IMX415_WRJ_OPEN		  CCI_REG8(0x3390)
a13751ef748a7a Alexander Stein 2023-12-05   73  #define IMX415_SENSOR_INFO	  CCI_REG16_LE(0x3F12)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   74  #define IMX415_SENSOR_INFO_MASK	  0xFFF
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   75  #define IMX415_CHIP_ID		  0x514
a13751ef748a7a Alexander Stein 2023-12-05   76  #define IMX415_LANEMODE		  CCI_REG16_LE(0x4001)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   77  #define IMX415_LANEMODE_2	  1
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   78  #define IMX415_LANEMODE_4	  3
a13751ef748a7a Alexander Stein 2023-12-05   79  #define IMX415_TXCLKESC_FREQ	  CCI_REG16_LE(0x4004)
a13751ef748a7a Alexander Stein 2023-12-05   80  #define IMX415_INCKSEL6		  CCI_REG8(0x400C)
a13751ef748a7a Alexander Stein 2023-12-05   81  #define IMX415_TCLKPOST		  CCI_REG16_LE(0x4018)
a13751ef748a7a Alexander Stein 2023-12-05   82  #define IMX415_TCLKPREPARE	  CCI_REG16_LE(0x401A)
a13751ef748a7a Alexander Stein 2023-12-05   83  #define IMX415_TCLKTRAIL	  CCI_REG16_LE(0x401C)
a13751ef748a7a Alexander Stein 2023-12-05   84  #define IMX415_TCLKZERO		  CCI_REG16_LE(0x401E)
a13751ef748a7a Alexander Stein 2023-12-05   85  #define IMX415_THSPREPARE	  CCI_REG16_LE(0x4020)
a13751ef748a7a Alexander Stein 2023-12-05   86  #define IMX415_THSZERO		  CCI_REG16_LE(0x4022)
a13751ef748a7a Alexander Stein 2023-12-05   87  #define IMX415_THSTRAIL		  CCI_REG16_LE(0x4024)
a13751ef748a7a Alexander Stein 2023-12-05   88  #define IMX415_THSEXIT		  CCI_REG16_LE(0x4026)
a13751ef748a7a Alexander Stein 2023-12-05   89  #define IMX415_TLPX		  CCI_REG16_LE(0x4028)
a13751ef748a7a Alexander Stein 2023-12-05   90  #define IMX415_INCKSEL7		  CCI_REG8(0x4074)
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   91  
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   92  static const char *const imx415_supply_names[] = {
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   93  	"dvdd",
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   94  	"ovdd",
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   95  	"avdd",
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   96  };
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   97  
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   98  /*
14cd15e7a1e2a3 Gerald Loacker  2023-01-30   99   * The IMX415 data sheet uses lane rates but v4l2 uses link frequency to
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  100   * describe MIPI CSI-2 speed. This driver uses lane rates wherever possible
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  101   * and converts them to link frequencies by a factor of two when needed.
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  102   */
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  103  static const s64 link_freq_menu_items[] = {
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  104  	594000000 / 2,	720000000 / 2,	891000000 / 2,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  105  	1440000000 / 2, 1485000000 / 2,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  106  };
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  107  
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  108  struct imx415_clk_params {
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  109  	u64 lane_rate;
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  110  	u64 inck;
a13751ef748a7a Alexander Stein 2023-12-05  111  	struct cci_reg_sequence regs[IMX415_NUM_CLK_PARAM_REGS];
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  112  };
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  113  
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  114  /* INCK Settings - includes all lane rate and INCK dependent registers */
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  115  static const struct imx415_clk_params imx415_clk_params[] = {
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  116  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  117  		.lane_rate = 594000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  118  		.inck = 27000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30 @119  		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  120  		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  121  		.regs[2] = { IMX415_SYS_MODE, 0x7 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  122  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  123  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  124  		.regs[5] = { IMX415_INCKSEL3, 0x084 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  125  		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  126  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  127  		.regs[8] = { IMX415_INCKSEL6, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  128  		.regs[9] = { IMX415_INCKSEL7, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  129  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  130  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  131  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  132  		.lane_rate = 720000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  133  		.inck = 24000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  134  		.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  135  		.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  136  		.regs[2] = { IMX415_SYS_MODE, 0x9 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  137  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  138  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  139  		.regs[5] = { IMX415_INCKSEL3, 0x0B4 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  140  		.regs[6] = { IMX415_INCKSEL4, 0x0FC },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  141  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  142  		.regs[8] = { IMX415_INCKSEL6, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  143  		.regs[9] = { IMX415_INCKSEL7, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  144  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  145  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  146  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  147  		.lane_rate = 891000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  148  		.inck = 27000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  149  		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  150  		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  151  		.regs[2] = { IMX415_SYS_MODE, 0x5 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  152  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  153  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  154  		.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  155  		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  156  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  157  		.regs[8] = { IMX415_INCKSEL6, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  158  		.regs[9] = { IMX415_INCKSEL7, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  159  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  160  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  161  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  162  		.lane_rate = 1440000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  163  		.inck = 24000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  164  		.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  165  		.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  166  		.regs[2] = { IMX415_SYS_MODE, 0x8 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  167  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  168  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  169  		.regs[5] = { IMX415_INCKSEL3, 0x0B4 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  170  		.regs[6] = { IMX415_INCKSEL4, 0x0FC },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  171  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  172  		.regs[8] = { IMX415_INCKSEL6, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  173  		.regs[9] = { IMX415_INCKSEL7, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  174  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  175  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  176  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  177  		.lane_rate = 1485000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  178  		.inck = 27000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  179  		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  180  		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  181  		.regs[2] = { IMX415_SYS_MODE, 0x8 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  182  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  183  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  184  		.regs[5] = { IMX415_INCKSEL3, 0x0A5 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  185  		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  186  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  187  		.regs[8] = { IMX415_INCKSEL6, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  188  		.regs[9] = { IMX415_INCKSEL7, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  189  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  190  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  191  };
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  192  
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  193  /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
a13751ef748a7a Alexander Stein 2023-12-05  194  static const struct cci_reg_sequence imx415_mode_2_720[] = {
14cd15e7a1e2a3 Gerald Loacker  2023-01-30 @195  	{ IMX415_VMAX, 0x08CA },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  196  	{ IMX415_HMAX, 0x07F0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  197  	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  198  	{ IMX415_TCLKPOST, 0x006F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  199  	{ IMX415_TCLKPREPARE, 0x002F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  200  	{ IMX415_TCLKTRAIL, 0x002F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  201  	{ IMX415_TCLKZERO, 0x00BF },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  202  	{ IMX415_THSPREPARE, 0x002F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  203  	{ IMX415_THSZERO, 0x0057 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  204  	{ IMX415_THSTRAIL, 0x002F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  205  	{ IMX415_THSEXIT, 0x004F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  206  	{ IMX415_TLPX, 0x0027 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  207  };
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  208  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 3/3] media: i2c: imx415: Add more supported modes
  2023-12-05 14:54         ` Laurent Pinchart
@ 2023-12-06  7:38           ` Alexander Stein
  0 siblings, 0 replies; 15+ messages in thread
From: Alexander Stein @ 2023-12-06  7:38 UTC (permalink / raw)
  To: Gerald Loacker, Laurent Pinchart
  Cc: Mauro Carvalho Chehab, Michael Riesch, Sakari Ailus, linux-media

Hi,

Am Dienstag, 5. Dezember 2023, 15:54:35 CET schrieb Laurent Pinchart:
> Hello,
> 
> On Tue, Dec 05, 2023 at 03:47:15PM +0100, Gerald Loacker wrote:
> > Am 05.12.2023 um 12:12 schrieb Alexander Stein:
> > > Am Dienstag, 5. Dezember 2023, 11:45:09 CET schrieb Laurent Pinchart:
> > >> On Tue, Dec 05, 2023 at 10:05:57AM +0100, Alexander Stein wrote:
> > >>> These modes are listed in section "All-pixel mode" of the datasheet
> > >>> IMX415-AAQR-C (Rev. E19504, 2019/05/21).
> > >>> hmax_pix and pixel_rate are taken from the comment above the mode
> > >>> list.
> > >>> 
> > >>> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > >>> ---
> > >>> 
> > >>>  drivers/media/i2c/imx415.c | 362
> > >>>  +++++++++++++++++++++++++++++++++++++
> > >>>  1 file changed, 362 insertions(+)
> > >>> 
> > >>> diff --git a/drivers/media/i2c/imx415.c b/drivers/media/i2c/imx415.c
> > >>> index a222b9134aa2..48b8ae6d790d 100644
> > >>> --- a/drivers/media/i2c/imx415.c
> > >>> +++ b/drivers/media/i2c/imx415.c
> > >>> @@ -445,6 +445,38 @@ static const struct imx415_clk_params
> > >>> imx415_clk_params[] = {> >>> 
> > >>>  	},
> > >>>  
> > >>>  };
> > >>> 
> > >>> +/* all-pixel 2-lane 594 Mbps 10 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_2_594[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0CE4 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> > >>> +	{ IMX415_TCLKPOST, 0x0067 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0027 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x0027 },
> > >>> +	{ IMX415_TCLKZERO, 0x00B7 },
> > >>> +	{ IMX415_THSPREPARE, 0x002F },
> > >>> +	{ IMX415_THSZERO, 0x004F },
> > >>> +	{ IMX415_THSTRAIL, 0x002F },
> > >>> +	{ IMX415_THSEXIT, 0x0047 },
> > >>> +	{ IMX415_TLPX, 0x0027 },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 2-lane 891 Mbps 15 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_2_891[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0898 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> > >>> +	{ IMX415_TCLKPOST, 0x007F },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0037 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x0037 },
> > >>> +	{ IMX415_TCLKZERO, 0x00F7 },
> > >>> +	{ IMX415_THSPREPARE, 0x003F },
> > >>> +	{ IMX415_THSZERO, 0x006F },
> > >>> +	{ IMX415_THSTRAIL, 0x003F },
> > >>> +	{ IMX415_THSEXIT, 0x005F },
> > >>> +	{ IMX415_TLPX, 0x002F },
> > >>> +};
> > >>> +
> > >>> 
> > >>>  /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
> > >>>  static const struct cci_reg_sequence imx415_mode_2_720[] = {
> > >>>  
> > >>>  	{ IMX415_VMAX, 0x08CA },
> > >>> 
> > >>> @@ -461,6 +493,38 @@ static const struct cci_reg_sequence
> > >>> imx415_mode_2_720[] = {> >>> 
> > >>>  	{ IMX415_TLPX, 0x0027 },
> > >>>  
> > >>>  };
> > >>> 
> > >>> +/* all-pixel 2-lane 1782 Mbps 30 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_2_1782[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x044C },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> > >>> +	{ IMX415_TCLKPOST, 0x00B7 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0067 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x006F },
> > >>> +	{ IMX415_TCLKZERO, 0x01DF },
> > >>> +	{ IMX415_THSPREPARE, 0x006F },
> > >>> +	{ IMX415_THSZERO, 0x00CF },
> > >>> +	{ IMX415_THSTRAIL, 0x006F },
> > >>> +	{ IMX415_THSEXIT, 0x00B7 },
> > >>> +	{ IMX415_TLPX, 0x005F },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 2-lane 2079 Mbps 30 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_2_2079[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x044C },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
> > >>> +	{ IMX415_TCLKPOST, 0x00D7 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x007F },
> > >>> +	{ IMX415_TCLKTRAIL, 0x007F },
> > >>> +	{ IMX415_TCLKZERO, 0x0237 },
> > >>> +	{ IMX415_THSPREPARE, 0x0087 },
> > >>> +	{ IMX415_THSZERO, 0x00EF },
> > >>> +	{ IMX415_THSTRAIL, 0x0087 },
> > >>> +	{ IMX415_THSEXIT, 0x00DF },
> > >>> +	{ IMX415_TLPX, 0x006F },
> > >>> +};
> > >>> +
> > >>> 
> > >>>  /* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */
> > >>>  static const struct cci_reg_sequence imx415_mode_2_1440[] = {
> > >>>  
> > >>>  	{ IMX415_VMAX, 0x08CA },
> > >>> 
> > >>> @@ -477,6 +541,70 @@ static const struct cci_reg_sequence
> > >>> imx415_mode_2_1440[] = {> >>> 
> > >>>  	{ IMX415_TLPX, 0x004F },
> > >>>  
> > >>>  };
> > >>> 
> > >>> +/* all-pixel 4-lane 594 Mbps 20 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_594_20fps[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0672 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x0067 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0027 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x0027 },
> > >>> +	{ IMX415_TCLKZERO, 0x00B7 },
> > >>> +	{ IMX415_THSPREPARE, 0x002F },
> > >>> +	{ IMX415_THSZERO, 0x004F },
> > >>> +	{ IMX415_THSTRAIL, 0x002F },
> > >>> +	{ IMX415_THSEXIT, 0x0047 },
> > >>> +	{ IMX415_TLPX, 0x0027 },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 4-lane 594 Mbps 25 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_594_25fps[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0528 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x0067 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0027 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x0027 },
> > >>> +	{ IMX415_TCLKZERO, 0x00B7 },
> > >>> +	{ IMX415_THSPREPARE, 0x002F },
> > >>> +	{ IMX415_THSZERO, 0x004F },
> > >>> +	{ IMX415_THSTRAIL, 0x002F },
> > >>> +	{ IMX415_THSEXIT, 0x0047 },
> > >>> +	{ IMX415_TLPX, 0x0027 },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 4-lane 720 Mbps 25 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_720_25fps[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0500 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x006F },
> > >>> +	{ IMX415_TCLKPREPARE, 0x002F },
> > >>> +	{ IMX415_TCLKTRAIL, 0x002F },
> > >>> +	{ IMX415_TCLKZERO, 0x00BF },
> > >>> +	{ IMX415_THSPREPARE, 0x002F },
> > >>> +	{ IMX415_THSZERO, 0x0057 },
> > >>> +	{ IMX415_THSTRAIL, 0x002F },
> > >>> +	{ IMX415_THSEXIT, 0x004F },
> > >>> +	{ IMX415_TLPX, 0x0027 },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 4-lane 720 Mbps 30.01 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_720_30fps[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x042A },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x006F },
> > >>> +	{ IMX415_TCLKPREPARE, 0x002F },
> > >>> +	{ IMX415_TCLKTRAIL, 0x002F },
> > >>> +	{ IMX415_TCLKZERO, 0x00BF },
> > >>> +	{ IMX415_THSPREPARE, 0x002F },
> > >>> +	{ IMX415_THSZERO, 0x0057 },
> > >>> +	{ IMX415_THSTRAIL, 0x002F },
> > >>> +	{ IMX415_THSEXIT, 0x004F },
> > >>> +	{ IMX415_TLPX, 0x0027 },
> > >>> +};
> > >>> +
> > >>> 
> > >>>  /* all-pixel 4-lane 891 Mbps 30 Hz mode */
> > >>>  static const struct cci_reg_sequence imx415_mode_4_891[] = {
> > >>>  
> > >>>  	{ IMX415_VMAX, 0x08CA },
> > >>> 
> > >>> @@ -493,6 +621,102 @@ static const struct cci_reg_sequence
> > >>> imx415_mode_4_891[] = {> >>> 
> > >>>  	{ IMX415_TLPX, 0x002F },
> > >>>  
> > >>>  };
> > >>> 
> > >>> +/* all-pixel 4-lane 1440 Mbps 30.01 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_1440_30fps[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x042A },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x009F },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0057 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x0057 },
> > >>> +	{ IMX415_TCLKZERO, 0x0187 },
> > >>> +	{ IMX415_THSPREPARE, 0x005F },
> > >>> +	{ IMX415_THSZERO, 0x00A7 },
> > >>> +	{ IMX415_THSTRAIL, 0x005F },
> > >>> +	{ IMX415_THSEXIT, 0x0097 },
> > >>> +	{ IMX415_TLPX, 0x004F },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 4-lane 1440 Mbps 60.03 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_1440_60fps[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0215 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x009F },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0057 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x0057 },
> > >>> +	{ IMX415_TCLKZERO, 0x0187 },
> > >>> +	{ IMX415_THSPREPARE, 0x005F },
> > >>> +	{ IMX415_THSZERO, 0x00A7 },
> > >>> +	{ IMX415_THSTRAIL, 0x005F },
> > >>> +	{ IMX415_THSEXIT, 0x0097 },
> > >>> +	{ IMX415_TLPX, 0x004F },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 4-lane 1485 Mbps 60 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_1485[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0226 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x00A7 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0057 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x005F },
> > >>> +	{ IMX415_TCLKZERO, 0x0197 },
> > >>> +	{ IMX415_THSPREPARE, 0x005F },
> > >>> +	{ IMX415_THSZERO, 0x00AF },
> > >>> +	{ IMX415_THSTRAIL, 0x005F },
> > >>> +	{ IMX415_THSEXIT, 0x009F },
> > >>> +	{ IMX415_TLPX, 0x004F },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 4-lane 1782 Mbps 60 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_1782[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0226 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x00B7 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x0067 },
> > >>> +	{ IMX415_TCLKTRAIL, 0x006F },
> > >>> +	{ IMX415_TCLKZERO, 0x01DF },
> > >>> +	{ IMX415_THSPREPARE, 0x006F },
> > >>> +	{ IMX415_THSZERO, 0x00CF },
> > >>> +	{ IMX415_THSTRAIL, 0x006F },
> > >>> +	{ IMX415_THSEXIT, 0x00B7 },
> > >>> +	{ IMX415_TLPX, 0x005F },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 4-lane 2079 Mbps 60 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_2079[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x0226 },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x00D7 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x007F },
> > >>> +	{ IMX415_TCLKTRAIL, 0x007F },
> > >>> +	{ IMX415_TCLKZERO, 0x0237 },
> > >>> +	{ IMX415_THSPREPARE, 0x0087 },
> > >>> +	{ IMX415_THSZERO, 0x00EF },
> > >>> +	{ IMX415_THSTRAIL, 0x0087 },
> > >>> +	{ IMX415_THSEXIT, 0x00DF },
> > >>> +	{ IMX415_TLPX, 0x006F },
> > >>> +};
> > >>> +
> > >>> +/* all-pixel 4-lane 2376 Mbps 60 Hz mode */
> > >>> +static const struct cci_reg_sequence imx415_mode_4_2376[] = {
> > >>> +	{ IMX415_VMAX, 0x08CA },
> > >>> +	{ IMX415_HMAX, 0x016E },
> > >>> +	{ IMX415_LANEMODE, IMX415_LANEMODE_4 },
> > >>> +	{ IMX415_TCLKPOST, 0x00E7 },
> > >>> +	{ IMX415_TCLKPREPARE, 0x008F },
> > >>> +	{ IMX415_TCLKTRAIL, 0x008F },
> > >>> +	{ IMX415_TCLKZERO, 0x027F },
> > >>> +	{ IMX415_THSPREPARE, 0x0097 },
> > >>> +	{ IMX415_THSZERO, 0x010F },
> > >>> +	{ IMX415_THSTRAIL, 0x0097 },
> > >>> +	{ IMX415_THSEXIT, 0x00F7 },
> > >>> +	{ IMX415_TLPX, 0x007F },
> > >>> +};
> > >>> +
> > >>> 
> > >>>  struct imx415_mode_reg_list {
> > >>>  
> > >>>  	u32 num_of_regs;
> > >>>  	const struct cci_reg_sequence *regs;
> > >>> 
> > >>> @@ -536,6 +760,26 @@ struct imx415_mode {
> > >>> 
> > >>>  /* mode configs */
> > >>>  static const struct imx415_mode supported_modes[] = {
> > >>> 
> > >>> +	{
> > >>> +		.lane_rate = 594000000,
> > >>> +		.lanes = 2,
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 99000000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_594),
> > >>> +			.regs = imx415_mode_2_594,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 891000000,
> > >>> +		.lanes = 2,
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 148500000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_891),
> > >>> +			.regs = imx415_mode_2_891,
> > >>> +		},
> > >>> +	},
> > >>> 
> > >>>  	{
> > >>>  	
> > >>>  		.lane_rate = 720000000,
> > >>>  		.lanes = 2,
> > >>> 
> > >>> @@ -547,6 +791,24 @@ static const struct imx415_mode supported_modes[]
> > >>> = {
> > >>> 
> > >>>  		},
> > >>>  	
> > >>>  	},
> > >>>  	{
> > >>> 
> > >>> +		.lane_rate = 1782000000,
> > >>> +		.lanes = 2,
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 297000000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_1782),
> > >>> +			.regs = imx415_mode_2_1782,
> > >>> +		},
> > >>> +	},	{
> > >>> +		.lane_rate = 2079000000,
> > >>> +		.lanes = 2,
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 304615385,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_2_2079),
> > >>> +			.regs = imx415_mode_2_2079,
> > >>> +		},
> > >>> +	},	{
> > >>> 
> > >>>  		.lane_rate = 1440000000,
> > >>>  		.lanes = 2,
> > >>>  		.hmax_pix = 4510,
> > >>> 
> > >>> @@ -556,6 +818,46 @@ static const struct imx415_mode supported_modes[]
> > >>> = {
> > >>> 
> > >>>  			.regs = imx415_mode_2_1440,
> > >>>  		
> > >>>  		},
> > >>>  	
> > >>>  	},
> > >>> 
> > >>> +	{
> > >>> +		.lane_rate = 594000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 5500,
> > >>> +		.pixel_rate = 247500000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_594_20fps),
> > >>> +			.regs = imx415_mode_4_594_20fps,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 594000000,
> > >>> +		.lanes = 4,
> > >> 
> > >> The mode is selected from the number of data lanes and the lane rate.
> > >> They're the same as the previous entry, so this entry will never be
> > >> selected. Same below.
> > > 
> > > I noticed that as well. The datasheet lists different FPS for the same
> > > link
> > > frequency / lane combination, only HMAX being different. Right now
> > > HMAX/VMAX is fixed, so is FPS.
> > > I am aware there is no way to select between these modes, but I added
> > > them for completeness.
> > 
> > I'd prefer to only add common and tested modes. We have to keep in mind
> > that in future we may want to add more features as 12 bit support or
> > HDR. Adding all modes could make this more complex.
> 
> More than that, it would also be good to start computing parameters
> dynamically instead of adding lots of hardcoded values. The
> IMX415_LANEMODE register value in the cci_reg_sequence arrays is a
> low-hanging fruit, the register can be programmed from the number of
> lanes. The CSI-2 timings would also benefit from being computed
> dynamically based on the lane rate. Dynamic calculation of the HMAX and
> VMAX values to achieve a particular default frame rate should be
> possible too, but more importantly, they should be configurable from
> userspace too.

Fine by me. But I don't know when I will be able to do that.
Nevertheless patches 1 & 2 can be applied meanwhile, if there are no comments

Best regards,
Alexander

> 
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 247500000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_594_25fps),
> > >>> +			.regs = imx415_mode_4_594_25fps,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 720000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 247500000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_720_25fps),
> > >>> +			.regs = imx415_mode_4_720_25fps,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 720000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 4510,
> > >>> +		.pixel_rate = 304615385,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_720_30fps),
> > >>> +			.regs = imx415_mode_4_720_30fps,
> > >>> +		},
> > >>> +	},
> > >>> 
> > >>>  	{
> > >>>  	
> > >>>  		.lane_rate = 891000000,
> > >>>  		.lanes = 4,
> > >>> 
> > >>> @@ -566,6 +868,66 @@ static const struct imx415_mode supported_modes[]
> > >>> = {
> > >>> 
> > >>>  			.regs = imx415_mode_4_891,
> > >>>  		
> > >>>  		},
> > >>>  	
> > >>>  	},
> > >>> 
> > >>> +	{
> > >>> +		.lane_rate = 1440000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 4510,
> > >>> +		.pixel_rate = 304615385,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_1440_30fps),
> > >>> +			.regs = imx415_mode_4_1440_30fps,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 1440000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 4510,
> > >>> +		.pixel_rate = 609230769,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = 
ARRAY_SIZE(imx415_mode_4_1440_60fps),
> > >>> +			.regs = imx415_mode_4_1440_60fps,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 1485000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 594000000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1485),
> > >>> +			.regs = imx415_mode_4_1485,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 1782000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 594000000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_1782),
> > >>> +			.regs = imx415_mode_4_1782,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 2079000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 4400,
> > >>> +		.pixel_rate = 594000000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2079),
> > >>> +			.regs = imx415_mode_4_2079,
> > >>> +		},
> > >>> +	},
> > >>> +	{
> > >>> +		.lane_rate = 12376000000,
> > >>> +		.lanes = 4,
> > >>> +		.hmax_pix = 4392,
> > >>> +		.pixel_rate = 891000000,
> > >>> +		.reg_list = {
> > >>> +			.num_of_regs = ARRAY_SIZE(imx415_mode_4_2376),
> > >>> +			.regs = imx415_mode_4_2376,
> > >>> +		},
> > >>> +	},
> > >>> 
> > >>>  };
> > >>>  
> > >>>  static const char *const imx415_test_pattern_menu[] = {


-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
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^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers
  2023-12-05  9:05 ` [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers Alexander Stein
  2023-12-05 19:24   ` kernel test robot
@ 2023-12-07 19:30   ` kernel test robot
  2023-12-07 21:02   ` Sakari Ailus
  2 siblings, 0 replies; 15+ messages in thread
From: kernel test robot @ 2023-12-07 19:30 UTC (permalink / raw)
  To: Alexander Stein, Mauro Carvalho Chehab, Michael Riesch,
	Sakari Ailus, Laurent Pinchart, Gerald Loacker
  Cc: llvm, oe-kbuild-all, linux-media, Alexander Stein

Hi Alexander,

kernel test robot noticed the following build errors:

[auto build test ERROR on media-tree/master]
[also build test ERROR on linuxtv-media-stage/master linus/master v6.7-rc4 next-20231207]
[cannot apply to sailus-media-tree/streams]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Alexander-Stein/media-i2c-imx415-Convert-to-new-CCI-register-access-helpers/20231205-170736
base:   git://linuxtv.org/media_tree.git master
patch link:    https://lore.kernel.org/r/20231205090557.298680-2-alexander.stein%40ew.tq-group.com
patch subject: [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers
config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20231208/202312080321.6wjzIYcj-lkp@intel.com/config)
compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231208/202312080321.6wjzIYcj-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312080321.6wjzIYcj-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/media/i2c/imx415.c:119:16: error: call to undeclared function 'CCI_REG16_LE'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
                   .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
                                ^
   drivers/media/i2c/imx415.c:41:30: note: expanded from macro 'IMX415_BCWAIT_TIME'
   #define IMX415_BCWAIT_TIME        CCI_REG16_LE(0x3008)
                                     ^
>> drivers/media/i2c/imx415.c:119:16: error: initializer element is not a compile-time constant
                   .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
                                ^~~~~~~~~~~~~~~~~~
   drivers/media/i2c/imx415.c:41:30: note: expanded from macro 'IMX415_BCWAIT_TIME'
   #define IMX415_BCWAIT_TIME        CCI_REG16_LE(0x3008)
                                     ^~~~~~~~~~~~~~~~~~~~
>> drivers/media/i2c/imx415.c:195:4: error: call to undeclared function 'CCI_REG24_LE'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
           { IMX415_VMAX, 0x08CA },
             ^
   drivers/media/i2c/imx415.c:53:24: note: expanded from macro 'IMX415_VMAX'
   #define IMX415_VMAX               CCI_REG24_LE(0x3024)
                                     ^
   drivers/media/i2c/imx415.c:195:4: error: initializer element is not a compile-time constant
           { IMX415_VMAX, 0x08CA },
             ^~~~~~~~~~~
   drivers/media/i2c/imx415.c:53:24: note: expanded from macro 'IMX415_VMAX'
   #define IMX415_VMAX               CCI_REG24_LE(0x3024)
                                     ^~~~~~~~~~~~~~~~~~~~
   drivers/media/i2c/imx415.c:211:4: error: initializer element is not a compile-time constant
           { IMX415_VMAX, 0x08CA },
             ^~~~~~~~~~~
   drivers/media/i2c/imx415.c:53:24: note: expanded from macro 'IMX415_VMAX'
   #define IMX415_VMAX               CCI_REG24_LE(0x3024)
                                     ^~~~~~~~~~~~~~~~~~~~
   drivers/media/i2c/imx415.c:227:4: error: initializer element is not a compile-time constant
           { IMX415_VMAX, 0x08CA },
             ^~~~~~~~~~~
   drivers/media/i2c/imx415.c:53:24: note: expanded from macro 'IMX415_VMAX'
   #define IMX415_VMAX               CCI_REG24_LE(0x3024)
                                     ^~~~~~~~~~~~~~~~~~~~
   6 errors generated.


vim +/CCI_REG16_LE +119 drivers/media/i2c/imx415.c

14cd15e7a1e2a3 Gerald Loacker  2023-01-30  113  
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  114  /* INCK Settings - includes all lane rate and INCK dependent registers */
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  115  static const struct imx415_clk_params imx415_clk_params[] = {
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  116  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  117  		.lane_rate = 594000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  118  		.inck = 27000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30 @119  		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  120  		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  121  		.regs[2] = { IMX415_SYS_MODE, 0x7 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  122  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  123  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  124  		.regs[5] = { IMX415_INCKSEL3, 0x084 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  125  		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  126  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  127  		.regs[8] = { IMX415_INCKSEL6, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  128  		.regs[9] = { IMX415_INCKSEL7, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  129  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  130  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  131  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  132  		.lane_rate = 720000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  133  		.inck = 24000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  134  		.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  135  		.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  136  		.regs[2] = { IMX415_SYS_MODE, 0x9 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  137  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  138  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  139  		.regs[5] = { IMX415_INCKSEL3, 0x0B4 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  140  		.regs[6] = { IMX415_INCKSEL4, 0x0FC },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  141  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  142  		.regs[8] = { IMX415_INCKSEL6, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  143  		.regs[9] = { IMX415_INCKSEL7, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  144  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  145  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  146  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  147  		.lane_rate = 891000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  148  		.inck = 27000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  149  		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  150  		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  151  		.regs[2] = { IMX415_SYS_MODE, 0x5 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  152  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  153  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  154  		.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  155  		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  156  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  157  		.regs[8] = { IMX415_INCKSEL6, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  158  		.regs[9] = { IMX415_INCKSEL7, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  159  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  160  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  161  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  162  		.lane_rate = 1440000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  163  		.inck = 24000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  164  		.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  165  		.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  166  		.regs[2] = { IMX415_SYS_MODE, 0x8 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  167  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  168  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  169  		.regs[5] = { IMX415_INCKSEL3, 0x0B4 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  170  		.regs[6] = { IMX415_INCKSEL4, 0x0FC },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  171  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  172  		.regs[8] = { IMX415_INCKSEL6, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  173  		.regs[9] = { IMX415_INCKSEL7, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  174  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  175  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  176  	{
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  177  		.lane_rate = 1485000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  178  		.inck = 27000000,
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  179  		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  180  		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  181  		.regs[2] = { IMX415_SYS_MODE, 0x8 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  182  		.regs[3] = { IMX415_INCKSEL1, 0x00 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  183  		.regs[4] = { IMX415_INCKSEL2, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  184  		.regs[5] = { IMX415_INCKSEL3, 0x0A5 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  185  		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  186  		.regs[7] = { IMX415_INCKSEL5, 0x23 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  187  		.regs[8] = { IMX415_INCKSEL6, 0x1 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  188  		.regs[9] = { IMX415_INCKSEL7, 0x0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  189  		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  190  	},
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  191  };
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  192  
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  193  /* all-pixel 2-lane 720 Mbps 15.74 Hz mode */
a13751ef748a7a Alexander Stein 2023-12-05  194  static const struct cci_reg_sequence imx415_mode_2_720[] = {
14cd15e7a1e2a3 Gerald Loacker  2023-01-30 @195  	{ IMX415_VMAX, 0x08CA },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  196  	{ IMX415_HMAX, 0x07F0 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  197  	{ IMX415_LANEMODE, IMX415_LANEMODE_2 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  198  	{ IMX415_TCLKPOST, 0x006F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  199  	{ IMX415_TCLKPREPARE, 0x002F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  200  	{ IMX415_TCLKTRAIL, 0x002F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  201  	{ IMX415_TCLKZERO, 0x00BF },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  202  	{ IMX415_THSPREPARE, 0x002F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  203  	{ IMX415_THSZERO, 0x0057 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  204  	{ IMX415_THSTRAIL, 0x002F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  205  	{ IMX415_THSEXIT, 0x004F },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  206  	{ IMX415_TLPX, 0x0027 },
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  207  };
14cd15e7a1e2a3 Gerald Loacker  2023-01-30  208  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers
  2023-12-05  9:05 ` [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers Alexander Stein
  2023-12-05 19:24   ` kernel test robot
  2023-12-07 19:30   ` kernel test robot
@ 2023-12-07 21:02   ` Sakari Ailus
  2 siblings, 0 replies; 15+ messages in thread
From: Sakari Ailus @ 2023-12-07 21:02 UTC (permalink / raw)
  To: Alexander Stein
  Cc: Mauro Carvalho Chehab, Michael Riesch, Laurent Pinchart,
	Gerald Loacker, linux-media

Hi Alexander,

Thanks for the patch.

On Tue, Dec 05, 2023 at 10:05:55AM +0100, Alexander Stein wrote:
> Use the new common CCI register access helpers to replace the private
> register access helpers in the imx415 driver.
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
>  drivers/media/i2c/Kconfig  |   2 +
>  drivers/media/i2c/imx415.c | 396 +++++++++++++++----------------------
>  2 files changed, 162 insertions(+), 236 deletions(-)
> 
> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> index 59356eded339..71f8128f2df9 100644
> --- a/drivers/media/i2c/Kconfig
> +++ b/drivers/media/i2c/Kconfig
> @@ -194,6 +194,8 @@ config VIDEO_IMX412
>  config VIDEO_IMX415
>  	tristate "Sony IMX415 sensor support"
>  	depends on OF_GPIO
> +	select REGMAP_I2C

No need to select REGMAP_I2C---V4L2_CCI_I2C already does it.

> +	select V4L2_CCI_I2C
>  	help
>  	  This is a Video4Linux2 sensor driver for the Sony
>  	  IMX415 camera.

-- 
Regards,

Sakari Ailus

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 2/3] media: i2c: imx415: Add more clock configurations
  2023-12-05  9:05 ` [PATCH 2/3] media: i2c: imx415: Add more clock configurations Alexander Stein
@ 2023-12-12 11:37   ` Sakari Ailus
  2023-12-12 12:18     ` Alexander Stein
  0 siblings, 1 reply; 15+ messages in thread
From: Sakari Ailus @ 2023-12-12 11:37 UTC (permalink / raw)
  To: Alexander Stein
  Cc: Mauro Carvalho Chehab, Michael Riesch, Laurent Pinchart,
	Gerald Loacker, linux-media

Hi Alexander,

On Tue, Dec 05, 2023 at 10:05:56AM +0100, Alexander Stein wrote:
> Complete the list from "INCK Setting" section in IMX415-AAQR-C
> (Rev. E19504, 2019/05/21)
> 
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>

Could you address these smatch warnings, and run

	./scripts/checkpatch.pl --strict --max-line-length=80

on the patches?

drivers/media/i2c/imx415.c:402:30: warning: decimal constant 2376000000 is      
between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are 
very likely to produce unsigned long (and a                                     
warning) here                                                                   
drivers/media/i2c/imx415.c:417:30: warning: decimal constant 2376000000 is      
between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are 
very likely to produce unsigned long (and a                                     
warning) here                                                                   
drivers/media/i2c/imx415.c:432:30: warning: decimal constant 2376000000 is      
between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers are 
very likely to produce unsigned long (and a                                     
warning) here                                                                   

-- 
Sakari Ailus

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 2/3] media: i2c: imx415: Add more clock configurations
  2023-12-12 11:37   ` Sakari Ailus
@ 2023-12-12 12:18     ` Alexander Stein
  2023-12-12 12:45       ` Sakari Ailus
  0 siblings, 1 reply; 15+ messages in thread
From: Alexander Stein @ 2023-12-12 12:18 UTC (permalink / raw)
  To: Sakari Ailus
  Cc: Mauro Carvalho Chehab, Michael Riesch, Laurent Pinchart,
	Gerald Loacker, linux-media

Hi Sakari,

Am Dienstag, 12. Dezember 2023, 12:37:37 CET schrieb Sakari Ailus:
> Hi Alexander,
> 
> On Tue, Dec 05, 2023 at 10:05:56AM +0100, Alexander Stein wrote:
> > Complete the list from "INCK Setting" section in IMX415-AAQR-C
> > (Rev. E19504, 2019/05/21)
> > 
> > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> 
> Could you address these smatch warnings, and run
> 
> 	./scripts/checkpatch.pl --strict --max-line-length=80
> 
> on the patches?
> 
> drivers/media/i2c/imx415.c:402:30: warning: decimal constant 2376000000 is
> between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers
> are very likely to produce unsigned long (and a
> warning) here
> drivers/media/i2c/imx415.c:417:30: warning: decimal constant 2376000000 is
> between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers
> are very likely to produce unsigned long (and a
> warning) here
> drivers/media/i2c/imx415.c:432:30: warning: decimal constant 2376000000 is
> between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers
> are very likely to produce unsigned long (and a
> warning) here

Interesting, I don't have these warnings here. Is this some more recent 
checkpath.pl not in next?
I've addressed this and some 80 char length warnings as well. As I've sent out 
v2 this morning already, I'm waiting a bit more bevore v3.

Best regards,
Alexander
-- 
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
http://www.tq-group.com/



^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH 2/3] media: i2c: imx415: Add more clock configurations
  2023-12-12 12:18     ` Alexander Stein
@ 2023-12-12 12:45       ` Sakari Ailus
  0 siblings, 0 replies; 15+ messages in thread
From: Sakari Ailus @ 2023-12-12 12:45 UTC (permalink / raw)
  To: Alexander Stein
  Cc: Mauro Carvalho Chehab, Michael Riesch, Laurent Pinchart,
	Gerald Loacker, linux-media

Hi Alexander,

On Tue, Dec 12, 2023 at 01:18:18PM +0100, Alexander Stein wrote:
> Hi Sakari,
> 
> Am Dienstag, 12. Dezember 2023, 12:37:37 CET schrieb Sakari Ailus:
> > Hi Alexander,
> > 
> > On Tue, Dec 05, 2023 at 10:05:56AM +0100, Alexander Stein wrote:
> > > Complete the list from "INCK Setting" section in IMX415-AAQR-C
> > > (Rev. E19504, 2019/05/21)
> > > 
> > > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > 
> > Could you address these smatch warnings, and run
> > 
> > 	./scripts/checkpatch.pl --strict --max-line-length=80
> > 
> > on the patches?
> > 
> > drivers/media/i2c/imx415.c:402:30: warning: decimal constant 2376000000 is
> > between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers
> > are very likely to produce unsigned long (and a
> > warning) here
> > drivers/media/i2c/imx415.c:417:30: warning: decimal constant 2376000000 is
> > between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers
> > are very likely to produce unsigned long (and a
> > warning) here
> > drivers/media/i2c/imx415.c:432:30: warning: decimal constant 2376000000 is
> > between LONG_MAX and ULONG_MAX. For C99 that means long long, C90 compilers
> > are very likely to produce unsigned long (and a
> > warning) here
> 
> Interesting, I don't have these warnings here. Is this some more recent 
> checkpath.pl not in next?

Not checkpatch.pl but smatch <URL:https://github.com/error27/smatch>.

> I've addressed this and some 80 char length warnings as well. As I've
> sent out v2 this morning already, I'm waiting a bit more bevore v3.

Ack.

-- 
Sakari Ailus

^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2023-12-12 12:46 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-12-05  9:05 [PATCH 0/3] media: imx415: Add more modes Alexander Stein
2023-12-05  9:05 ` [PATCH 1/3] media: i2c: imx415: Convert to new CCI register access helpers Alexander Stein
2023-12-05 19:24   ` kernel test robot
2023-12-07 19:30   ` kernel test robot
2023-12-07 21:02   ` Sakari Ailus
2023-12-05  9:05 ` [PATCH 2/3] media: i2c: imx415: Add more clock configurations Alexander Stein
2023-12-12 11:37   ` Sakari Ailus
2023-12-12 12:18     ` Alexander Stein
2023-12-12 12:45       ` Sakari Ailus
2023-12-05  9:05 ` [PATCH 3/3] media: i2c: imx415: Add more supported modes Alexander Stein
2023-12-05 10:45   ` Laurent Pinchart
2023-12-05 11:12     ` Alexander Stein
2023-12-05 14:47       ` Gerald Loacker
2023-12-05 14:54         ` Laurent Pinchart
2023-12-06  7:38           ` Alexander Stein

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