Re: [PATCH v3 06/12] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8QM(QXP) compatible strings

Laurent Pinchart
2025-03-27T19:40:15Z

Hi Frank,

Thank you for the patch.

On Mon, Feb 10, 2025 at 03:59:25PM -0500, Frank Li wrote:
> From: Robert Chiras <robert.chiras@nxp.com>
>
> Add compatible strings for i.MX8QM/i.MX8QXP platform. Remove
> fsl,mipi-phy-gpr from required properties and add new reg space, since
> i.MX8QM and i.MX8QXP use dedicate control and status register(csr) space.
>
> Keep the same restriction for other compatible strings.
>
> Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change from v2 to v3
> - use dedicate csr register space
> change from v1 to v2
> - remove internal review tags
> - remove reg maxitems:1
> - remove 8ulp part
> - add 8qxp compatible string and make 8qm failback to 8qxp
> - limit reset and power domain number to 1 for 8qxp and 8qm
> - remove power-domains change because 8qm/8qxp only need 1 power domain
> ---
> .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 38 +++++++++++++++++++---
> 1 file changed, 34 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> index 2a14e3b0e0040..522449e50079e 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> @@ -16,11 +16,19 @@ description: |-
>
> properties:
> compatible:
> - enum:
> - - fsl,imx8mq-mipi-csi2
> + oneOf:
> + - enum:
> + - fsl,imx8mq-mipi-csi2
> + - fsl,imx8qxp-mipi-csi2
> + - items:
> + - const: fsl,imx8qm-mipi-csi2
> + - const: fsl,imx8qxp-mipi-csi2
>
> reg:
> - maxItems: 1
> + items:
> + - description: mipi csi2 rx host controller register.

s/mipi csi2 rx/MIPI CSI-2 RX/

> + - description: mipi csi2 control and status register (csr).

Same here, and s/csr/CSR/

> + minItems: 1
>
> clocks:
> items:
> @@ -46,6 +54,7 @@ properties:
> - description: CORE_RESET reset register bit definition
> - description: PHY_REF_RESET reset register bit definition
> - description: ESC_RESET reset register bit definition
> + minItems: 1

Is this because on QM and QXP the three resets are handled by the SCU,
which exposes them as a single reset ? The reset description is then not
very accurate anymore, but I suppose we can live with that.

With the above small changes,

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>
> fsl,mipi-phy-gpr:
> description: |
> @@ -113,9 +122,30 @@ required:
> - clock-names
> - power-domains
> - resets
> - - fsl,mipi-phy-gpr
> - ports
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8qxp-mipi-csi2
> + then:
> + properties:
> + reg:
> + minItems: 2
> + resets:
> + maxItems: 1
> + else:
> + properties:
> + reg:
> + maxItems: 1
> + resets:
> + minItems: 3
> + required:
> + - fsl,mipi-phy-gpr
> +
> additionalProperties: false
>
> examples:

--
Regards,

Laurent Pinchart