From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Cc: tomm.merciai@gmail.com, linux-renesas-soc@vger.kernel.org,
linux-media@vger.kernel.org, biju.das.jz@bp.renesas.com,
prabhakar.mahadev-lad.rj@bp.renesas.com,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Hans Verkuil" <hverkuil@xs4all.nl>,
"Uwe Kleine-König" <u.kleine-koenig@baylibre.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 12/18] media: rzg2l-cru: Pass resolution limits via OF data
Date: Sun, 23 Feb 2025 21:54:05 +0200 [thread overview]
Message-ID: <20250223195405.GG8330@pendragon.ideasonboard.com> (raw)
In-Reply-To: <20250221155532.576759-13-tommaso.merciai.xr@bp.renesas.com>
Hi Tommaso,
Thank you for the patch.
On Fri, Feb 21, 2025 at 04:55:26PM +0100, Tommaso Merciai wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Pass `max_width` and `max_height` as part of the OF data to facilitate the
> addition of support for RZ/G3E and RZ/V2H(P) SoCs. These SoCs have a
> maximum resolution of 4096x4096 as compared to 2800x4095 on RZ/G2L SoC.
> This change prepares the driver for easier integration of these SoCs by
> defining the resolution limits in the `rzg2l_cru_info` structure.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
> .../media/platform/renesas/rzg2l-cru/rzg2l-core.c | 2 ++
> .../media/platform/renesas/rzg2l-cru/rzg2l-cru.h | 4 ++--
> drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c | 13 +++++++++----
> .../media/platform/renesas/rzg2l-cru/rzg2l-video.c | 5 +++--
> 4 files changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c
> index abc2a979833a..19f93b7fe6fb 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-core.c
> @@ -355,6 +355,8 @@ static const u16 rzg2l_cru_regs[] = {
> };
>
> static const struct rzg2l_cru_info rzgl2_cru_info = {
> + .max_width = 2800,
> + .max_height = 4095,
> .regs = rzg2l_cru_regs,
> };
>
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h
> index 00c3f7458e20..6a621073948a 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-cru.h
> @@ -27,9 +27,7 @@
> #define RZG2L_CRU_CSI2_VCHANNEL 4
>
> #define RZG2L_CRU_MIN_INPUT_WIDTH 320
> -#define RZG2L_CRU_MAX_INPUT_WIDTH 2800
> #define RZG2L_CRU_MIN_INPUT_HEIGHT 240
> -#define RZG2L_CRU_MAX_INPUT_HEIGHT 4095
>
> enum rzg2l_csi2_pads {
> RZG2L_CRU_IP_SINK = 0,
> @@ -81,6 +79,8 @@ struct rzg2l_cru_ip_format {
> };
>
> struct rzg2l_cru_info {
> + unsigned int max_width;
> + unsigned int max_height;
> const u16 *regs;
> };
>
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> index 76a2b451f1da..7836c7cd53dc 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-ip.c
> @@ -148,6 +148,8 @@ static int rzg2l_cru_ip_set_format(struct v4l2_subdev *sd,
> struct v4l2_subdev_state *state,
> struct v4l2_subdev_format *fmt)
> {
> + struct rzg2l_cru_dev *cru = v4l2_get_subdevdata(sd);
> + const struct rzg2l_cru_info *info = cru->info;
> struct v4l2_mbus_framefmt *src_format;
> struct v4l2_mbus_framefmt *sink_format;
>
> @@ -170,9 +172,9 @@ static int rzg2l_cru_ip_set_format(struct v4l2_subdev *sd,
> sink_format->ycbcr_enc = fmt->format.ycbcr_enc;
> sink_format->quantization = fmt->format.quantization;
> sink_format->width = clamp_t(u32, fmt->format.width,
> - RZG2L_CRU_MIN_INPUT_WIDTH, RZG2L_CRU_MAX_INPUT_WIDTH);
> + RZG2L_CRU_MIN_INPUT_WIDTH, info->max_width);
> sink_format->height = clamp_t(u32, fmt->format.height,
> - RZG2L_CRU_MIN_INPUT_HEIGHT, RZG2L_CRU_MAX_INPUT_HEIGHT);
> + RZG2L_CRU_MIN_INPUT_HEIGHT, info->max_height);
>
> fmt->format = *sink_format;
>
> @@ -197,6 +199,9 @@ static int rzg2l_cru_ip_enum_frame_size(struct v4l2_subdev *sd,
> struct v4l2_subdev_state *state,
> struct v4l2_subdev_frame_size_enum *fse)
> {
> + struct rzg2l_cru_dev *cru = v4l2_get_subdevdata(sd);
> + const struct rzg2l_cru_info *info = cru->info;
> +
> if (fse->index != 0)
> return -EINVAL;
>
> @@ -205,8 +210,8 @@ static int rzg2l_cru_ip_enum_frame_size(struct v4l2_subdev *sd,
>
> fse->min_width = RZG2L_CRU_MIN_INPUT_WIDTH;
> fse->min_height = RZG2L_CRU_MIN_INPUT_HEIGHT;
> - fse->max_width = RZG2L_CRU_MAX_INPUT_WIDTH;
> - fse->max_height = RZG2L_CRU_MAX_INPUT_HEIGHT;
> + fse->max_width = info->max_width;
> + fse->max_height = info->max_height;
>
> return 0;
> }
> diff --git a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c
> index f25fd9b35c55..9e5e79c6ca98 100644
> --- a/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c
> +++ b/drivers/media/platform/renesas/rzg2l-cru/rzg2l-video.c
> @@ -690,6 +690,7 @@ int rzg2l_cru_dma_register(struct rzg2l_cru_dev *cru)
> static void rzg2l_cru_format_align(struct rzg2l_cru_dev *cru,
> struct v4l2_pix_format *pix)
> {
> + const struct rzg2l_cru_info *info = cru->info;
> const struct rzg2l_cru_ip_format *fmt;
>
> fmt = rzg2l_cru_ip_format_to_fmt(pix->pixelformat);
> @@ -712,8 +713,8 @@ static void rzg2l_cru_format_align(struct rzg2l_cru_dev *cru,
> }
>
> /* Limit to CRU capabilities */
> - v4l_bound_align_image(&pix->width, 320, RZG2L_CRU_MAX_INPUT_WIDTH, 1,
> - &pix->height, 240, RZG2L_CRU_MAX_INPUT_HEIGHT, 2, 0);
> + v4l_bound_align_image(&pix->width, 320, info->max_width, 1,
> + &pix->height, 240, info->max_height, 2, 0);
>
> pix->bytesperline = pix->width * fmt->bpp;
> pix->sizeimage = pix->bytesperline * pix->height;
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2025-02-23 19:54 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-21 15:55 [PATCH v2 00/18] media: rzg2l-cru: Add support for RZ/G3E (CSI2, CRU) Tommaso Merciai
2025-02-21 15:55 ` [PATCH v2 01/18] media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/V2H(P) SoC Tommaso Merciai
2025-02-23 18:08 ` Laurent Pinchart
2025-02-23 21:00 ` Lad, Prabhakar
2025-02-24 8:07 ` Tommaso Merciai
2025-02-24 9:00 ` Geert Uytterhoeven
2025-02-24 9:05 ` Geert Uytterhoeven
2025-02-24 9:09 ` Biju Das
2025-02-24 9:21 ` Geert Uytterhoeven
2025-02-24 17:25 ` Rob Herring (Arm)
2025-02-21 15:55 ` [PATCH v2 02/18] media: dt-bindings: renesas,rzg2l-csi2: Document Renesas RZ/G3E CSI-2 block Tommaso Merciai
2025-02-23 18:10 ` Laurent Pinchart
2025-02-23 21:11 ` Lad, Prabhakar
2025-02-24 8:11 ` Tommaso Merciai
2025-02-21 15:55 ` [PATCH v2 03/18] media: dt-bindings: renesas,rzg2l-cru: Document Renesas RZ/G3E SoC Tommaso Merciai
2025-02-24 17:27 ` Rob Herring (Arm)
2025-02-21 15:55 ` [PATCH v2 04/18] media: rzg2l-cru: csi2: Use local variable for struct device in rzg2l_csi2_probe() Tommaso Merciai
2025-02-23 18:13 ` Laurent Pinchart
2025-02-21 15:55 ` [PATCH v2 05/18] media: rzg2l-cru: csi2: Use devm_pm_runtime_enable() Tommaso Merciai
2025-02-23 21:13 ` Lad, Prabhakar
2025-02-21 15:55 ` [PATCH v2 06/18] media: rzg2l-cru: rzg2l-core: Use local variable for struct device in rzg2l_cru_probe() Tommaso Merciai
2025-02-21 15:55 ` [PATCH v2 07/18] media: rzg2l-cru: rzg2l-core: Use devm_pm_runtime_enable() Tommaso Merciai
2025-02-23 18:14 ` Laurent Pinchart
2025-02-23 21:14 ` Lad, Prabhakar
2025-02-21 15:55 ` [PATCH v2 08/18] media: rzg2l-cru: csi2: Introduce SoC-specific D-PHY handling Tommaso Merciai
2025-02-23 18:17 ` Laurent Pinchart
2025-02-23 21:21 ` Lad, Prabhakar
2025-02-21 15:55 ` [PATCH v2 09/18] media: rzg2l-cru: csi2: Make system clock optional for RZ/V2H(P) SoC Tommaso Merciai
2025-02-23 18:19 ` Laurent Pinchart
2025-02-23 20:57 ` Lad, Prabhakar
2025-02-21 15:55 ` [PATCH v2 10/18] media: rzg2l-cru: csi2: Add support " Tommaso Merciai
2025-02-23 18:24 ` Laurent Pinchart
2025-02-21 15:55 ` [PATCH v2 11/18] media: rzg2l-cru: Add register mapping support Tommaso Merciai
2025-02-23 19:52 ` Laurent Pinchart
2025-02-24 13:46 ` Tommaso Merciai
2025-02-24 18:44 ` Laurent Pinchart
2025-02-25 11:21 ` Tommaso Merciai
2025-02-21 15:55 ` [PATCH v2 12/18] media: rzg2l-cru: Pass resolution limits via OF data Tommaso Merciai
2025-02-23 19:54 ` Laurent Pinchart [this message]
2025-02-21 15:55 ` [PATCH v2 13/18] media: rzg2l-cru: Add image_conv offset to " Tommaso Merciai
2025-02-21 15:55 ` [PATCH v2 14/18] media: rzg2l-cru: Add IRQ handler " Tommaso Merciai
2025-02-23 19:55 ` Laurent Pinchart
2025-02-21 15:55 ` [PATCH v2 15/18] media: rzg2l-cru: Add function pointers to enable and disable interrupts Tommaso Merciai
2025-02-23 19:56 ` Laurent Pinchart
2025-02-21 15:55 ` [PATCH v2 16/18] media: rzg2l-cru: Add function pointer to check if FIFO is empty Tommaso Merciai
2025-02-23 20:00 ` Laurent Pinchart
2025-02-21 15:55 ` [PATCH v2 17/18] media: rzg2l-cru: Add function pointer to configure CSI Tommaso Merciai
2025-02-23 20:03 ` Laurent Pinchart
2025-02-21 15:55 ` [PATCH v2 18/18] media: rzg2l-cru: Add support for RZ/G3E SoC Tommaso Merciai
2025-02-23 20:32 ` Laurent Pinchart
2025-02-24 18:15 ` Tommaso Merciai
2025-02-24 18:38 ` Laurent Pinchart
2025-02-25 11:28 ` Tommaso Merciai
2025-02-25 10:52 ` Tommaso Merciai
2025-02-25 11:23 ` Laurent Pinchart
2025-02-25 11:30 ` Tommaso Merciai
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