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From: Rob Herring <robh@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: "Thierry Reding" <thierry.reding@gmail.com>,
	"Thierry Reding" <treding@nvidia.com>,
	"Mikko Perttunen" <mperttunen@nvidia.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Sowjanya Komatineni" <skomatineni@nvidia.com>,
	"Luca Ceresoli" <luca.ceresoli@bootlin.com>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Prashant Gaikwad" <pgaikwad@nvidia.com>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Dmitry Osipenko" <digetx@gmail.com>,
	"Jonas Schwöbel" <jonasschwoebel@yahoo.de>,
	"Charan Pedumuru" <charan.pedumuru@gmail.com>,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-media@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-staging@lists.linux.dev
Subject: Re: [PATCH v2 21/23] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI
Date: Tue, 9 Sep 2025 21:13:32 -0500	[thread overview]
Message-ID: <20250910021332.GA3634809-robh@kernel.org> (raw)
In-Reply-To: <CAPVz0n2Hafvnk4BBXfhWLWCfTg336DLOr=xN9vKBGc2xEWYrMw@mail.gmail.com>

On Tue, Sep 09, 2025 at 07:39:02PM +0300, Svyatoslav Ryhel wrote:
> вт, 9 вер. 2025 р. о 19:26 Rob Herring <robh@kernel.org> пише:
> >
> > On Sat, Sep 06, 2025 at 04:53:42PM +0300, Svyatoslav Ryhel wrote:
> > > Document CSI HW block found in Tegra20 and Tegra30 SoC.
> > >
> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > > ---
> > >  .../display/tegra/nvidia,tegra20-csi.yaml     | 104 ++++++++++++++++
> > >  .../display/tegra/nvidia,tegra30-csi.yaml     | 115 ++++++++++++++++++
> > >  2 files changed, 219 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> > >  create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra30-csi.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> > > new file mode 100644
> > > index 000000000000..1a2858a5893c
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-csi.yaml
> > > @@ -0,0 +1,104 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-csi.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: NVIDIA Tegra20 CSI controller
> > > +
> > > +maintainers:
> > > +  - Svyatoslav Ryhel <clamor95@gmail.com>
> > > +
> > > +properties:
> > > +  compatible:
> > > +    enum:
> > > +      - nvidia,tegra20-csi
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  clocks:
> > > +    maxItems: 1
> > > +
> > > +  avdd-dsi-csi-supply:
> > > +    description: DSI/CSI power supply. Must supply 1.2 V.
> > > +
> > > +  power-domains:
> > > +    maxItems: 1
> > > +
> > > +  "#nvidia,mipi-calibrate-cells":
> > > +    description: The number of cells in a MIPI calibration specifier.
> > > +      Should be 1. The single cell specifies an id of the pads that
> > > +      need to be calibrated for a given device.
> > > +    $ref: /schemas/types.yaml#/definitions/uint32
> > > +    const: 1
> >
> > This property goes in the provider. Is the parent node the provider? You
> > don't really need any of it if it's all one block.
> >
> 
> Yes parent node is provides and channel is one of receivers, other one
> is DSI node.

Please make that clear in the descriptions somewhere.

> 
> > > +
> > > +  "#address-cells":
> > > +    const: 1
> > > +
> > > +  "#size-cells":
> > > +    const: 0
> > > +
> > > +patternProperties:
> > > +  "^channel@[0-1]$":
> > > +    type: object
> > > +    description: channel 0 represents CSI-A and 1 represents CSI-B
> > > +    additionalProperties: false
> > > +
> > > +    properties:
> > > +      reg:
> > > +        maxItems: 1
> >
> > Instead:
> >
> > maximum: 1
> >
> >
> > > +
> > > +      nvidia,mipi-calibrate:
> > > +        description: Should contain a phandle and a specifier specifying
> > > +          which pads are used by this DSI output and need to be
> > > +          calibrated. 0 is for CSI-A, 1 is for CSI-B, 2 is for DSI.
> > > +        $ref: /schemas/types.yaml#/definitions/phandle-array
> >
> > Is DSI applicable here?
> >
> 
> It is because CSI is calibration provider. I can move it up into
> #nvidia,mipi-calibrate-cells which may be more appropriate place.

Yes, as the provider defines the meaning of the cells (and they are 
opaque to the consumer).

Rob

  reply	other threads:[~2025-09-10  2:13 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-06 13:53 [PATCH v2 00/23] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 01/23] clk: tegra: set CSUS as vi_sensors gate for Tegra20, Tegra30 and Tegra114 Svyatoslav Ryhel
2025-09-19  6:29   ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 02/23] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks Svyatoslav Ryhel
2025-09-07  9:34   ` Krzysztof Kozlowski
2025-09-07  9:43     ` Svyatoslav Ryhel
2025-09-07 18:25       ` Krzysztof Kozlowski
2025-09-06 13:53 ` [PATCH v2 03/23] clk: tegra30: add CSI pad clock gates Svyatoslav Ryhel
2025-09-19  6:33   ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 04/23] dt-bindings: display: tegra: document Tegra30 VI and VIP Svyatoslav Ryhel
2025-09-06 19:17   ` Rob Herring (Arm)
2025-09-06 13:53 ` [PATCH v2 05/23] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-09-17  7:52   ` Luca Ceresoli
2025-09-06 13:53 ` [PATCH v2 06/23] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 07/23] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 08/23] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 09/23] gpu: host1x: convert MIPI to use operations Svyatoslav Ryhel
2025-09-19  6:47   ` Mikko Perttunen
2025-09-19  7:58     ` Svyatoslav Ryhel
2025-09-19  8:56       ` Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 10/23] staging: media: tegra-video: csi: add support for SoCs with integrated MIPI calibration Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 11/23] staging: media: tegra-video: csi: add a check to tegra_channel_get_remote_csi_subdev Svyatoslav Ryhel
2025-09-16 16:04   ` Luca Ceresoli
2025-09-16 16:24     ` Svyatoslav Ryhel
2025-09-17  7:25       ` Luca Ceresoli
2025-09-17  7:49         ` Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 12/23] dt-bindings: display: tegra: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2025-09-09  0:49   ` Rob Herring (Arm)
2025-09-09  0:57   ` Rob Herring
2025-09-09  5:00     ` Svyatoslav Ryhel
2025-09-09 16:03       ` Rob Herring
2025-09-06 13:53 ` [PATCH v2 13/23] staging: media: tegra-video: csi: " Svyatoslav Ryhel
2025-09-17  7:52   ` Luca Ceresoli
2025-09-22  4:11   ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 14/23] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 15/23] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-22  4:29   ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 16/23] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-09-22  4:44   ` Mikko Perttunen
2025-09-22  5:13     ` Svyatoslav Ryhel
2025-09-22  6:23       ` Mikko Perttunen
2025-09-22  6:30         ` Svyatoslav Ryhel
2025-09-22  7:27           ` Mikko Perttunen
2025-09-22  7:36             ` Svyatoslav Ryhel
2025-09-23  6:03               ` Mikko Perttunen
2025-09-23  6:11                 ` Svyatoslav Ryhel
2025-09-23  6:50                   ` Svyatoslav Ryhel
2025-09-24  4:47                     ` Mikko Perttunen
2025-09-24 10:24                       ` Svyatoslav Ryhel
2025-09-24 23:20                         ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 17/23] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 18/23] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-09-22  4:54   ` Mikko Perttunen
2025-09-22  4:58     ` Svyatoslav Ryhel
2025-09-22  6:23       ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 19/23] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Svyatoslav Ryhel
2025-09-22  5:00   ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 20/23] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 21/23] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-09-09 16:26   ` Rob Herring
2025-09-09 16:39     ` Svyatoslav Ryhel
2025-09-10  2:13       ` Rob Herring [this message]
2025-09-06 13:53 ` [PATCH v2 22/23] ARM: tegra: add CSI nodes for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 23/23] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
2025-09-15  5:46   ` kernel test robot
2025-09-22  5:15   ` Mikko Perttunen
2025-09-22  5:19     ` Svyatoslav Ryhel
2025-09-22  5:38       ` Mikko Perttunen
2025-09-22  6:16     ` Svyatoslav Ryhel
2025-09-22  6:36       ` Mikko Perttunen
2025-09-11 16:03 ` (subset) [PATCH v2 00/23] " Thierry Reding

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