* [PATCH v4 0/3] Add CAMSS support for SM6350
@ 2026-02-16 8:54 Luca Weiss
2026-02-16 8:54 ` [PATCH v4 1/3] dt-bindings: media: camss: Add qcom,sm6350-camss Luca Weiss
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Luca Weiss @ 2026-02-16 8:54 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Luca Weiss,
Krzysztof Kozlowski
Add bindings, driver and dts to support the Camera Subsystem on the
SM6350 SoC.
These patches were tested on a Fairphone 4 smartphone with WIP sensor
drivers (Sony IMX576 and IMX582), the camera pipeline works properly as
far as I can tell.
Though when stopping the camera stream, the following clock warning
appears in dmesg. But it does not interfere with any functionality,
starting and stopping the stream works and debugcc is showing 426.4 MHz
while the clock is on, and 'off' while it's off.
Any suggestion how to fix this, is appreciated.
[ 5738.590980] ------------[ cut here ]------------
[ 5738.591009] gcc_camera_axi_clk status stuck at 'on'
[ 5738.591049] WARNING: CPU: 0 PID: 6918 at drivers/clk/qcom/clk-branch.c:87 clk_branch_toggle+0x170/0x190
[ 5738.591081] Modules linked in:
[ 5738.591099] CPU: 0 UID: 10000 PID: 6918 Comm: plasma-camera Tainted: G W 6.17.0-00057-ge6b67db49622 #71 NONE
[ 5738.591118] Tainted: [W]=WARN
[ 5738.591126] Hardware name: Fairphone 4 (DT)
[ 5738.591136] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 5738.591150] pc : clk_branch_toggle+0x170/0x190
[ 5738.591164] lr : clk_branch_toggle+0x170/0x190
[ 5738.591177] sp : ffff800086ed3980
[ 5738.591184] x29: ffff800086ed3990 x28: 0000000000000001 x27: ffff800086ed3cd8
[ 5738.591208] x26: 0000000000000000 x25: ffffda14fcfbd250 x24: 0000000000000000
[ 5738.591230] x23: 0000000000000000 x22: ffffda14fc38bce0 x21: 0000000000000000
[ 5738.591252] x20: ffffda14fd33e618 x19: 0000000000000000 x18: 00000000000064c8
[ 5738.591274] x17: 0000000000000000 x16: 00001ae003667e9e x15: ffffda14fd2a07b0
[ 5738.591295] x14: 0000000000000000 x13: 6f27207461206b63 x12: 7574732073757461
[ 5738.591317] x11: 0000000000000058 x10: 0000000000000018 x9 : ffffda14fd2a0838
[ 5738.591338] x8 : 0000000000057fa8 x7 : 0000000000000a16 x6 : ffffda14fd2f8838
[ 5738.591360] x5 : ffff0001f6f59788 x4 : 0000000000000a15 x3 : ffff25ecf9d7e000
[ 5738.591381] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000baf5c100
[ 5738.591403] Call trace:
[ 5738.591412] clk_branch_toggle+0x170/0x190 (P)
[ 5738.591429] clk_branch2_disable+0x1c/0x30
[ 5738.591445] clk_core_disable+0x5c/0xb4
[ 5738.591462] clk_disable+0x38/0x60
[ 5738.591478] camss_disable_clocks+0x44/0x78
[ 5738.591496] vfe_put+0x7c/0xc0
[ 5738.591512] vfe_set_power+0x40/0x50
[ 5738.591528] pipeline_pm_power_one+0x14c/0x150
[ 5738.591546] pipeline_pm_power+0x74/0xf4
[ 5738.591561] v4l2_pipeline_pm_use+0x54/0x9c
[ 5738.591577] v4l2_pipeline_pm_put+0x14/0x40
[ 5738.591592] video_unprepare_streaming+0x18/0x24
[ 5738.591608] __vb2_queue_cancel+0x4c/0x314
[ 5738.591626] vb2_core_streamoff+0x24/0xc8
[ 5738.591643] vb2_ioctl_streamoff+0x58/0x98
[ 5738.591657] v4l_streamoff+0x24/0x30
[ 5738.591672] __video_do_ioctl+0x430/0x4a8
[ 5738.591689] video_usercopy+0x2ac/0x680
[ 5738.591705] video_ioctl2+0x18/0x40
[ 5738.591720] v4l2_ioctl+0x40/0x60
[ 5738.591734] __arm64_sys_ioctl+0x90/0xf0
[ 5738.591750] invoke_syscall.constprop.0+0x40/0xf0
[ 5738.591769] el0_svc_common.constprop.0+0x38/0xd8
[ 5738.591785] do_el0_svc+0x1c/0x28
[ 5738.591801] el0_svc+0x34/0xe8
[ 5738.591820] el0t_64_sync_handler+0xa0/0xe4
[ 5738.591838] el0t_64_sync+0x198/0x19c
[ 5738.591854] ---[ end trace 0000000000000000 ]---
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Changes in v4:
- Update power-domain-names order (Krzysztof)
- Make hex numbers lower case in init seq (David)
- Pick up tags
- Link to v3: https://lore.kernel.org/r/20260213-sm6350-camss-v3-0-30a845b0b7cc@fairphone.com
Changes in v3:
- Update dt-bindings to include everything related to camss
- Update regulator names
- Remove slow_ahb_src
- Link to v2: https://lore.kernel.org/r/20251114-sm6350-camss-v2-0-d1ff67da33b6@fairphone.com
Changes in v2:
- Remove prefix from interconnect-names
- Move 'top' power-domain to the top of list
- Update regulator supply names
- Link to v1: https://lore.kernel.org/r/20251024-sm6350-camss-v1-0-63d626638add@fairphone.com
---
Luca Weiss (3):
dt-bindings: media: camss: Add qcom,sm6350-camss
media: qcom: camss: Add SM6350 support
arm64: dts: qcom: sm6350: Add CAMSS node
.../bindings/media/qcom,sm6350-camss.yaml | 471 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm6350.dtsi | 233 ++++++++++
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 125 ++++++
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 261 ++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
6 files changed, 1093 insertions(+)
---
base-commit: 3daf23347bb5f4a375d0101ed29c97ce1a99721b
change-id: 20251024-sm6350-camss-9c404bf9cfdd
Best regards,
--
Luca Weiss <luca.weiss@fairphone.com>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v4 1/3] dt-bindings: media: camss: Add qcom,sm6350-camss
2026-02-16 8:54 [PATCH v4 0/3] Add CAMSS support for SM6350 Luca Weiss
@ 2026-02-16 8:54 ` Luca Weiss
2026-02-16 8:54 ` [PATCH v4 2/3] media: qcom: camss: Add SM6350 support Luca Weiss
2026-02-16 8:54 ` [PATCH v4 3/3] arm64: dts: qcom: sm6350: Add CAMSS node Luca Weiss
2 siblings, 0 replies; 4+ messages in thread
From: Luca Weiss @ 2026-02-16 8:54 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Luca Weiss,
Krzysztof Kozlowski
Add bindings for the Camera Subsystem on the SM6350 SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
.../bindings/media/qcom,sm6350-camss.yaml | 471 +++++++++++++++++++++
1 file changed, 471 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml
new file mode 100644
index 000000000000..96974d90d8c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml
@@ -0,0 +1,471 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,sm6350-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6350 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Luca Weiss <luca.weiss@fairphone.com>
+
+description:
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,sm6350-camss
+
+ reg:
+ maxItems: 24
+
+ reg-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite
+ - const: a5_csr
+ - const: a5_qgic
+ - const: a5_sierra
+ - const: bps
+ - const: camnoc
+ - const: core_top_csr_tcsr
+ - const: cpas_cdm
+ - const: cpas_top
+ - const: ipe
+ - const: jpeg_dma
+ - const: jpeg_enc
+ - const: lrme
+
+ clocks:
+ maxItems: 39
+
+ clock-names:
+ items:
+ - const: cam_axi
+ - const: soc_ahb
+ - const: camnoc_axi
+ - const: core_ahb
+ - const: cpas_ahb
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy3
+ - const: csiphy3_timer
+ - const: vfe0_axi
+ - const: vfe0
+ - const: vfe0_cphy_rx
+ - const: vfe0_csid
+ - const: vfe1_axi
+ - const: vfe1
+ - const: vfe1_cphy_rx
+ - const: vfe1_csid
+ - const: vfe2_axi
+ - const: vfe2
+ - const: vfe2_cphy_rx
+ - const: vfe2_csid
+ - const: vfe_lite
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+ - const: bps
+ - const: bps_ahb
+ - const: bps_areg
+ - const: bps_axi
+ - const: icp
+ - const: ipe0
+ - const: ipe0_ahb
+ - const: ipe0_areg
+ - const: ipe0_axi
+ - const: jpeg
+ - const: lrme
+
+ interrupts:
+ maxItems: 18
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy3
+ - const: vfe0
+ - const: vfe1
+ - const: vfe2
+ - const: vfe_lite
+ - const: a5
+ - const: cpas
+ - const: cpas_cdm
+ - const: jpeg_dma
+ - const: jpeg_enc
+ - const: lrme
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: ahb
+ - const: hf_mnoc
+ - const: sf_mnoc
+ - const: sf_icp_mnoc
+
+ iommus:
+ maxItems: 14
+
+ power-domains:
+ maxItems: 6
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: ife2
+ - const: top
+ - const: bps
+ - const: ipe
+
+ vdd-csiphy0-0p9-supply:
+ description:
+ Phandle to a 0.9V regulator supply to CSIPHY0.
+
+ vdd-csiphy0-1p25-supply:
+ description:
+ Phandle to a 1.25V regulator supply to CSIPHY0.
+
+ vdd-csiphy1-0p9-supply:
+ description:
+ Phandle to a 0.9V regulator supply to CSIPHY1.
+
+ vdd-csiphy1-1p25-supply:
+ description:
+ Phandle to a 1.25V regulator supply to CSIPHY1.
+
+ vdd-csiphy2-0p9-supply:
+ description:
+ Phandle to a 0.9V regulator supply to CSIPHY2.
+
+ vdd-csiphy2-1p25-supply:
+ description:
+ Phandle to a 1.25V regulator supply to CSIPHY2.
+
+ vdd-csiphy3-0p9-supply:
+ description:
+ Phandle to a 0.9V regulator supply to CSIPHY3.
+
+ vdd-csiphy3-1p25-supply:
+ description:
+ Phandle to a 1.25V regulator supply to CSIPHY3.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-3]$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ description:
+ Input port for receiving CSI data from a CSIPHY.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ bus-type:
+ enum:
+ - 1 # MEDIA_BUS_TYPE_CSI2_CPHY
+ - 4 # MEDIA_BUS_TYPE_CSI2_DPHY
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm6350.h>
+ #include <dt-bindings/clock/qcom,sm6350-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,sm6350.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/media/video-interfaces.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ isp@acb3000 {
+ compatible = "qcom,sm6350-camss";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc1000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0ac65000 0x0 0x1000>,
+ <0x0 0x0ac66000 0x0 0x1000>,
+ <0x0 0x0ac67000 0x0 0x1000>,
+ <0x0 0x0ac68000 0x0 0x1000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acbd000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0ac18000 0x0 0x3000>,
+ <0x0 0x0ac00000 0x0 0x6000>,
+ <0x0 0x0ac10000 0x0 0x8000>,
+ <0x0 0x0ac6f000 0x0 0x8000>,
+ <0x0 0x0ac42000 0x0 0x4600>,
+ <0x0 0x01fc0000 0x0 0x40000>,
+ <0x0 0x0ac48000 0x0 0x1000>,
+ <0x0 0x0ac40000 0x0 0x1000>,
+ <0x0 0x0ac87000 0x0 0xa000>,
+ <0x0 0x0ac52000 0x0 0x4000>,
+ <0x0 0x0ac4e000 0x0 0x4000>,
+ <0x0 0x0ac6b000 0x0 0xa00>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite",
+ "a5_csr",
+ "a5_qgic",
+ "a5_sierra",
+ "bps",
+ "camnoc",
+ "core_top_csr_tcsr",
+ "cpas_cdm",
+ "cpas_top",
+ "ipe",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ clocks = <&gcc GCC_CAMERA_AXI_CLK>,
+ <&camcc CAMCC_SOC_AHB_CLK>,
+ <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_CORE_AHB_CLK>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CSIPHY0_CLK>,
+ <&camcc CAMCC_CSI0PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY1_CLK>,
+ <&camcc CAMCC_CSI1PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY2_CLK>,
+ <&camcc CAMCC_CSI2PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY3_CLK>,
+ <&camcc CAMCC_CSI3PHYTIMER_CLK>,
+ <&camcc CAMCC_IFE_0_AXI_CLK>,
+ <&camcc CAMCC_IFE_0_CLK>,
+ <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_0_CSID_CLK>,
+ <&camcc CAMCC_IFE_1_AXI_CLK>,
+ <&camcc CAMCC_IFE_1_CLK>,
+ <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_1_CSID_CLK>,
+ <&camcc CAMCC_IFE_2_AXI_CLK>,
+ <&camcc CAMCC_IFE_2_CLK>,
+ <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_2_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_CLK>,
+ <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_CSID_CLK>,
+ <&camcc CAMCC_BPS_CLK>,
+ <&camcc CAMCC_BPS_AHB_CLK>,
+ <&camcc CAMCC_BPS_AREG_CLK>,
+ <&camcc CAMCC_BPS_AXI_CLK>,
+ <&camcc CAMCC_ICP_CLK>,
+ <&camcc CAMCC_IPE_0_CLK>,
+ <&camcc CAMCC_IPE_0_AHB_CLK>,
+ <&camcc CAMCC_IPE_0_AREG_CLK>,
+ <&camcc CAMCC_IPE_0_AXI_CLK>,
+ <&camcc CAMCC_JPEG_CLK>,
+ <&camcc CAMCC_LRME_CLK>;
+ clock-names = "cam_axi",
+ "soc_ahb",
+ "camnoc_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe2_axi",
+ "vfe2",
+ "vfe2_cphy_rx",
+ "vfe2_csid",
+ "vfe_lite",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "bps",
+ "bps_ahb",
+ "bps_areg",
+ "bps_axi",
+ "icp",
+ "ipe0",
+ "ipe0_ahb",
+ "ipe0_areg",
+ "ipe0_axi",
+ "jpeg",
+ "lrme";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 473 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 472 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite",
+ "a5",
+ "cpas",
+ "cpas_cdm",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc",
+ "sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x820 0xc0>,
+ <&apps_smmu 0x840 0x0>,
+ <&apps_smmu 0x860 0xc0>,
+ <&apps_smmu 0x880 0x0>,
+ <&apps_smmu 0xc40 0x20>,
+ <&apps_smmu 0xc60 0x20>,
+ <&apps_smmu 0xc80 0x0>,
+ <&apps_smmu 0xca2 0x0>,
+ <&apps_smmu 0xcc0 0x20>,
+ <&apps_smmu 0xce0 0x20>,
+ <&apps_smmu 0xd00 0x20>,
+ <&apps_smmu 0xd20 0x20>,
+ <&apps_smmu 0xd40 0x20>,
+ <&apps_smmu 0xd60 0x20>;
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc IFE_2_GDSC>,
+ <&camcc TITAN_TOP_GDSC>,
+ <&camcc BPS_GDSC>,
+ <&camcc IPE_0_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top",
+ "bps",
+ "ipe";
+
+ vdd-csiphy0-0p9-supply = <&vreg_l18a>;
+ vdd-csiphy0-1p25-supply = <&vreg_l22a>;
+ vdd-csiphy1-0p9-supply = <&vreg_l18a>;
+ vdd-csiphy1-1p25-supply = <&vreg_l22a>;
+ vdd-csiphy2-0p9-supply = <&vreg_l18a>;
+ vdd-csiphy2-1p25-supply = <&vreg_l22a>;
+ vdd-csiphy3-0p9-supply = <&vreg_l18a>;
+ vdd-csiphy3-1p25-supply = <&vreg_l22a>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy0_ep: endpoint {
+ data-lanes = <0 1 2 3>;
+ bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.53.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v4 2/3] media: qcom: camss: Add SM6350 support
2026-02-16 8:54 [PATCH v4 0/3] Add CAMSS support for SM6350 Luca Weiss
2026-02-16 8:54 ` [PATCH v4 1/3] dt-bindings: media: camss: Add qcom,sm6350-camss Luca Weiss
@ 2026-02-16 8:54 ` Luca Weiss
2026-02-16 8:54 ` [PATCH v4 3/3] arm64: dts: qcom: sm6350: Add CAMSS node Luca Weiss
2 siblings, 0 replies; 4+ messages in thread
From: Luca Weiss @ 2026-02-16 8:54 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Luca Weiss
Add the necessary support for CAMSS on the SM6350 SoC.
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 125 ++++++++++
drivers/media/platform/qcom/camss/camss-vfe.c | 2 +
drivers/media/platform/qcom/camss/camss.c | 261 +++++++++++++++++++++
drivers/media/platform/qcom/camss/camss.h | 1 +
4 files changed, 389 insertions(+)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 415483274552..dac8d2ecf799 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -399,6 +399,126 @@ csiphy_lane_regs lane_regs_sm8250[] = {
{0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
};
+/* GEN2 1.2.3 2PH */
+static const struct
+csiphy_lane_regs lane_regs_sm6350[] = {
+ {0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0904, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0910, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0900, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0908, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0904, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x002c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0034, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0010, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x001c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0028, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x003c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0004, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0038, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x005c, 0xc0, 0x00, CSIPHY_SKEW_CAL},
+ {0x0060, 0x0d, 0x00, CSIPHY_SKEW_CAL},
+ {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0730, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c84, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c80, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c88, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c84, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x072c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0734, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0710, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x071c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0714, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0728, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x073c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0700, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0704, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0720, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0708, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x070c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0710, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0738, 0x1f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0230, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a00, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x022c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0234, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0210, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x021c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0214, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x023c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0200, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0204, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0220, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0208, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0210, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0238, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x025c, 0xc0, 0x00, CSIPHY_SKEW_CAL},
+ {0x0260, 0x0d, 0x00, CSIPHY_SKEW_CAL},
+ {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b00, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x042c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0434, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0410, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x041c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0428, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x043c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0400, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0404, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0408, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0438, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x045c, 0xc0, 0x00, CSIPHY_SKEW_CAL},
+ {0x0460, 0x0d, 0x00, CSIPHY_SKEW_CAL},
+ {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+ {0x0630, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c00, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c08, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0c04, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x062c, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0634, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x061c, 0x0a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0614, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x063c, 0xb8, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0600, 0x91, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0604, 0x0c, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0620, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0610, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0638, 0xfe, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x065c, 0xc0, 0x00, CSIPHY_SKEW_CAL},
+ {0x0660, 0x0d, 0x00, CSIPHY_SKEW_CAL},
+ {0x0800, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0000, 0x00, 0x00, CSIPHY_DNP_PARAMS},
+};
+
/* 14nm 2PH v 2.0.1 2p5Gbps 4 lane DPHY mode */
static const struct
csiphy_lane_regs lane_regs_qcm2290[] = {
@@ -1011,6 +1131,7 @@ static bool csiphy_is_gen2(u32 version)
switch (version) {
case CAMSS_2290:
case CAMSS_6150:
+ case CAMSS_6350:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
@@ -1105,6 +1226,10 @@ static int csiphy_init(struct csiphy_device *csiphy)
regs->lane_regs = &lane_regs_qcm2290[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
break;
+ case CAMSS_6350:
+ regs->lane_regs = &lane_regs_sm6350[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
+ break;
case CAMSS_7280:
case CAMSS_8250:
regs->lane_regs = &lane_regs_sm8250[0];
diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 5baf0e3d4bc4..7dc937d018f6 100644
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -343,6 +343,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
case CAMSS_660:
case CAMSS_2290:
case CAMSS_6150:
+ case CAMSS_6350:
case CAMSS_7280:
case CAMSS_8x96:
case CAMSS_8250:
@@ -2003,6 +2004,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
switch (vfe->camss->res->version) {
case CAMSS_6150:
+ case CAMSS_6350:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index 00b87fd9afbd..b53fb94ab54a 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -1703,6 +1703,253 @@ static const struct resources_icc icc_res_sm6150[] = {
},
};
+static const struct camss_subdev_resources csiphy_res_sm6350[] = {
+ /* CSIPHY0 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy0-0p9", .init_load_uA = 80000 },
+ { .supply = "vdd-csiphy0-1p25", .init_load_uA = 80000 },
+ },
+ .clock = { "csiphy0", "csiphy0_timer" },
+ .clock_rate = { { 300000000, 384000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy0" },
+ .interrupt = { "csiphy0" },
+ .csiphy = {
+ .id = 0,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY1 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy1-0p9", .init_load_uA = 80000 },
+ { .supply = "vdd-csiphy1-1p25", .init_load_uA = 80000 },
+ },
+ .clock = { "csiphy1", "csiphy1_timer" },
+ .clock_rate = { { 300000000, 384000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy1" },
+ .interrupt = { "csiphy1" },
+ .csiphy = {
+ .id = 1,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY2 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy2-0p9", .init_load_uA = 80000 },
+ { .supply = "vdd-csiphy2-1p25", .init_load_uA = 80000 },
+ },
+ .clock = { "csiphy2", "csiphy2_timer" },
+ .clock_rate = { { 300000000, 384000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy2" },
+ .interrupt = { "csiphy2" },
+ .csiphy = {
+ .id = 2,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ },
+ /* CSIPHY3 */
+ {
+ .regulators = {
+ { .supply = "vdd-csiphy3-0p9", .init_load_uA = 80000 },
+ { .supply = "vdd-csiphy3-1p25", .init_load_uA = 80000 },
+ },
+ .clock = { "csiphy3", "csiphy3_timer" },
+ .clock_rate = { { 300000000, 384000000, 400000000 },
+ { 300000000 } },
+ .reg = { "csiphy3" },
+ .interrupt = { "csiphy3" },
+ .csiphy = {
+ .id = 3,
+ .hw_ops = &csiphy_ops_3ph_1_0,
+ .formats = &csiphy_formats_sdm845
+ }
+ }
+};
+
+static const struct camss_subdev_resources csid_res_sm6350[] = {
+ /* CSID0 */
+ {
+ .regulators = {},
+ .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" },
+ .clock_rate = { { 300000000, 384000000, 400000000 },
+ { 0 },
+ { 320000000, 404000000, 480000000, 600000000 } },
+ .reg = { "csid0" },
+ .interrupt = { "csid0" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID1 */
+ {
+ .regulators = {},
+ .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" },
+ .clock_rate = { { 300000000, 384000000, 400000000 },
+ { 0 },
+ { 320000000, 404000000, 480000000, 600000000 } },
+ .reg = { "csid1" },
+ .interrupt = { "csid1" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID2 */
+ {
+ .regulators = {},
+ .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" },
+ .clock_rate = { { 300000000, 384000000, 400000000 },
+ { 0 },
+ { 320000000, 404000000, 480000000, 600000000 } },
+ .reg = { "csid2" },
+ .interrupt = { "csid2" },
+ .csid = {
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ },
+ /* CSID3 (lite) */
+ {
+ .regulators = {},
+ .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite" },
+ .clock_rate = { { 300000000, 384000000, 400000000 },
+ { 0 },
+ { 400000000, 480000000 } },
+ .reg = { "csid_lite" },
+ .interrupt = { "csid_lite" },
+ .csid = {
+ .is_lite = true,
+ .hw_ops = &csid_ops_gen2,
+ .parent_dev_ops = &vfe_parent_dev_ops,
+ .formats = &csid_formats_gen2
+ }
+ }
+};
+
+static const struct camss_subdev_resources vfe_res_sm6350[] = {
+ /* VFE0 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "camnoc_axi", "vfe0",
+ "vfe0_axi", "cam_axi", "soc_ahb" },
+ .clock_rate = { { 19200000 },
+ { 0 },
+ { 320000000, 404000000, 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe0" },
+ .interrupt = { "vfe0" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife0",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE1 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "camnoc_axi", "vfe1",
+ "vfe1_axi", "cam_axi", "soc_ahb" },
+ .clock_rate = { { 19200000 },
+ { 0 },
+ { 320000000, 404000000, 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe1" },
+ .interrupt = { "vfe1" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife1",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE2 */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "camnoc_axi", "vfe2",
+ "vfe2_axi", "cam_axi", "soc_ahb" },
+ .clock_rate = { { 19200000 },
+ { 0 },
+ { 320000000, 404000000, 480000000, 600000000 },
+ { 0 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe2" },
+ .interrupt = { "vfe2" },
+ .vfe = {
+ .line_num = 3,
+ .has_pd = true,
+ .pd_name = "ife2",
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+ /* VFE3 (lite) */
+ {
+ .regulators = {},
+ .clock = { "cpas_ahb", "camnoc_axi", "vfe_lite",
+ "cam_axi", "soc_ahb" },
+ .clock_rate = { { 19200000 },
+ { 0 },
+ { 400000000, 480000000 },
+ { 0 },
+ { 0 } },
+ .reg = { "vfe_lite" },
+ .interrupt = { "vfe_lite" },
+ .vfe = {
+ .is_lite = true,
+ .line_num = 4,
+ .hw_ops = &vfe_ops_170,
+ .formats_rdi = &vfe_formats_rdi_845,
+ .formats_pix = &vfe_formats_pix_845
+ }
+ },
+};
+
+static const struct resources_icc icc_res_sm6350[] = {
+ {
+ .name = "ahb",
+ .icc_bw_tbl.avg = 0,
+ .icc_bw_tbl.peak = 300000,
+ },
+ {
+ .name = "hf_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+ {
+ .name = "sf_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+ {
+ .name = "sf_icp_mnoc",
+ .icc_bw_tbl.avg = 2097152,
+ .icc_bw_tbl.peak = 2097152,
+ },
+};
+
static const struct camss_subdev_resources csiphy_res_8250[] = {
/* CSIPHY0 */
{
@@ -5233,6 +5480,19 @@ static const struct camss_resources sm6150_resources = {
.vfe_num = ARRAY_SIZE(vfe_res_sm6150),
};
+static const struct camss_resources sm6350_resources = {
+ .version = CAMSS_6350,
+ .pd_name = "top",
+ .csiphy_res = csiphy_res_sm6350,
+ .csid_res = csid_res_sm6350,
+ .vfe_res = vfe_res_sm6350,
+ .icc_res = icc_res_sm6350,
+ .icc_path_num = ARRAY_SIZE(icc_res_sm6350),
+ .csiphy_num = ARRAY_SIZE(csiphy_res_sm6350),
+ .csid_num = ARRAY_SIZE(csid_res_sm6350),
+ .vfe_num = ARRAY_SIZE(vfe_res_sm6350),
+};
+
static const struct camss_resources sm8250_resources = {
.version = CAMSS_8250,
.pd_name = "top",
@@ -5329,6 +5589,7 @@ static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,sdm670-camss", .data = &sdm670_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm6150-camss", .data = &sm6150_resources },
+ { .compatible = "qcom,sm6350-camss", .data = &sm6350_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
{ .compatible = "qcom,sm8650-camss", .data = &sm8650_resources },
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index 6d048414c919..d323c105d185 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -81,6 +81,7 @@ enum camss_version {
CAMSS_660,
CAMSS_2290,
CAMSS_6150,
+ CAMSS_6350,
CAMSS_7280,
CAMSS_8x16,
CAMSS_8x39,
--
2.53.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v4 3/3] arm64: dts: qcom: sm6350: Add CAMSS node
2026-02-16 8:54 [PATCH v4 0/3] Add CAMSS support for SM6350 Luca Weiss
2026-02-16 8:54 ` [PATCH v4 1/3] dt-bindings: media: camss: Add qcom,sm6350-camss Luca Weiss
2026-02-16 8:54 ` [PATCH v4 2/3] media: qcom: camss: Add SM6350 support Luca Weiss
@ 2026-02-16 8:54 ` Luca Weiss
2 siblings, 0 replies; 4+ messages in thread
From: Luca Weiss @ 2026-02-16 8:54 UTC (permalink / raw)
To: Bryan O'Donoghue, Robert Foss, Todor Tomov,
Vladimir Zapolskiy, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bryan O'Donoghue,
Bjorn Andersson, Konrad Dybcio
Cc: ~postmarketos/upstreaming, phone-devel, linux-arm-msm,
linux-media, devicetree, linux-kernel, Luca Weiss
Add a node for the CAMSS on the SM6350 SoC.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 233 +++++++++++++++++++++++++++++++++++
1 file changed, 233 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 9f9b9f9af0da..9ff9508c5ce6 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -2161,6 +2161,239 @@ cci1_i2c0: i2c-bus@0 {
/* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */
};
+ camss: isp@acb3000 {
+ compatible = "qcom,sm6350-camss";
+
+ reg = <0x0 0x0acb3000 0x0 0x1000>,
+ <0x0 0x0acba000 0x0 0x1000>,
+ <0x0 0x0acc1000 0x0 0x1000>,
+ <0x0 0x0acc8000 0x0 0x1000>,
+ <0x0 0x0ac65000 0x0 0x1000>,
+ <0x0 0x0ac66000 0x0 0x1000>,
+ <0x0 0x0ac67000 0x0 0x1000>,
+ <0x0 0x0ac68000 0x0 0x1000>,
+ <0x0 0x0acaf000 0x0 0x4000>,
+ <0x0 0x0acb6000 0x0 0x4000>,
+ <0x0 0x0acbd000 0x0 0x4000>,
+ <0x0 0x0acc4000 0x0 0x4000>,
+ <0x0 0x0ac18000 0x0 0x3000>,
+ <0x0 0x0ac00000 0x0 0x6000>,
+ <0x0 0x0ac10000 0x0 0x8000>,
+ <0x0 0x0ac6f000 0x0 0x8000>,
+ <0x0 0x0ac42000 0x0 0x4600>,
+ <0x0 0x01fc0000 0x0 0x40000>,
+ <0x0 0x0ac48000 0x0 0x1000>,
+ <0x0 0x0ac40000 0x0 0x1000>,
+ <0x0 0x0ac87000 0x0 0xa000>,
+ <0x0 0x0ac52000 0x0 0x4000>,
+ <0x0 0x0ac4e000 0x0 0x4000>,
+ <0x0 0x0ac6b000 0x0 0xa00>;
+ reg-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite",
+ "a5_csr",
+ "a5_qgic",
+ "a5_sierra",
+ "bps",
+ "camnoc",
+ "core_top_csr_tcsr",
+ "cpas_cdm",
+ "cpas_top",
+ "ipe",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ clocks = <&gcc GCC_CAMERA_AXI_CLK>,
+ <&camcc CAMCC_SOC_AHB_CLK>,
+ <&camcc CAMCC_CAMNOC_AXI_CLK>,
+ <&camcc CAMCC_CORE_AHB_CLK>,
+ <&camcc CAMCC_CPAS_AHB_CLK>,
+ <&camcc CAMCC_CSIPHY0_CLK>,
+ <&camcc CAMCC_CSI0PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY1_CLK>,
+ <&camcc CAMCC_CSI1PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY2_CLK>,
+ <&camcc CAMCC_CSI2PHYTIMER_CLK>,
+ <&camcc CAMCC_CSIPHY3_CLK>,
+ <&camcc CAMCC_CSI3PHYTIMER_CLK>,
+ <&camcc CAMCC_IFE_0_AXI_CLK>,
+ <&camcc CAMCC_IFE_0_CLK>,
+ <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_0_CSID_CLK>,
+ <&camcc CAMCC_IFE_1_AXI_CLK>,
+ <&camcc CAMCC_IFE_1_CLK>,
+ <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_1_CSID_CLK>,
+ <&camcc CAMCC_IFE_2_AXI_CLK>,
+ <&camcc CAMCC_IFE_2_CLK>,
+ <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_2_CSID_CLK>,
+ <&camcc CAMCC_IFE_LITE_CLK>,
+ <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAMCC_IFE_LITE_CSID_CLK>,
+ <&camcc CAMCC_BPS_CLK>,
+ <&camcc CAMCC_BPS_AHB_CLK>,
+ <&camcc CAMCC_BPS_AREG_CLK>,
+ <&camcc CAMCC_BPS_AXI_CLK>,
+ <&camcc CAMCC_ICP_CLK>,
+ <&camcc CAMCC_IPE_0_CLK>,
+ <&camcc CAMCC_IPE_0_AHB_CLK>,
+ <&camcc CAMCC_IPE_0_AREG_CLK>,
+ <&camcc CAMCC_IPE_0_AXI_CLK>,
+ <&camcc CAMCC_JPEG_CLK>,
+ <&camcc CAMCC_LRME_CLK>;
+ clock-names = "cam_axi",
+ "soc_ahb",
+ "camnoc_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy3",
+ "csiphy3_timer",
+ "vfe0_axi",
+ "vfe0",
+ "vfe0_cphy_rx",
+ "vfe0_csid",
+ "vfe1_axi",
+ "vfe1",
+ "vfe1_cphy_rx",
+ "vfe1_csid",
+ "vfe2_axi",
+ "vfe2",
+ "vfe2_cphy_rx",
+ "vfe2_csid",
+ "vfe_lite",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid",
+ "bps",
+ "bps_ahb",
+ "bps_areg",
+ "bps_axi",
+ "icp",
+ "ipe0",
+ "ipe0_ahb",
+ "ipe0_areg",
+ "ipe0_axi",
+ "jpeg",
+ "lrme";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 473 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 472 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy3",
+ "vfe0",
+ "vfe1",
+ "vfe2",
+ "vfe_lite",
+ "a5",
+ "cpas",
+ "cpas_cdm",
+ "jpeg_dma",
+ "jpeg_enc",
+ "lrme";
+
+ interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ahb",
+ "hf_mnoc",
+ "sf_mnoc",
+ "sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x820 0xc0>,
+ <&apps_smmu 0x840 0x0>,
+ <&apps_smmu 0x860 0xc0>,
+ <&apps_smmu 0x880 0x0>,
+ <&apps_smmu 0xc40 0x20>,
+ <&apps_smmu 0xc60 0x20>,
+ <&apps_smmu 0xc80 0x0>,
+ <&apps_smmu 0xca2 0x0>,
+ <&apps_smmu 0xcc0 0x20>,
+ <&apps_smmu 0xce0 0x20>,
+ <&apps_smmu 0xd00 0x20>,
+ <&apps_smmu 0xd20 0x20>,
+ <&apps_smmu 0xd40 0x20>,
+ <&apps_smmu 0xd60 0x20>;
+
+ power-domains = <&camcc IFE_0_GDSC>,
+ <&camcc IFE_1_GDSC>,
+ <&camcc IFE_2_GDSC>,
+ <&camcc TITAN_TOP_GDSC>,
+ <&camcc BPS_GDSC>,
+ <&camcc IPE_0_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "ife2",
+ "top",
+ "bps",
+ "ipe";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+ };
+ };
+
camcc: clock-controller@ad00000 {
compatible = "qcom,sm6350-camcc";
reg = <0x0 0x0ad00000 0x0 0x16000>;
--
2.53.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-02-16 8:57 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2026-02-16 8:54 [PATCH v4 0/3] Add CAMSS support for SM6350 Luca Weiss
2026-02-16 8:54 ` [PATCH v4 1/3] dt-bindings: media: camss: Add qcom,sm6350-camss Luca Weiss
2026-02-16 8:54 ` [PATCH v4 2/3] media: qcom: camss: Add SM6350 support Luca Weiss
2026-02-16 8:54 ` [PATCH v4 3/3] arm64: dts: qcom: sm6350: Add CAMSS node Luca Weiss
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