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From: Svyatoslav Ryhel <clamor95@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Thierry Reding <treding@nvidia.com>,
	Mikko Perttunen <mperttunen@nvidia.com>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Sowjanya Komatineni <skomatineni@nvidia.com>,
	Luca Ceresoli <luca.ceresoli@bootlin.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Hans Verkuil <hverkuil+cisco@kernel.org>,
	Svyatoslav Ryhel <clamor95@gmail.com>
Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	linux-tegra@vger.kernel.org, linux-media@vger.kernel.org,
	linux-staging@lists.linux.dev
Subject: [PATCH v7 10/15] staging: media: tegra-video: tegra20: adjust format align calculations
Date: Tue,  3 Mar 2026 10:42:33 +0200	[thread overview]
Message-ID: <20260303084239.15007-11-clamor95@gmail.com> (raw)
In-Reply-To: <20260303084239.15007-1-clamor95@gmail.com>

Expand supported formats structure with data_type and bit_width fields
required for CSI support. Adjust tegra20_fmt_align by factoring out common
bytesperline and sizeimage calculation logic shared by supported planar
and non-planar formats and leaving planar-related correction under a
switch.

Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 drivers/staging/media/tegra-video/tegra20.c | 39 ++++++++++-----------
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
index c8afc6f2adf2..4b218b9fbc26 100644
--- a/drivers/staging/media/tegra-video/tegra20.c
+++ b/drivers/staging/media/tegra-video/tegra20.c
@@ -280,18 +280,13 @@ static void tegra20_fmt_align(struct v4l2_pix_format *pix, unsigned int bpp)
 	pix->width  = clamp(pix->width,  TEGRA20_MIN_WIDTH,  TEGRA20_MAX_WIDTH);
 	pix->height = clamp(pix->height, TEGRA20_MIN_HEIGHT, TEGRA20_MAX_HEIGHT);
 
+	pix->bytesperline = roundup(pix->width, 8) * bpp;
+	pix->sizeimage = pix->bytesperline * pix->height;
+
 	switch (pix->pixelformat) {
-	case V4L2_PIX_FMT_UYVY:
-	case V4L2_PIX_FMT_VYUY:
-	case V4L2_PIX_FMT_YUYV:
-	case V4L2_PIX_FMT_YVYU:
-		pix->bytesperline = roundup(pix->width, 2) * 2;
-		pix->sizeimage = roundup(pix->width, 2) * 2 * pix->height;
-		break;
 	case V4L2_PIX_FMT_YUV420:
 	case V4L2_PIX_FMT_YVU420:
-		pix->bytesperline = roundup(pix->width, 8);
-		pix->sizeimage = roundup(pix->width, 8) * pix->height * 3 / 2;
+		pix->sizeimage = pix->sizeimage * 3 / 2;
 		break;
 	}
 }
@@ -576,20 +571,24 @@ static const struct tegra_vi_ops tegra20_vi_ops = {
 	.vi_stop_streaming = tegra20_vi_stop_streaming,
 };
 
-#define TEGRA20_VIDEO_FMT(MBUS_CODE, BPP, FOURCC)	\
-{							\
-	.code    = MEDIA_BUS_FMT_##MBUS_CODE,		\
-	.bpp     = BPP,					\
-	.fourcc  = V4L2_PIX_FMT_##FOURCC,		\
+#define TEGRA20_VIDEO_FMT(DATA_TYPE, BIT_WIDTH, MBUS_CODE, BPP, FOURCC)	\
+{									\
+	.img_dt		= TEGRA_IMAGE_DT_##DATA_TYPE,			\
+	.bit_width	= BIT_WIDTH,					\
+	.code		= MEDIA_BUS_FMT_##MBUS_CODE,			\
+	.bpp		= BPP,						\
+	.fourcc		= V4L2_PIX_FMT_##FOURCC,			\
 }
 
 static const struct tegra_video_format tegra20_video_formats[] = {
-	TEGRA20_VIDEO_FMT(UYVY8_2X8, 2, UYVY),
-	TEGRA20_VIDEO_FMT(VYUY8_2X8, 2, VYUY),
-	TEGRA20_VIDEO_FMT(YUYV8_2X8, 2, YUYV),
-	TEGRA20_VIDEO_FMT(YVYU8_2X8, 2, YVYU),
-	TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YUV420),
-	TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YVU420),
+	/* YUV422 */
+	TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 2, UYVY),
+	TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 2, VYUY),
+	TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 2, YUYV),
+	TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 2, YVYU),
+	/* YUV420P */
+	TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 1, YUV420),
+	TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 1, YVU420),
 };
 
 const struct tegra_vi_soc tegra20_vi_soc = {
-- 
2.51.0


  parent reply	other threads:[~2026-03-03  8:43 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-03  8:42 [PATCH v7 00/15] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 01/15] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 02/15] staging: media: tegra-video: vi: adjust get_selection operation check Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 03/15] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 04/15] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 05/15] gpu: host1x: convert MIPI to use operation function pointers Svyatoslav Ryhel
2026-03-17 13:07   ` Hans Verkuil
2026-03-19  2:20     ` Mikko Perttunen
2026-03-20 14:04       ` Thierry Reding
2026-03-03  8:42 ` [PATCH v7 06/15] staging: media: tegra-video: vi: improve logic of source requesting Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 07/15] staging: media: tegra-video: csi: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 08/15] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 09/15] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2026-03-03  8:42 ` Svyatoslav Ryhel [this message]
2026-03-03  8:42 ` [PATCH v7 11/15] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 12/15] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 13/15] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422/YUV420p 1X16 Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 14/15] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2026-03-03  8:42 ` [PATCH v7 15/15] staging: media: tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2026-03-05  9:24 ` [PATCH v7 00/15] " Svyatoslav Ryhel
2026-03-17 10:04   ` Luca Ceresoli

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