From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2B7627F75C for ; Wed, 25 Mar 2026 14:51:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774450273; cv=none; b=GWp/uIytvELJPuUbnpI/tZYCz5tcqUZdWCu9Bl8tXZgdc5AlMEyINeF2FGngUFnFsnf+Jl7eQtyAkY6Yb5m4lvXKyAC9uhhYH/LiEf872tcmZkpgvSQSfKzlOCJvyldG4giAeaibpGNgmnSh65bE/fztSJuox+oea78iR34T6gw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774450273; c=relaxed/simple; bh=ObZviKpJk4gfdCnRY802bi/Mc/33SGuma6hYQ7oO8iE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dfiZPHdjuvonV5OGemq4Ge+izn8e6cvE9qEQbuDoFEOfRbasimUZFnEWa33TG/1SBQ8yjEZroH9p9grk5GnU1Zy1DJGjj0KpDqolOEMXMd+Oy6X2239Pp7ON/wPv6kI6ms8htomnBt4P5SbNwn6o5cFZBvsv5tKeXx9sRl2dIUo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from ptz.office.stw.pengutronix.de ([2a0a:edc0:0:900:1d::77] helo=peter.mobile.pengutronix.de) by metis.whiteo.stw.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1w5PZX-00050C-8q; Wed, 25 Mar 2026 15:51:03 +0100 From: =?utf-8?q?Sven_P=C3=BCschel?= Date: Wed, 25 Mar 2026 15:50:58 +0100 Subject: [PATCH v4 27/27] arm64: dts: rockchip: add rga3 dt nodes Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260325-spu-rga3-v4-27-e90ec1c61354@pengutronix.de> References: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de> In-Reply-To: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de> To: Jacob Chen , Ezequiel Garcia , Mauro Carvalho Chehab , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, nicolas@ndufresne.ca, sebastian.reichel@collabora.com, =?utf-8?q?Sven_P=C3=BCschel?= X-Mailer: b4 0.15.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:900:1d::77 X-SA-Exim-Mail-From: s.pueschel@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-media@vger.kernel.org Add devicetree nodes for the RGA3 (Raster Graphics Acceleration 3) peripheral in the RK3588. The existing rga node refers to the RGA2-Enhanced peripheral. The RK3588 contains one RGA2-Enhanced core and two RGA3 cores. Both feature a similar functionality of scaling, cropping and rotating of up to two input images into one output image. Key differences of the RGA3 are: - supports 10bit YUV output formats - supports 8x8 tiles and FBCD as inputs and outputs - supports BT2020 color space conversion - max output resolution of (8192-64)x(8192-64) - MMU can map up to 32G DDR RAM - fully planar formats (3 planes) are not supported - max scale up/down factor of 8 (RGA2 allows up to 16) Signed-off-by: Sven Püschel --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index 7fe9593d8c198..87334636544f8 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -1273,6 +1273,50 @@ rga: rga@fdb80000 { power-domains = <&power RK3588_PD_VDPU>; }; + rga3_core0: rga@fdb60000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb60000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_0_CORE>, <&cru SRST_A_RGA3_0>, <&cru SRST_H_RGA3_0>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA30>; + iommus = <&rga3_0_mmu>; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA30>; + }; + + rga3_core1: rga@fdb70000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb70000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_1_CORE>, <&cru SRST_A_RGA3_1>, <&cru SRST_H_RGA3_1>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA31>; + iommus = <&rga3_1_mmu>; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA31>; + }; + vepu121_0: video-codec@fdba0000 { compatible = "rockchip,rk3588-vepu121"; reg = <0x0 0xfdba0000 0x0 0x800>; -- 2.53.0