[PATCH] media: ccs-pll: Fix OP_SYS_DDR handling in op_sys_clk_freq_hz_sdr calculation

[Alexander Shiyan <eagle.alexander923@gmail.com>]

When OP_SYS_DDR flag is set, the PLL's effective SDR-equivalent
frequency should be based on the link frequency (bitrate per lane)
without an extra factor of 2, because two bits are transferred per
clock cycle. The current code always multiplies link_freq by 2,
overestimating the effective frequency for DDR mode. This leads to
excessive VCO frequencies and PLL calculation failures for high link
frequencies.

Fix this by halving the multiplication factor when OP_SYS_DDR is set.

All further calculations (pixel_rate_csi, mul/div, sys_clk_freq_hz,
pix_clk_freq_hz) remain consistent because sys_clk_freq_hz is
additionally shifted by op_sys_ddr().

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 drivers/media/i2c/ccs-pll.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 1605cfa5db19..788dec797259 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -801,9 +801,11 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 	switch (pll->bus_type) {
 	case CCS_PLL_BUS_TYPE_CSI2_DPHY:
 	case CCS_PLL_BUS_TYPE_CSI2_CPHY:
-		op_sys_clk_freq_hz_sdr = pll->link_freq * 2
+		op_sys_clk_freq_hz_sdr = pll->link_freq
 			* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
 			   1 : pll->csi2.lanes);
+		if (!(pll->flags & CCS_PLL_FLAG_OP_SYS_DDR))
+			op_sys_clk_freq_hz_sdr *= 2;
 		break;
 	default:
 		return -EINVAL;
-- 
2.52.0