From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCE1D3D410D; Wed, 13 May 2026 07:17:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=68.232.154.123 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778656674; cv=none; b=Q2A9WhAPFNFU6uOGaH71IPtd55gVTJPgHrWOCeaKRVXUQRZGyaf4zBnUci/OOzhTDEqXaeis9B7WY0s6YIMB4VQkAlH7EL6AXVIF/f+q6paDG7BRvjvw4Ves/O5464GpoAFjWxQhwvL0DxHe6sBUgAL1PE2v3qkI3K/Nro4KzQI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778656674; c=relaxed/simple; bh=bDCNkFWrqc1yiAAN0gpdMujJO3mWbHOblXWtB3kw2r0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GH27sX3JJiRcUVKqCNh8Nhv6nSxgf64blyxm9hoHPL77ATwCDRF+RhlNqNxdJI/idLWy/LQeywW1wYV+5LPRVWCev4R3KjtyDIEjPomSXPyNKnRQoB8My3hOPZxPUMPIlLXgy6ci7nHElqahttcGbLM25C0teE3SLYNtq9XJOwI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com; spf=pass smtp.mailfrom=microchip.com; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b=fRSs6W7e; arc=none smtp.client-ip=68.232.154.123 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=microchip.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=microchip.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=microchip.com header.i=@microchip.com header.b="fRSs6W7e" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1778656673; x=1810192673; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bDCNkFWrqc1yiAAN0gpdMujJO3mWbHOblXWtB3kw2r0=; b=fRSs6W7eNUbpRHAbEehMjpdbD9hKK+8yOyg9gtUrdscXNzHthVERutPl aXiCMiLbInsPfhgFn1ZsvQPMZOUaWXiAOjFPubZDc33fKodkIjYtU0jGp 2C3xXD0YjHdW23D55npxmlHnU5HKCvFzlLSjS31oiAzS8tv9AaanV/jiy aoc37IWZpA7bV+IpY0NKKOSltY5Gi+cIrT6jpV8HweWZTfnUHf6OtVhHb OEEG/vJKTZelywS2H60pPwmb2VPU0EhwM8SEVXyhV18JB4UNRkjDw9QWd 33hjRAjEYtknDv2CF/mF3WbSJ8tz7oV7YObLa82Gm58LmJ+qx+QtCJeAX g==; X-CSE-ConnectionGUID: d1B9Q248RhOtsSl+i6PAHw== X-CSE-MsgGUID: L2gCghXKRoWRkaPogBLiJw== X-IronPort-AV: E=Sophos;i="6.23,232,1770620400"; d="scan'208";a="56656508" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 May 2026 00:17:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.87.71) by chn-vm-ex4.mchp-main.com (10.10.87.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.37; Wed, 13 May 2026 00:17:52 -0700 Received: from che-ll-i71840.microchip.com (10.10.85.11) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.58 via Frontend Transport; Wed, 13 May 2026 00:17:49 -0700 From: Balakrishnan Sambath To: CC: , , , , Subject: [PATCH v3 02/15] media: microchip-isc: mask WB offset and gain register fields Date: Wed, 13 May 2026 12:47:29 +0530 Message-ID: <20260513071742.97263-3-balakrishnan.s@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260513071742.97263-1-balakrishnan.s@microchip.com> References: <20260512154339.210444-1-balakrishnan.s@microchip.com> <20260513071742.97263-1-balakrishnan.s@microchip.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain ISC_WB_O_* and ISC_WB_G_* pack two 13-bit fields per register. Sign extension from negative offsets corrupts the upper field. Mask both fields to 13 bits before packing. Fixes: 91b4e487b0c6 ("media: microchip: add ISC driver as Microchip ISC") Cc: stable@vger.kernel.org Signed-off-by: Balakrishnan Sambath --- .../platform/microchip/microchip-isc-base.c | 21 ++++++++++++------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/driver= s/media/platform/microchip/microchip-isc-base.c index a7cdc743fda7..45b94f1e89d8 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -61,18 +61,23 @@ static inline void isc_update_awb_ctrls(struct isc_devi= ce *isc) =20 /* In here we set our actual hw pipeline config */ =20 + /* + * Mask offset fields to 13 bits. Sign extension of negative s32 + * values would otherwise corrupt the adjacent field. + */ regmap_write(isc->regmap, ISC_WB_O_RGR, - ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_O_BGB, - ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + ((u32)ctrls->offset[ISC_HIS_CFG_MODE_B] & GENMASK(12, 0)) | + (((u32)ctrls->offset[ISC_HIS_CFG_MODE_GB] & GENMASK(12, 0)) << 16)); + /* Gains are 13-bit unsigned fields [12:0] and [28:16] */ regmap_write(isc->regmap, ISC_WB_G_RGR, - ctrls->gain[ISC_HIS_CFG_MODE_R] | - (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + (ctrls->gain[ISC_HIS_CFG_MODE_R] & GENMASK(12, 0)) | + ((ctrls->gain[ISC_HIS_CFG_MODE_GR] & GENMASK(12, 0)) << 16)); regmap_write(isc->regmap, ISC_WB_G_BGB, - ctrls->gain[ISC_HIS_CFG_MODE_B] | - (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); + (ctrls->gain[ISC_HIS_CFG_MODE_B] & GENMASK(12, 0)) | + ((ctrls->gain[ISC_HIS_CFG_MODE_GB] & GENMASK(12, 0)) << 16)); } =20 static inline void isc_reset_awb_ctrls(struct isc_device *isc) --=20 2.34.1