From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10E1A399013 for ; Sun, 12 Jul 2026 11:52:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783857148; cv=none; b=d+OaAoydkD97prXDOh5irr7WhEzZ+V3oQAjzqqZBfd1z0XJ/j49GafXebtnq67xQ8UCxddczQW3igqsn52Wm4q0hcs5iTjBC0tJWImv05aTKxHYC56QcDhYZsztT8fkc0WNg/SO4sIlstVN5f0zyfTAJ5QNxtBbDsRUg5yU4z4c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783857148; c=relaxed/simple; bh=q+ddrb5rYif3qeX2sXyF+JWJUbajh9aLGpbWw5Dck34=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q74QwZWALrVUclBrFqfae6cDamkK/qSGILeOfn5dXOTPYWTpaZlMYWabTW2dQQUQVtL/NMAypCqiXtJMB1SGs4klM/99FaUnjw6+4tjURyQTQ8GsWq/g5MVl1mII87x1wHfoTnpbTa1VGRJy0MLXSZhgv59rsajOFcz/us7k/7A= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=XPSbXbw8; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="XPSbXbw8" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-2caced6038eso25965095ad.0 for ; Sun, 12 Jul 2026 04:52:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1783857146; x=1784461946; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=6dXvkgr3glg7kJCZbznRyT5LNMiM0E/jveTDZSgSRdw=; b=XPSbXbw88QqQ4eoMwXBvy2piqATSM4IEjGmFMpD4A5z5ERGNJjOi2RvWSIsp+2IXnu 6p0MDq/eXWa6CQKt2UVdJvBvx3NXv1n4yG869+LvSkhjUFquqLmFb0/j3vTxa48Mk2Zz mCR8unywzTPnDgj+0gp7AMSY1snq59W7e4r7djfRRdttC1nn/VkVLjqPsIOeSZVWKN9T yESGMjA5BcC5+5N3Hu9v5rSmMEZhhLmT0SYRqAV1TGe0gsjqdoMw8EeCfQYj9d7Ve7BQ C44LcTN5cFXyjW0DRIjkzsfjbBZgFmF8spN12++hna/nP/EEn4x5gzbVHpK86xxcvxOs ZWUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1783857146; x=1784461946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=6dXvkgr3glg7kJCZbznRyT5LNMiM0E/jveTDZSgSRdw=; b=Nth4HX0GKqt6kXewFVQdrXxSBa0CP4vvvRKcpahT1qt59DfkRBrD6e5HfW8svuaOVN BxStRNC5ACuX/8iYG8b0ydcN1QyhlFtLrW7mH/1mrnM5bWtG4Wi/16Muwp7/K3yl8zib VoDV/ASOCjn2Gw8anT980rQZHBRTQvMcvgrNnAkKkiRELAiDOot3VEd0eKbp72A4TcQP 48juHeFsQ7nygptlLlXqXKgCD3YazmPyAdN0cS8YULUjGUyOsUNRaauRXI6S8EIeLvix Yfv5V2qZVn4iUoSytJhjwFCYNMAalzTw2dQGE0rahRwjfgRVjmgPx+1HXrKKM65EVCiZ 7Hjw== X-Forwarded-Encrypted: i=1; AHgh+RqbkBM9lNDGs0W46gtRQ0V2mFBwR3QbwBzcjaNeDT9biL6DxzeKceN2Wp5LybOv1mgxEelStidGdoGw7A==@vger.kernel.org X-Gm-Message-State: AOJu0YwVSY1EDZ3m1PZxZ45TvRD9PP7uBZguIsfcic9ruF6MdKzdfjJo ZSmeW1nnB8S5hGJvPRIVPFMWfngteeyXvjierzS4WdX79Hiq5xr20XE8 X-Gm-Gg: AfdE7clHFbp5XiybRBZHSpp6HbynJmXwGKEwtDROo27V+/LVErC/KAMtc32XI0h55nU 1Yv6/v+cDbktwvxXbFAIJ7AhQfrzrI/0OYSARdD/mOfqgJYs9hiISqcSK4LTH4cNs/2ItzeKUbF UQQ0SWZ2qC10pOs3D9GocMurzRL18JH/oV32SRrnovVcnivt7wviZDXYU6GBfOzXsWxH/Bxgx6o jgsGX5efhrBfWtNia3M97TJvK4j2xLTn4Kq2nSmyMu1jU1I5kAwaqftbVWmY31fHXPRqblObZgz axUmApz8J1i/zYfVF5FOcXF/cQELOBRr6/Az50yVRH0QiAMTuhv7GXe9meC7I/ApVsCDoTK9PUt 2Q/Sm7VCbjBk1wOVhUwoH9l0EeQtiRMTYuOV6Xw/QOL0SBwZGIvKQ2i6hklP21+vPzDUW4r1Z6p Ae9NXwukTse/BK3eLylKNyi5X8/h8D1q7Ig22WsRs= X-Received: by 2002:a17:902:ce8a:b0:2ca:c847:8e41 with SMTP id d9443c01a7336-2cea17f9ad8mr50877445ad.11.1783857146424; Sun, 12 Jul 2026 04:52:26 -0700 (PDT) Received: from nuvole ([144.202.86.13]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ccc9bfe040sm84538295ad.31.2026.07.12.04.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Jul 2026 04:52:26 -0700 (PDT) From: Pengyu Luo To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Sakari Ailus , Martin Kepplinger-Novakovic , Mauro Carvalho Chehab , Hans Verkuil , Sebastian Krzyszkowiak Cc: devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Pengyu Luo Subject: [PATCH v5 4/5] media: hi846: Add 6MP and 8MP modes support Date: Sun, 12 Jul 2026 19:50:11 +0800 Message-ID: <20260712115012.91600-5-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260712115012.91600-1-mitltlatltl@gmail.com> References: <20260712115012.91600-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi846 is an 8MP sensor, but the upstream driver has only supported 2MP mode for years. This patch adds 6MP and 8MP modes to maximize sensor utilization. Note that these modes require 4-lane MIPI CSI-2, as the downstream driver only exposes 2MP, 6MP, and 8MP configurations in 4-lane operation on the target device. The register sequences are extracted from the downstream Windows driver. Signed-off-by: Pengyu Luo --- v5: - Use separated fields instead of raw register values for PLL cfg (Sakari) --- drivers/media/i2c/hi846.c | 154 +++++++++++++++++++++++++++++++++++++- 1 file changed, 153 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/hi846.c b/drivers/media/i2c/hi846.c index 1223567641c4..cb06fc4188a6 100644 --- a/drivers/media/i2c/hi846.c +++ b/drivers/media/i2c/hi846.c @@ -1028,6 +1028,106 @@ static const struct hi846_reg mode_1632x1224_mipi_4lane[] = { {HI846_REG_TG_ENABLE, 0x0100}, }; +static const struct hi846_reg mode_3264x1836_config[] = { + {HI846_REG_MODE_SELECT, 0x0000}, + {HI846_REG_Y_ODD_INC_FOBP, 0x1111}, + {HI846_REG_Y_ODD_INC_VACT, 0x1111}, + {HI846_REG_Y_ADDR_START_VACT_H, 0x0172}, + {HI846_REG_Y_ADDR_END_VACT_H, 0x089d}, + {HI846_REG_UNKNOWN_005C, 0x2101}, + {HI846_REG_FLL, 0x09de}, + {HI846_REG_LLP, 0x0ed8}, + {HI846_REG_BINNING_MODE, 0x0022}, + {HI846_REG_HBIN_MODE, 0x0000}, + {HI846_REG_UNKNOWN_0A24, 0x0000}, + {HI846_REG_X_START_H, 0x0000}, + {HI846_REG_X_OUTPUT_SIZE_H, 0x0cc0}, + {HI846_REG_Y_OUTPUT_SIZE_H, 0x072c}, + {HI846_REG_EXPOSURE, 0x09d8}, + + /* For OTP */ + {HI846_REG_UNKNOWN_021C, 0x0001}, + {HI846_REG_UNKNOWN_021E, 0x0235}, + + {HI846_REG_ISP_EN_H, 0x014a}, + {HI846_REG_UNKNOWN_0418, 0x023e}, + {HI846_REG_UNKNOWN_0B02, 0xe04d}, + {HI846_REG_UNKNOWN_0B10, 0x6821}, + {HI846_REG_UNKNOWN_0B12, 0x0120}, + {HI846_REG_UNKNOWN_0B14, 0x0001}, + {HI846_REG_UNKNOWN_2008, 0x38fd}, + {HI846_REG_UNKNOWN_326E, 0x0000}, +}; + +static const struct hi846_reg mode_3264x1836_mipi_4lane[] = { + {HI846_REG_UNKNOWN_0900, 0x0300}, + {HI846_REG_MIPI_TX_OP_MODE, 0xc319}, + {HI846_REG_UNKNOWN_0914, 0xc109}, + {HI846_REG_TCLK_PREPARE, 0x061a}, + {HI846_REG_UNKNOWN_0918, 0x0407}, + {HI846_REG_THS_ZERO, 0x0a0b}, + {HI846_REG_TCLK_POST, 0x0e08}, + {HI846_REG_UNKNOWN_091E, 0x0a00}, + {HI846_REG_UNKNOWN_090C, 0x0427}, + {HI846_REG_UNKNOWN_090E, 0x0059}, + {HI846_REG_UNKNOWN_0954, 0x0089}, + {HI846_REG_UNKNOWN_0956, 0x0000}, + {HI846_REG_UNKNOWN_0958, 0xca80}, + {HI846_REG_UNKNOWN_095A, 0x9240}, + {HI846_REG_PLL_CFG_MIPI2_H, 0x4124}, + {HI846_REG_TG_ENABLE, 0x0100}, +}; + +static const struct hi846_reg mode_3264x2448_config[] = { + {HI846_REG_MODE_SELECT, 0x0000}, + {HI846_REG_Y_ODD_INC_FOBP, 0x1111}, + {HI846_REG_Y_ODD_INC_VACT, 0x1111}, + {HI846_REG_Y_ADDR_START_VACT_H, 0x0040}, + {HI846_REG_Y_ADDR_END_VACT_H, 0x09cf}, + {HI846_REG_UNKNOWN_005C, 0x2101}, + {HI846_REG_FLL, 0x09de}, + {HI846_REG_LLP, 0x0ed8}, + {HI846_REG_BINNING_MODE, 0x0022}, + {HI846_REG_HBIN_MODE, 0x0000}, + {HI846_REG_UNKNOWN_0A24, 0x0000}, + {HI846_REG_X_START_H, 0x0000}, + {HI846_REG_X_OUTPUT_SIZE_H, 0x0cc0}, + {HI846_REG_Y_OUTPUT_SIZE_H, 0x0990}, + {HI846_REG_EXPOSURE, 0x09d8}, + + /* For OTP */ + {HI846_REG_UNKNOWN_021C, 0x0001}, + {HI846_REG_UNKNOWN_021E, 0x0235}, + + {HI846_REG_ISP_EN_H, 0x014a}, + {HI846_REG_UNKNOWN_0418, 0x0000}, + {HI846_REG_UNKNOWN_0B02, 0xe04d}, + {HI846_REG_UNKNOWN_0B10, 0x6821}, + {HI846_REG_UNKNOWN_0B12, 0x0120}, + {HI846_REG_UNKNOWN_0B14, 0x0001}, + {HI846_REG_UNKNOWN_2008, 0x38fd}, + {HI846_REG_UNKNOWN_326E, 0x0000}, +}; + +static const struct hi846_reg mode_3264x2448_mipi_4lane[] = { + {HI846_REG_UNKNOWN_0900, 0x0300}, + {HI846_REG_MIPI_TX_OP_MODE, 0xc319}, + {HI846_REG_UNKNOWN_0914, 0xc109}, + {HI846_REG_TCLK_PREPARE, 0x061a}, + {HI846_REG_UNKNOWN_0918, 0x0407}, + {HI846_REG_THS_ZERO, 0x0a0b}, + {HI846_REG_TCLK_POST, 0x0e08}, + {HI846_REG_UNKNOWN_091E, 0x0a00}, + {HI846_REG_UNKNOWN_090C, 0x0427}, + {HI846_REG_UNKNOWN_090E, 0x0059}, + {HI846_REG_UNKNOWN_0954, 0x0089}, + {HI846_REG_UNKNOWN_0956, 0x0000}, + {HI846_REG_UNKNOWN_0958, 0xca80}, + {HI846_REG_UNKNOWN_095A, 0x9240}, + {HI846_REG_PLL_CFG_MIPI2_H, 0x4124}, + {HI846_REG_TG_ENABLE, 0x0100}, +}; + static const char * const hi846_test_pattern_menu[] = { "Disabled", "Solid Colour", @@ -1136,7 +1236,59 @@ static const struct hi846_mode supported_modes[] = { .width = 1632 * 2, .height = 1224 * 2, }, - } + }, + { + .width = 3264, + .height = 1836, + .mipi_clk_div_2lane = 1, /* dummy */ + .mipi_clk_div_4lane = 2, + .fps = 30, + .frame_len = 2526, + .llp = HI846_LINE_LENGTH, + .reg_list_config = { + .num_of_regs = ARRAY_SIZE(mode_3264x1836_config), + .regs = mode_3264x1836_config, + }, + .reg_list_2lane = { + .num_of_regs = 0, + }, + .reg_list_4lane = { + .num_of_regs = ARRAY_SIZE(mode_3264x1836_mipi_4lane), + .regs = mode_3264x1836_mipi_4lane, + }, + .crop = { + .left = 0x46, + .top = 0x172, + .width = 3264, + .height = 1836, + }, + }, + { + .width = 3264, + .height = 2448, + .mipi_clk_div_2lane = 1, /* dummy */ + .mipi_clk_div_4lane = 2, + .fps = 30, + .frame_len = 2526, + .llp = HI846_LINE_LENGTH, + .reg_list_config = { + .num_of_regs = ARRAY_SIZE(mode_3264x2448_config), + .regs = mode_3264x2448_config, + }, + .reg_list_2lane = { + .num_of_regs = 0, + }, + .reg_list_4lane = { + .num_of_regs = ARRAY_SIZE(mode_3264x2448_mipi_4lane), + .regs = mode_3264x2448_mipi_4lane, + }, + .crop = { + .left = 0x46, + .top = 0x40, + .width = 3264, + .height = 2448, + }, + }, }; struct hi846_datafmt { -- 2.54.0