From: Vladimir Zapolskiy <vz@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>,
Bryan O'Donoghue <bod@kernel.org>, Vinod Koul <vkoul@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Loic Poulain <loic.poulain@oss.qualcomm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-media@vger.kernel.org,
Neil Armstrong <neil.armstrong@linaro.org>,
Manivannan Sadhasivam <mani@kernel.org>,
linux-phy@lists.infradead.org, Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org
Subject: [PATCH 2/7] arm64: dts: qcom: sm8450: Add CSI2 PHY device tree nodes
Date: Fri, 23 Oct 2026 19:30:52 +0300 [thread overview]
Message-ID: <20261023163057.775917-3-vz@kernel.org> (raw)
In-Reply-To: <20261023163057.775917-1-vz@kernel.org>
Add device tree nodes of six CAMSS CSIPHYs found on Qualcomm Waipio SoC,
and a shared CSIPHY OPP table for them.
Signed-off-by: Vladimir Zapolskiy <vz@kernel.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 280 +++++++++++++++++++++++++++
1 file changed, 280 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 05417cb5c4e5..babf1a4196a1 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -564,6 +564,22 @@ cluster_pd: power-domain-cpu-cluster0 {
};
};
+ csiphy_opp_table: opp-table-csiphy {
+ compatible = "operating-points-v2";
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+ };
+
qup_opp_table_100mhz: opp-table-qup {
compatible = "operating-points-v2";
@@ -3294,6 +3310,270 @@ cci1_i2c1: i2c-bus@1 {
};
};
+ csiphy0: phy@ace4000 {
+ compatible = "qcom,waipio-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0 0x0ace4000 0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy0_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy0_out_ep: endpoint {
+ };
+ };
+ };
+ };
+
+ csiphy1: phy@ace6000 {
+ compatible = "qcom,waipio-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0 0x0ace6000 0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy1_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy1_out_ep: endpoint {
+ };
+ };
+ };
+ };
+
+ csiphy2: phy@ace8000 {
+ compatible = "qcom,waipio-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0 0x0ace8000 0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy2_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy2_out_ep: endpoint {
+ };
+ };
+ };
+ };
+
+ csiphy3: phy@acea000 {
+ compatible = "qcom,waipio-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0 0x0acea000 0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy3_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy3_out_ep: endpoint {
+ };
+ };
+ };
+ };
+
+ csiphy4: phy@acec000 {
+ compatible = "qcom,waipio-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0 0x0acec000 0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy4_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy4_out_ep: endpoint {
+ };
+ };
+ };
+ };
+
+ csiphy5: phy@acee000 {
+ compatible = "qcom,waipio-csi2-phy", "qcom,x1e80100-csi2-phy";
+ reg = <0 0x0acee000 0 0x2000>;
+
+ clocks = <&camcc CAM_CC_CSIPHY5_CLK>,
+ <&camcc CAM_CC_CSI5PHYTIMER_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>;
+ clock-names = "core",
+ "timer",
+ "ahb";
+
+ interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+
+ power-domains = <&camcc TITAN_TOP_GDSC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
+ power-domain-names = "top",
+ "mmcx",
+ "mx";
+
+ operating-points-v2 = <&csiphy_opp_table>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csiphy5_in_ep: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csiphy5_out_ep: endpoint {
+ };
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,sm8450-camcc";
reg = <0 0x0ade0000 0 0x20000>;
--
2.53.0
next prev parent reply other threads:[~2026-10-23 16:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-23 16:30 [PATCH 0/7] media: qcom: camss: Add Waipio CAMSS support Vladimir Zapolskiy
2026-10-23 16:30 ` [PATCH 1/7] dt-bindings: phy: qcom,x1e80100-csi2-phy: Add Waipio compatible Vladimir Zapolskiy
2026-10-23 22:43 ` Bryan O'Donoghue
2026-10-23 16:30 ` Vladimir Zapolskiy [this message]
2026-10-23 22:44 ` [PATCH 2/7] arm64: dts: qcom: sm8450: Add CSI2 PHY device tree nodes Bryan O'Donoghue
2026-10-23 16:30 ` [PATCH 3/7] dt-bindings: media: Add description of Qualcomm Waipio CAMSS IP Vladimir Zapolskiy
2026-10-23 16:30 ` [PATCH 4/7] arm64: dts: qcom: sm8450: Add CAMSS device tree node Vladimir Zapolskiy
2026-10-23 16:30 ` [PATCH 5/7] arm64: dts: qcom: sm8450: Add description of pins with MCLK function Vladimir Zapolskiy
2026-10-23 16:30 ` [PATCH 6/7] media: qcom: camss: Allow CSI2 PHY devices without CSIPHY resources Vladimir Zapolskiy
2026-10-23 16:30 ` [PATCH 7/7] media: qcom: camss: Add Waipio CAMSS support Vladimir Zapolskiy
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