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Fri, 30 Oct 2026 22:35:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1793396150; bh=mhvqEixdDbdzdKOTvnXWf9scL4yTOZMFHRlK1GjWEZM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Q6f/BoxDuUcNEpgNKmjpwv32hVuO7+97TwlOliyS1O/NIMXvvAQ8L6jJHeSv03vnS xeq1/GzIVeX91waAx0db4Lc2QSu82iVn41eCtBV7gl01Ljz9mX9KDyngeAdXc7+rPk tqPPPFGL+DGl2ZQwVoILu/+gSyPzypQSBUyQAesk= Date: Fri, 30 Oct 2026 23:38:03 +0200 From: Laurent Pinchart To: Paul Elder Cc: Geert Uytterhoeven , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Ulf Hansson , Mauro Carvalho Chehab , Philipp Zabel , Kieran Bingham , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org Subject: Re: [PATCH DNI v3 05/15] arm64: renesas: r8a78000: Add VSP[BI] nodes Message-ID: <20261030213803.GC3178046@killaraus.ideasonboard.com> References: <20261015-epaul-v7-3-rc1-x5h-vsp-fcp-v3-0-e052903a3832@ideasonboard.com> <20261015-epaul-v7-3-rc1-x5h-vsp-fcp-v3-5-e052903a3832@ideasonboard.com> X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20261015-epaul-v7-3-rc1-x5h-vsp-fcp-v3-5-e052903a3832@ideasonboard.com> Hi Paul, On Thu, Oct 15, 2026 at 04:51:45PM +0900, Paul Elder wrote: > From: Laurent Pinchart > > Add DT nodes for the VSPB and VSPI IP cores in the R-Car X5H SoC. > > Signed-off-by: Laurent Pinchart > Signed-off-by: Paul Elder > Reviewed-by: Laurent Pinchart > Tested-by: Laurent Pinchart > --- > arch/arm64/boot/dts/renesas/r8a78000.dtsi | 99 +++++++++++++++++++++++++++++++ > 1 file changed, 99 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi > index 2f8886f8b6545026397fd83969882f8c62afa9d3..f90b869579d384e3fc13d0a13625b7cddaac2868 100644 > --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi > @@ -1072,6 +1072,105 @@ fcpvb4: fcp@c503c000 { > resets = <&mdlc_vio 0x106>; > }; > > + vspi0: vsp@c5080000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc5080000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; For the reason explained in 04/15, I would use R8A78000_CPG_SGD1_VIO_DP_OTHER here and below. > + power-domains = <&mdlc_vio 0x07 0xfe>; > + resets = <&mdlc_vio 0xfe>; > + > + renesas,fcp = <&fcpvi0>; > + }; > + > + vspi1: vsp@c5088000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc5088000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; > + power-domains = <&mdlc_vio 0x07 0xff>; > + resets = <&mdlc_vio 0xff>; > + > + renesas,fcp = <&fcpvi1>; > + }; > + > + vspi2: vsp@c5090000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc5090000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; > + power-domains = <&mdlc_vio 0x07 0x100>; > + resets = <&mdlc_vio 0x100>; > + > + renesas,fcp = <&fcpvi2>; > + }; > + > + vspi3: vsp@c5098000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc5098000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; > + power-domains = <&mdlc_vio 0x07 0x101>; > + resets = <&mdlc_vio 0x101>; > + > + renesas,fcp = <&fcpvi3>; > + }; > + > + vspb0: vsp@c50c0000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc50c0000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; > + power-domains = <&mdlc_vio 0x07 0xf9>; > + resets = <&mdlc_vio 0xf9>; > + > + renesas,fcp = <&fcpvb0>; > + }; > + > + vspb1: vsp@c50c8000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc50c8000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; > + power-domains = <&mdlc_vio 0x07 0xfa>; > + resets = <&mdlc_vio 0xfa>; > + > + renesas,fcp = <&fcpvb1>; > + }; > + > + vspb2: vsp@c50d0000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc50d0000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; > + power-domains = <&mdlc_vio 0x07 0xfb>; > + resets = <&mdlc_vio 0xfb>; > + > + renesas,fcp = <&fcpvb2>; > + }; > + > + vspb3: vsp@c50d8000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc50d8000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; > + power-domains = <&mdlc_vio 0x07 0xfc>; > + resets = <&mdlc_vio 0xfc>; > + > + renesas,fcp = <&fcpvb3>; > + }; > + > + vspb4: vsp@c50e0000 { > + compatible = "renesas,vsp2"; > + reg = <0 0xc50e0000 0 0x8000>; > + interrupts = ; > + clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>; > + power-domains = <&mdlc_vio 0x07 0xfd>; > + resets = <&mdlc_vio 0xfd>; > + > + renesas,fcp = <&fcpvb4>; > + }; > + > mdlc_cmnn: system-controller@ca410000 { > compatible = "renesas,r8a78000-mdlc"; > reg = <0 0xca410000 0 0x1000>; -- Regards, Laurent Pinchart