Re: [PATCH 7/8] media: iris: move common register definitions to the header

Dikshita Agarwal
2025-10-09T06:10:32Z

On 10/8/2025 10:03 AM, Dmitry Baryshkov wrote:
> Simplify adding new platforms by moving common registers definitions
> from VPU 3.x and "common" file to the header with other register
> defines.
>

Similar to
https://lore.kernel.org/all/20250925-knp_video-v1-5-e323c0b3c0cd@oss.qualcomm.com/
?

Thanks,
Dikshita
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 35 --------------
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 -----------------
> .../platform/qcom/iris/iris_vpu_register_defines.h | 56 ++++++++++++++++++++++
> 3 files changed, 56 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> index 339776a0b4672e246848c3a6a260eb83c7da6a60..78aede9ac497abafc0545647c34a53c63c595f72 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> @@ -11,48 +11,13 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> #define AON_MVP_NOC_RESET 0x0001F000
>
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> -#define CORE_CLK_RUN 0x0
> -/* VPU v3.5 */
> -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
> -
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> -#define CORE_BRIDGE_SW_RESET BIT(0)
> -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> -
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
>
> #define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
>
> -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> -
> #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
> #define SW_RESET BIT(0)
> #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index bb98950e018fadf69ac4f41b3037f7fd6ac33c5b..2d6548e47d47967c1c110489cb8088130fb625fd 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -11,13 +11,6 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -
> -#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
> -
> -#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
> -#define CLEAR_XTENSA2HOST_INTR BIT(0)
>
> #define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48)
> #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C)
> @@ -35,42 +28,6 @@
> #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64)
> #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68)
>
> -#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
> -#define HOST2XTENSA_INTR_ENABLE BIT(0)
> -
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> -#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
> -#define CPU_IC_SOFTINT_H2A_SHFT 0x0
> -
> -#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
> -#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
> -#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
> -
> -#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
> -#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
> -#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
> -
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -
> -#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> -
> static void iris_vpu_interrupt_init(struct iris_core *core)
> {
> u32 mask_val;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..9955367a9f8179d2e364c41dcfe8ad445a0a13f4 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> @@ -9,9 +9,65 @@
> #define VCODEC_BASE_OFFS 0x00000000
> #define CPU_BASE_OFFS 0x000A0000
> #define WRAPPER_BASE_OFFS 0x000B0000
> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> +#define AON_BASE_OFFS 0x000E0000
> +
> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
>
> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
>
> +#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
> +#define CLEAR_XTENSA2HOST_INTR BIT(0)
> +
> +#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
> +#define HOST2XTENSA_INTR_ENABLE BIT(0)
> +
> +#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
> +#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
> +#define CPU_IC_SOFTINT_H2A_SHFT 0x0
> +
> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> +#define CORE_BRIDGE_SW_RESET BIT(0)
> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> +
> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> +#define MSK_CORE_POWER_ON BIT(1)
> +
> +#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
> +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
> +#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
> +
> +#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
> +#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
> +#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
> +
> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> +#define REQ_POWER_DOWN_PREP BIT(0)
> +
> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> +
> +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
> +
> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> +#define CORE_CLK_RUN 0x0
> +
> +#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
> +
> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> +#define CTL_AXI_CLK_HALT BIT(0)
> +#define CTL_CLK_HALT BIT(1)
> +
> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> +#define RESET_HIGH BIT(0)
> +
> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
>
> #endif
>