[PATCH v3 8/9] dt-bindings: media: nxp,imx8mq-vpu: Update bindings

Benjamin Gaignard
2021-02-22T12:26:05Z

The current bindings seem to make the assumption that the
two VPUs hardware blocks (G1 and G2) are only one set of
registers.
After implementing the VPU reset driver and G2 decoder driver
it shows that all the VPUs are independent and don't need to
know about the registers of the other blocks.
Remove from the bindings the need to set all blocks register
but keep reg-names property because removing it from the driver
may affect other variants.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
---
version 2:
- be more verbose about why I change the bindings
Keep in mind that series comes after: https://www.spinics.net/lists/arm-kernel/msg875766.html
without that review and ack it won't work

.../bindings/media/nxp,imx8mq-vpu.yaml | 54 ++++++++++++-------
1 file changed, 36 insertions(+), 18 deletions(-)

diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
index 762be3f96ce9..468435c70eef 100644
--- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
+++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml
@@ -15,24 +15,25 @@ description:

properties:
compatible:
- const: nxp,imx8mq-vpu
+ enum:
+ - nxp,imx8mq-vpu
+ - nxp,imx8mq-vpu-g2

reg:
- maxItems: 3
+ maxItems: 1

reg-names:
- items:
- - const: g1
- - const: g2
- - const: ctrl
+ enum:
+ - g1
+ - g2

interrupts:
- maxItems: 2
+ maxItems: 1

interrupt-names:
- items:
- - const: g1
- - const: g2
+ enum:
+ - g1
+ - g2

clocks:
maxItems: 3
@@ -46,6 +47,9 @@ properties:
power-domains:
maxItems: 1

+ resets:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -54,6 +58,7 @@ required:
- interrupt-names
- clocks
- clock-names
+ - resets

additionalProperties: false

@@ -61,19 +66,32 @@ examples:
- |
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/imx8mq-vpu-reset.h>

- vpu: video-codec@38300000 {
+ vpu_g1: video-codec@38300000 {
compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
+ reg = <0x38300000 0x10000>;
+ reg-names = "g1";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
+ clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "g2", "bus";
+ power-domains = <&pgc_vpu>;
+ resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G1>;
+ };
+
+ vpu_g2: video-codec@38310000 {
+ compatible = "nxp,imx8mq-vpu-g2";
+ reg = <0x38310000 0x10000>;
+ reg-names = "g2";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>,
<&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
clock-names = "g1", "g2", "bus";
power-domains = <&pgc_vpu>;
+ resets = <&vpu_reset IMX8MQ_RESET_VPU_RESET_G2>;
};
--
2.25.1