From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: "Niklas Söderlund" <niklas.soderlund@ragnatech.se>
Cc: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>,
Sakari Ailus <sakari.ailus@iki.fi>,
linux-renesas-soc@vger.kernel.org, linux-media@vger.kernel.org,
Jacopo Mondi <jacopo@jmondi.org>,
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
Jacopo Mondi <jacopo+renesas@jmondi.org>
Subject: Re: [PATCH v3 1/4] dt-bindings: media: i2c: Add bindings for Maxim Integrated MAX9286
Date: Tue, 16 Oct 2018 03:37:44 +0300 [thread overview]
Message-ID: <2443594.YVDbUcPb3K@avalon> (raw)
In-Reply-To: <20181015190121.GI24305@bigcity.dyn.berto.se>
Hello,
On Monday, 15 October 2018 22:01:21 EEST Niklas Söderlund wrote:
> On 2018-10-15 18:37:40 +0100, Kieran Bingham wrote:
> >>> diff --git
> >>> a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.txt
> >>> b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.txt
> >>> new file mode 100644
> >>> index 000000000000..a73e3c0dc31b
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.txt
> >>> @@ -0,0 +1,182 @@
> >>> +Maxim Integrated Quad GMSL Deserializer
> >>> +---------------------------------------
> >>> +
> >>> +The MAX9286 deserializer receives video data on up to 4 Gigabit
> >>> Multimedia
> >>> +Serial Links (GMSL) and outputs them on a CSI-2 port using up to 4
> >>> data lanes.
> >>
> >> CSI-2 D-PHY I presume?
> >
> > Yes, that's how I've adapted the driver based on the latest bus changes.
> >
> > Niklas - Could you confirm that everything in VIN/CSI2 is configured to
> > use D-PHY and not C-PHY at all ?
>
> Yes it's only D-PHY.
>
> >>> +
> >>> +- remote-endpoint: phandle to the remote GMSL source endpoint subnode
> >>> in the
> >>> + remote node port.
> >>> +
> >>> +Required Endpoint Properties for CSI-2 Output Port (Port 4):
> >>> +
> >>> +- data-lanes: array of physical CSI-2 data lane indexes.
> >>> +- clock-lanes: index of CSI-2 clock lane.
> >>
> >> Is any number of lanes supported? How about lane remapping? If you do
> >> not have lane remapping, the clock-lanes property is redundant.
> >
> > Uhm ... Niklas?
>
> The MAX9286 documentation contains information on lane remapping and
> support for any number (1-4) of enabled data-lanes. I have not tested if
> this works in practice but the registers are there and documented :-)
That's my understanding too. Clock lane remapping doesn't seem to be supported
though. We could thus omit the clock-lanes property.
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2018-10-16 8:25 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-09 20:57 [PATCH v3 0/4] MAX9286 GMSL Support Kieran Bingham
2018-10-09 20:57 ` [PATCH v3 1/4] dt-bindings: media: i2c: Add bindings for Maxim Integrated MAX9286 Kieran Bingham
2018-10-15 16:45 ` Sakari Ailus
2018-10-15 17:37 ` Kieran Bingham
2018-10-15 19:01 ` Niklas Söderlund
2018-10-16 0:37 ` Laurent Pinchart [this message]
2018-11-02 13:00 ` Kieran Bingham
2018-10-15 19:37 ` jacopo mondi
2018-11-02 13:29 ` Kieran Bingham
2018-11-02 13:56 ` jacopo mondi
2018-11-02 22:40 ` Sakari Ailus
2018-10-09 20:57 ` [PATCH v3 2/4] dt-bindings: media: i2c: Add bindings for IMI RDACM20 Kieran Bingham
2018-10-09 20:57 ` [PATCH v3 3/4] media: i2c: Add MAX9286 driver Kieran Bingham
2018-10-09 20:57 ` [PATCH v3 4/4] media: i2c: Add RDACM20 driver Kieran Bingham
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