public inbox for linux-media@vger.kernel.org
 help / color / mirror / Atom feed
From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Hans Verkuil <hverkuil@xs4all.nl>
Cc: linux-media@vger.kernel.org,
	Hans Verkuil <hans.verkuil@cisco.com>,
	Lars-Peter Clausen <lars@metafoo.de>
Subject: Re: [PATCH v3 36/48] adv7604: Make output format configurable through pad format operations
Date: Tue, 18 Mar 2014 14:02:43 +0100	[thread overview]
Message-ID: <2557122.W7Piv8LSLZ@avalon> (raw)
In-Reply-To: <532812B0.6000109@xs4all.nl>

Hi Hans,

On Tuesday 18 March 2014 10:32:32 Hans Verkuil wrote:
> Hi Laurent,
> 
> I've tested it and I thought I was going crazy. Everything was fine after
> applying this patch, but as soon as I applied the next patch (37/48) the
> colors were wrong. But that patch had nothing whatsoever to do with the
> bus ordering. You managed to make a small but crucial bug and it was pure
> bad luck that it ever worked.
> 
> See details below:
> 
> On 03/11/14 16:10, Laurent Pinchart wrote:
> > Replace the dummy video format operations by pad format operations that
> > configure the output format.
> > 
> > Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> > 
> >  drivers/media/i2c/adv7604.c | 280 +++++++++++++++++++++++++++++++++++----
> >  include/media/adv7604.h     |  56 ++++-----
> >  2 files changed, 275 insertions(+), 61 deletions(-)
> > 
> > diff --git a/drivers/media/i2c/adv7604.c b/drivers/media/i2c/adv7604.c
> > index 851b350..5aa7c29 100644
> > --- a/drivers/media/i2c/adv7604.c
> > +++ b/drivers/media/i2c/adv7604.c
> > @@ -53,6 +53,28 @@ MODULE_LICENSE("GPL");
> > 
> >  /* ADV7604 system clock frequency */
> >  #define ADV7604_fsc (28636360)
> > 
> > +#define ADV7604_RGB_OUT					(1 << 1)
> > +
> > +#define ADV7604_OP_FORMAT_SEL_8BIT			(0 << 0)
> > +#define ADV7604_OP_FORMAT_SEL_10BIT			(1 << 0)
> > +#define ADV7604_OP_FORMAT_SEL_12BIT			(2 << 0)
> > +
> > +#define ADV7604_OP_MODE_SEL_SDR_422			(0 << 5)
> > +#define ADV7604_OP_MODE_SEL_DDR_422			(1 << 5)
> > +#define ADV7604_OP_MODE_SEL_SDR_444			(2 << 5)
> > +#define ADV7604_OP_MODE_SEL_DDR_444			(3 << 5)
> > +#define ADV7604_OP_MODE_SEL_SDR_422_2X			(4 << 5)
> > +#define ADV7604_OP_MODE_SEL_ADI_CM			(5 << 5)
> > +
> > +#define ADV7604_OP_CH_SEL_GBR				(0 << 5)
> > +#define ADV7604_OP_CH_SEL_GRB				(1 << 5)
> > +#define ADV7604_OP_CH_SEL_BGR				(2 << 5)
> > +#define ADV7604_OP_CH_SEL_RGB				(3 << 5)
> > +#define ADV7604_OP_CH_SEL_BRG				(4 << 5)
> > +#define ADV7604_OP_CH_SEL_RBG				(5 << 5)
> 
> Note that these values are shifted 5 bits to the left...

[snip]

> > +struct adv7604_format_info {
> > +	enum v4l2_mbus_pixelcode code;
> > +	u8 op_ch_sel;
> > +	bool rgb_out;
> > +	bool swap_cb_cr;
> > +	u8 op_format_sel;
> > +};

[snip]

> > +static const struct adv7604_format_info adv7604_formats[] = {
> > +	{ V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
> > +	{ V4L2_MBUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
> > +	{ V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
> > +	{ V4L2_MBUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
> > +	{ V4L2_MBUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
> > +	{ V4L2_MBUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
> > +	{ V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
> > +};
> > +
> > +static const struct adv7604_format_info adv7611_formats[] = {
> > +	{ V4L2_MBUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
> > +	{ V4L2_MBUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
> > +	{ V4L2_MBUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
> > +	  ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
> > +};

[snip]

> > +/*
> > + * Compute the op_ch_sel value required to obtain on the bus the
> > component order
> > + * corresponding to the selected format taking into account bus
> > reordering
> > + * applied by the board at the output of the device.
> > + *
> > + * The following table gives the op_ch_value from the format component
> > order
> > + * (expressed as op_ch_sel value in column) and the bus reordering
> > (expressed as
> > + * adv7604_bus_order value in row).
> > + *
> > + *           |	GBR(0)	GRB(1)	BGR(2)	RGB(3)	BRG(4)	RBG(5)
> > + * ----------+-------------------------------------------------
> > + * RGB (NOP) |	GBR	GRB	BGR	RGB	BRG	RBG
> > + * GRB (1-2) |	BGR	RGB	GBR	GRB	RBG	BRG
> > + * RBG (2-3) |	GRB	GBR	BRG	RBG	BGR	RGB
> > + * BGR (1-3) |	RBG	BRG	RGB	BGR	GRB	GBR
> > + * BRG (ROR) |	BRG	RBG	GRB	GBR	RGB	BGR
> > + * GBR (ROL) |	RGB	BGR	RBG	BRG	GBR	GRB
> > + */
> > +static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
> > +{
> > +#define _SEL(a,b,c,d,e,f)	{ \
> > +	ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, 
\
> > +	ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f }
> > +#define _BUS(x)			[ADV7604_BUS_ORDER_##x]
> > +
> > +	static const unsigned int op_ch_sel[6][6] = {
> > +		_BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
> > +		_BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
> > +		_BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
> > +		_BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
> > +		_BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
> > +		_BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
> > +	};
> > +
> > +	return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel];
> 
> But you don't shift state->format->op_ch_sel back 5 bits to the right, so
> you end up with a random memory value. It should be:
> 
> 	return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
> 
> After correcting this everything worked fine for me.

Good catch ! Thank you. I've fixed that and submitted v4.

In addition to this patch, I'm only missing your Acked-by or Reviewed-by tag 
for patch 47/48 ("adv7604: Add LLC polarity configuration"). Could you please 
provide that ? I'll then send a pull request to Mauro for the whole series.

-- 
Regards,

Laurent Pinchart


  reply	other threads:[~2014-03-18 13:00 UTC|newest]

Thread overview: 92+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-10 23:15 [PATCH v2 00/48] ADV7611 support Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 01/48] v4l: of: Support empty port nodes Laurent Pinchart
2014-03-11 12:05   ` Sylwester Nawrocki
2014-03-10 23:15 ` [PATCH v2 02/48] v4l: Add UYVY10_2X10 and VYUY10_2X10 media bus pixel codes Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 03/48] v4l: Add UYVY10_1X20 and VYUY10_1X20 " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 04/48] v4l: Add 12-bit YUV 4:2:0 " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 05/48] v4l: Add 12-bit YUV 4:2:2 " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 06/48] v4l: Add pad-level DV timings subdev operations Laurent Pinchart
2014-03-11  7:24   ` Prabhakar Lad
2014-03-11 10:27   ` Hans Verkuil
2014-03-10 23:15 ` [PATCH v2 07/48] ad9389b: Add pad-level DV timings operations Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 08/48] adv7511: " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 09/48] adv7842: " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 10/48] s5p-tv: hdmi: " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 11/48] s5p-tv: hdmiphy: " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 12/48] ths8200: " Laurent Pinchart
2014-03-11  7:11   ` Prabhakar Lad
2014-03-10 23:15 ` [PATCH v2 13/48] tvp7002: " Laurent Pinchart
2014-03-11  7:12   ` Prabhakar Lad
2014-03-10 23:15 ` [PATCH v2 14/48] media: bfin_capture: Switch to pad-level DV operations Laurent Pinchart
2014-03-13  8:59   ` Scott Jiang
2014-03-10 23:15 ` [PATCH v2 15/48] media: davinci: vpif: " Laurent Pinchart
2014-03-11  7:15   ` Prabhakar Lad
2014-03-10 23:15 ` [PATCH v2 16/48] media: staging: davinci: vpfe: " Laurent Pinchart
2014-03-11  7:16   ` Prabhakar Lad
2014-03-10 23:15 ` [PATCH v2 17/48] s5p-tv: mixer: " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 18/48] ad9389b: Remove deprecated video-level DV timings operations Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 19/48] adv7511: " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 20/48] adv7842: " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 21/48] s5p-tv: hdmi: " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 22/48] s5p-tv: hdmiphy: Remove deprecated video-level DV timings operation Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 23/48] ths8200: Remove deprecated video-level DV timings operations Laurent Pinchart
2014-03-11  7:13   ` Prabhakar Lad
2014-03-10 23:15 ` [PATCH v2 24/48] tvp7002: " Laurent Pinchart
2014-03-11  7:12   ` Prabhakar Lad
2014-03-10 23:15 ` [PATCH v2 25/48] v4l: Improve readability by not wrapping ioctl number #define's Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 26/48] v4l: Add support for DV timings ioctls on subdev nodes Laurent Pinchart
2014-03-11 10:38   ` Hans Verkuil
2014-03-11 11:02     ` Laurent Pinchart
2014-03-11 15:09   ` [PATCH v3 " Laurent Pinchart
2014-03-11 15:33     ` Hans Verkuil
2014-03-10 23:15 ` [PATCH v2 27/48] v4l: Validate fields in the core code for subdev EDID ioctls Laurent Pinchart
2014-03-11  8:57   ` Sakari Ailus
2014-03-11 10:45   ` Hans Verkuil
2014-03-11 10:57     ` Laurent Pinchart
2014-03-11 10:59       ` Hans Verkuil
2014-03-11 15:09   ` [PATCH v3 " Laurent Pinchart
2014-03-11 15:44     ` Hans Verkuil
2014-03-11 16:08       ` Laurent Pinchart
2014-03-11 16:11         ` Hans Verkuil
2014-03-11 16:24           ` Laurent Pinchart
2014-03-11 16:44             ` Hans Verkuil
2014-03-10 23:15 ` [PATCH v2 28/48] adv7604: Add missing include to linux/types.h Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 29/48] adv7604: Add support for asynchronous probing Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 30/48] adv7604: Don't put info string arrays on the stack Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 31/48] adv7604: Add 16-bit read functions for CP and HDMI Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 32/48] adv7604: Cache register contents when reading multiple bits Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 33/48] adv7604: Add adv7611 support Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 34/48] adv7604: Remove subdev control handlers Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 35/48] adv7604: Add sink pads Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 36/48] adv7604: Make output format configurable through pad format operations Laurent Pinchart
2014-03-11 15:10   ` [PATCH v3 " Laurent Pinchart
2014-03-13 21:45     ` Hans Verkuil
2014-03-18  9:32     ` Hans Verkuil
2014-03-18 13:02       ` Laurent Pinchart [this message]
2014-03-18 13:09         ` Hans Verkuil
2014-03-10 23:15 ` [PATCH v2 37/48] adv7604: Add pad-level DV timings support Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 38/48] adv7604: Remove deprecated video-level DV timings operations Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 39/48] v4l: subdev: " Laurent Pinchart
2014-03-11  7:21   ` Prabhakar Lad
2014-03-10 23:15 ` [PATCH v2 40/48] adv7604: Inline the to_sd function Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 41/48] adv7604: Store I2C addresses and clients in arrays Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 42/48] adv7604: Replace *_and_or() functions with *_clr_set() Laurent Pinchart
2014-03-11 15:10   ` [PATCH v3 " Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 43/48] adv7604: Sort headers alphabetically Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 44/48] adv7604: Support hot-plug detect control through a GPIO Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 45/48] adv7604: Specify the default input through platform data Laurent Pinchart
2014-03-10 23:15 ` [PATCH v2 46/48] adv7604: Add DT support Laurent Pinchart
2014-03-11 15:11   ` [PATCH v3 " Laurent Pinchart
2014-04-17 10:59   ` [PATCH v2 " Sylwester Nawrocki
2014-04-17 12:36     ` Laurent Pinchart
2014-04-17 13:08       ` Laurent Pinchart
2014-04-17 13:41         ` Sylwester Nawrocki
2014-03-10 23:15 ` [PATCH v2 47/48] adv7604: Add LLC polarity configuration Laurent Pinchart
2014-03-18 13:05   ` Hans Verkuil
2014-04-17 11:29   ` Sylwester Nawrocki
2014-03-10 23:15 ` [PATCH v2 48/48] adv7604: Add endpoint properties to DT bindings Laurent Pinchart
2014-04-17 11:17   ` Sylwester Nawrocki
2014-04-17 12:45     ` Laurent Pinchart
2014-04-17 13:00       ` Ben Dooks
2014-04-17 13:04         ` Laurent Pinchart
2014-03-11 11:58 ` [PATCH v2 00/48] ADV7611 support Hans Verkuil

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=2557122.W7Piv8LSLZ@avalon \
    --to=laurent.pinchart@ideasonboard.com \
    --cc=hans.verkuil@cisco.com \
    --cc=hverkuil@xs4all.nl \
    --cc=lars@metafoo.de \
    --cc=linux-media@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox