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Tue, 22 Sep 2026 22:41:48 -0700 (PDT) X-Received: by 2002:a05:7300:b291:b0:33b:e21e:4a3a with SMTP id 5a478bee46e88-33e8e69cb4bmr1709602eec.40.1790142108165; Tue, 22 Sep 2026 22:41:48 -0700 (PDT) Received: from [10.206.101.140] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e96258351sm3193280eec.12.2026.09.22.22.41.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 22 Sep 2026 22:41:47 -0700 (PDT) Message-ID: <335528fa-72b1-b61c-a2f2-aa1e15c8f3ec@oss.qualcomm.com> Date: Wed, 23 Sep 2026 11:11:39 +0530 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v11 1/9] dt-bindings: media: qcom,glymur-iris: Add glymur video codec To: Dmitry Baryshkov Cc: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Krzysztof Kozlowski , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260917-glymur-v11-0-e0c8bc914742@oss.qualcomm.com> <20260917-glymur-v11-1-e0c8bc914742@oss.qualcomm.com> Content-Language: en-US From: Vishnu Reddy In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=EZdd0/mC c=1 sm=1 tr=0 ts=6ab366a2 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=6X4DAO4X2HBH6bcfxsAA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-ORIG-GUID: rpDhuql528nYy0o03ip-7rQ8uWJA3tvm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIzMDAyMiBTYWx0ZWRfX6bbj1oSJ764j zdDzUgr+13d3cwVHyIb/VQJ8tZS2g7Op9sbSEUo4WGBFtffjuoz/pxhwultZLYFGK5QYK4SN4jX h3mSCWXFfNP/EfVLtO8wkxOwKKUzchMdaLb8PREGmzMk0pjryESZvp/fv3GtOe97nwtZzEmWFZe 3FCGd8tBU5/ylzUxAFAlk71fGf6ropCKB7ogFHeXlF62UwmGPSuVKrTavRn7AFIJsYltIZD0nuP 7k0UEBeQ25XEoymexANsD9SPe3PNKdku8rCpdBff0SuhNThCBJibwibtexACEiD5Fy/pKc3ykKI CnXeszi73R1bygbtPccJ+HHbqioZ0DDtLYMlDSuXeGTNwOIjVUhcX0HC+aOzD7WArJ3MnGCYfZy tFQ52FEuzZYClXDy3ZMylIPeau5+Vc0TGrFx2fB1rripg+fFmoEWp2lpV587IETmYd+C8vJhr8T inqTwTt7N+Qk7xflTgA== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIzMDAyMiBTYWx0ZWRfXyJvHBRwetGsU uWINcCa26RP4y1eUgjHFuGCm7Zk2zSOzz8CI25yHW4jrOlhHDzlP8+ZBiW+y7oK1j/nyTYKIpO2 1ecOMOGzP0oCLmJkAVcXnIWlmhiVK7s= X-Proofpoint-GUID: rpDhuql528nYy0o03ip-7rQ8uWJA3tvm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-23_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609230022 On 9/22/2026 6:29 PM, Dmitry Baryshkov wrote: > On Thu, Sep 17, 2026 at 10:30:20AM +0530, Vishnu Reddy wrote: >> Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur >> is a new generation of video IP that introduces a dual-core architecture. >> The second core brings its own power domain, clocks, and reset lines, >> requiring additional power domains and clocks in the power sequence. The >> current maxItems constraints for clocks, power-domains and non-pixel >> iommus in the common venus schema were sized for platforms available at >> the time of authoring. The glymur platform introduces a dual core >> architecture that requires more clocks and power domains, exceeding these >> limits. Raise maxItems for clocks, clock-names, power-domains, >> power-domain-names and non-pixel iommus to accommodate glymur platform. >> The glymur platform specific schema have fixed constraints for these >> properties, so the common schema only acts as an upper bound. Since the >> common schema now only acts as an upper bound, add explicit maxItems >> overrides for the non-pixel iommus in the qcom,sm8550-iris and >> qcom,sm8750-iris schemas to keep the fixed constraints as before. >> >> Signed-off-by: Vishnu Reddy >> --- >> .../bindings/media/qcom,glymur-iris.yaml | 218 +++++++++++++++++++++ >> .../bindings/media/qcom,sm8550-iris.yaml | 6 + >> .../bindings/media/qcom,sm8750-iris.yaml | 6 + >> .../bindings/media/qcom,venus-common.yaml | 11 +- >> 4 files changed, 236 insertions(+), 5 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml >> new file mode 100644 >> index 000000000000..de4792f3b658 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml >> @@ -0,0 +1,218 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Glymur SoC Iris video encoder and decoder >> + >> +maintainers: >> + - Vishnu Reddy >> + >> +description: >> + The Iris video processing unit on Qualcomm Glymur SoC is a video encode and >> + decode accelerator. >> + >> +properties: >> + compatible: >> + const: qcom,glymur-iris >> + >> + clocks: >> + maxItems: 9 >> + >> + clock-names: >> + items: >> + - const: core_iface >> + - const: core >> + - const: vcodec0_core >> + - const: vcodec0_iface >> + - const: core_freerun >> + - const: vcodec0_core_freerun >> + - const: vcodec1_iface >> + - const: vcodec1_core > Nit: is there any logic in the order of the clocks? Why vcodec0_core > comes before vcodec0_iface, but vcodec1_core comes after vcodec1_iface? I followed the clock ordering from the SM8750 binding for the existing entries. For the additional glymur clocks, I appended them at the end and kept the new pair in the same interface-before-core style as the inherited clock list. That is why vcodec1_iface appears before vcodec1_core. There was no specific functional dependency intended by this ordering. Let me know if you have any preference on reordering. >> + - const: vcodec1_core_freerun >> + >> + dma-coherent: true >> + >> + interconnects: >> + maxItems: 2 >