From: Bingbu Cao <bingbu.cao@linux.intel.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Andreas Helbech Kleist <andreaskleist@gmail.com>
Cc: bingbu.cao@intel.com, linux-media@vger.kernel.org,
sakari.ailus@linux.intel.com, andriy.shevchenko@linux.intel.com,
hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com,
claus.stovgaard@gmail.com, tfiga@chromium.org,
senozhatsky@chromium.org, tomi.valkeinen@ideasonboard.com,
tian.shu.qiu@intel.com, hongju.wang@intel.com
Subject: Re: [PATCH v2 03/15] media: intel/ipu6: add IPU6 buttress interface driver
Date: Wed, 3 Jan 2024 21:33:26 +0800 [thread overview]
Message-ID: <42447c5f-88bf-3d3d-b805-dfb90d4da1ac@linux.intel.com> (raw)
In-Reply-To: <20240103104935.GA13622@pendragon.ideasonboard.com>
Laurent,
On 1/3/24 6:49 PM, Laurent Pinchart wrote:
> On Wed, Jan 03, 2024 at 10:22:20AM +0100, Andreas Helbech Kleist wrote:
>> Hi Bingbu,
>>
>> On Tue, 2023-10-24 at 19:29 +0800, bingbu.cao@intel.com wrote:
>>> From: Bingbu Cao <bingbu.cao@intel.com>
>>>
>>> The IPU6 buttress is the interface between IPU device (input system
>>> and processing system) with rest of the SoC. It contains overall IPU
>>> hardware control registers, these control registers are used as the
>>> interfaces with the Intel Converged Security Engine and Punit to do
>>> firmware authentication and power management.
>>>
>>> Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
>>> ---
>>
>> ...
>>
>>> +static irqreturn_t ipu6_buttress_call_isr(struct ipu6_bus_device *adev)
>>> +{
>>> + irqreturn_t ret = IRQ_WAKE_THREAD;
>>> +
>>> + if (!adev || !adev->auxdrv || !adev->auxdrv_data)
>>> + return IRQ_NONE;
>>> +
>>> + if (adev->auxdrv_data->isr)
>>> + ret = adev->auxdrv_data->isr(adev);
>>> +
>>> + if (ret == IRQ_WAKE_THREAD && !adev->auxdrv_data->isr_threaded)
>>> + ret = IRQ_NONE;
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +irqreturn_t ipu6_buttress_isr(int irq, void *isp_ptr)
>>> +{
>>> + struct ipu6_device *isp = isp_ptr;
>>> + struct ipu6_bus_device *adev[] = { isp->isys, isp->psys };
>>> + struct ipu6_buttress *b = &isp->buttress;
>>> + u32 reg_irq_sts = BUTTRESS_REG_ISR_STATUS;
>>> + irqreturn_t ret = IRQ_NONE;
>>> + u32 disable_irqs = 0;
>>> + u32 irq_status;
>>> + u32 i, count = 0;
>>> +
>>> + pm_runtime_get_noresume(&isp->pdev->dev);
>>> +
>>> + irq_status = readl(isp->base + reg_irq_sts);
>
> A drive-by comment: this seems dodgy. If someone calls pm_runtime_put*()
> just before the pm_runtime_get_noresume() above, the device won't be
> resumed when reading the register, which will likely not lead to the
> desired result.
Thanks for your review.
What do you think using pm_runtime_get_if_in_use() here?
>
>>> + if (!irq_status) {
>>> + pm_runtime_put_noidle(&isp->pdev->dev);
>>> + return IRQ_NONE;
>>> + }
>>> +
>>> + do {
>>> + writel(irq_status, isp->base + BUTTRESS_REG_ISR_CLEAR);
>>> +
>>> + for (i = 0; i < ARRAY_SIZE(ipu6_adev_irq_mask); i++) {
>>> + irqreturn_t r = ipu6_buttress_call_isr(adev[i]);
>>> +
>>> + if (!(irq_status & ipu6_adev_irq_mask[i]))
>>> + continue;
>>> +
>>> + if (r == IRQ_WAKE_THREAD) {
>>> + ret = IRQ_WAKE_THREAD;
>>> + disable_irqs |= ipu6_adev_irq_mask[i];
>>> + } else if (ret == IRQ_NONE && r == IRQ_HANDLED) {
>>> + ret = IRQ_HANDLED;
>>> + }
>>> + }
>>
>> It seems wrong to call the ISR for a adev[i] before checking the
>> corresponding IRQ mask. If the mask is not set, the ISR is still
>> called, but the result is thrown away.
>>
>> I started investigating this because I'm seeing "general protection
>> fault, probably for non-canonical address 0x6b6b6b6b6b6b6b6b" in this
>> function when unbinding the IPU4 driver.
>>
>> How do you ensure that the ISR is not called on a ipu6-bus device that
>> has been deleted? Specifically in ipu6_pci_remove, ipu6_bus_del_devices
>> is called before ipu6_buttress_exit (which disables buttress IRQs).
>> Perhaps the above for loop should really be a "for each ipu6-bus
>> device" loop?
>>
>>> +
>>> + if ((irq_status & BUTTRESS_EVENT) && ret == IRQ_NONE)
>>> + ret = IRQ_HANDLED;
>>> +
>>> + if (irq_status & BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING) {
>>> + dev_dbg(&isp->pdev->dev,
>>> + "BUTTRESS_ISR_IPC_FROM_CSE_IS_WAITING\n");
>>> + ipu6_buttress_ipc_recv(isp, &b->cse, &b->cse.recv_data);
>>> + complete(&b->cse.recv_complete);
>>> + }
>>> +
>>> + if (irq_status & BUTTRESS_ISR_IPC_FROM_ISH_IS_WAITING) {
>>> + dev_dbg(&isp->pdev->dev,
>>> + "BUTTRESS_ISR_IPC_FROM_ISH_IS_WAITING\n");
>>> + ipu6_buttress_ipc_recv(isp, &b->ish, &b->ish.recv_data);
>>> + complete(&b->ish.recv_complete);
>>> + }
>>> +
>>> + if (irq_status & BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE) {
>>> + dev_dbg(&isp->pdev->dev,
>>> + "BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE\n");
>>> + complete(&b->cse.send_complete);
>>> + }
>>> +
>>> + if (irq_status & BUTTRESS_ISR_IPC_EXEC_DONE_BY_ISH) {
>>> + dev_dbg(&isp->pdev->dev,
>>> + "BUTTRESS_ISR_IPC_EXEC_DONE_BY_CSE\n");
>>> + complete(&b->ish.send_complete);
>>> + }
>>> +
>>> + if (irq_status & BUTTRESS_ISR_SAI_VIOLATION &&
>>> + ipu6_buttress_get_secure_mode(isp))
>>> + dev_err(&isp->pdev->dev,
>>> + "BUTTRESS_ISR_SAI_VIOLATION\n");
>>> +
>>> + if (irq_status & (BUTTRESS_ISR_IS_FATAL_MEM_ERR |
>>> + BUTTRESS_ISR_PS_FATAL_MEM_ERR))
>>> + dev_err(&isp->pdev->dev,
>>> + "BUTTRESS_ISR_FATAL_MEM_ERR\n");
>>> +
>>> + if (irq_status & BUTTRESS_ISR_UFI_ERROR)
>>> + dev_err(&isp->pdev->dev, "BUTTRESS_ISR_UFI_ERROR\n");
>>> +
>>> + if (++count == BUTTRESS_MAX_CONSECUTIVE_IRQS) {
>>> + dev_err(&isp->pdev->dev, "too many consecutive IRQs\n");
>>> + ret = IRQ_NONE;
>>> + break;
>>> + }
>>> +
>>> + irq_status = readl(isp->base + reg_irq_sts);
>>> + } while (irq_status);
>>> +
>>> + if (disable_irqs)
>>> + writel(BUTTRESS_IRQS & ~disable_irqs,
>>> + isp->base + BUTTRESS_REG_ISR_ENABLE);
>>> +
>>> + pm_runtime_put(&isp->pdev->dev);
>>> +
>>> + return ret;
>>> +}
>>
>> ...
>>
>> /Andreas
>
--
Best regards,
Bingbu Cao
next prev parent reply other threads:[~2024-01-03 13:37 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-24 11:29 [PATCH v2 00/15] Intel IPU6 and IPU6 input system drivers bingbu.cao
2023-10-24 11:29 ` [PATCH v2 01/15] media: intel/ipu6: add Intel IPU6 PCI device driver bingbu.cao
2023-10-25 12:39 ` Andreas Helbech Kleist
2023-10-25 20:03 ` Andy Shevchenko
2023-11-05 14:43 ` Hans de Goede
2023-11-06 8:55 ` Bingbu Cao
2023-11-08 11:25 ` Hans de Goede
2023-11-08 13:24 ` Andy Shevchenko
2023-11-08 14:10 ` Andreas Helbech Kleist
2023-11-08 14:18 ` Cao, Bingbu
2023-11-17 18:43 ` Hans de Goede
2023-11-17 21:18 ` Andy Shevchenko
2023-11-20 3:54 ` Bingbu Cao
2023-11-23 9:17 ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 02/15] media: intel/ipu6: add IPU auxiliary devices bingbu.cao
2023-10-24 12:58 ` Andy Shevchenko
2023-10-25 7:14 ` Bingbu Cao
2023-10-25 8:35 ` Hans de Goede
2023-10-25 19:57 ` Andy Shevchenko
2023-10-26 3:04 ` Bingbu Cao
2023-10-24 11:29 ` [PATCH v2 03/15] media: intel/ipu6: add IPU6 buttress interface driver bingbu.cao
2024-01-03 9:22 ` Andreas Helbech Kleist
2024-01-03 10:49 ` Laurent Pinchart
2024-01-03 13:33 ` Bingbu Cao [this message]
2024-01-03 14:01 ` Laurent Pinchart
2024-01-03 13:11 ` Bingbu Cao
2024-01-03 13:18 ` Bingbu Cao
2024-01-08 10:27 ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 04/15] media: intel/ipu6: CPD parsing for get firmware components bingbu.cao
2023-10-24 11:29 ` [PATCH v2 05/15] media: intel/ipu6: add IPU6 DMA mapping API and MMU table bingbu.cao
2023-12-06 14:53 ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 06/15] media: intel/ipu6: add syscom interfaces between firmware and driver bingbu.cao
2023-11-23 9:33 ` Andreas Helbech Kleist
2023-12-28 6:39 ` Bingbu Cao
2024-01-03 9:25 ` Andreas Helbech Kleist
2024-01-08 4:19 ` Bingbu Cao
2023-10-24 11:29 ` [PATCH v2 07/15] media: intel/ipu6: input system ABI " bingbu.cao
2023-10-24 11:29 ` [PATCH v2 08/15] media: intel/ipu6: add IPU6 CSI2 receiver v4l2 sub-device bingbu.cao
2023-11-08 11:25 ` Andreas Helbech Kleist
2023-11-08 14:50 ` Cao, Bingbu
2023-11-08 14:51 ` Bingbu Cao
2023-11-08 15:00 ` Andreas Helbech Kleist
2023-11-08 15:32 ` andriy.shevchenko
2023-11-09 1:48 ` Bingbu Cao
2023-10-24 11:29 ` [PATCH v2 09/15] media: intel/ipu6: add the CSI2 DPHY implementation bingbu.cao
2023-10-24 11:29 ` [PATCH v2 10/15] media: intel/ipu6: add input system driver bingbu.cao
2023-11-23 9:37 ` Andreas Helbech Kleist
2024-01-09 13:52 ` Andreas Helbech Kleist
2024-01-10 12:47 ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 11/15] media: intel/ipu6: input system video capture nodes bingbu.cao
2023-11-05 16:59 ` Hans de Goede
2023-11-06 9:18 ` Bingbu Cao
2023-11-06 11:17 ` Andy Shevchenko
2023-12-05 9:15 ` Bingbu Cao
2024-01-09 13:35 ` Andreas Helbech Kleist
2023-10-24 11:29 ` [PATCH v2 12/15] media: add Kconfig and Makefile for IPU6 bingbu.cao
2023-10-24 13:04 ` Andy Shevchenko
2023-10-25 8:43 ` Bingbu Cao
2023-10-25 20:00 ` Andy Shevchenko
2023-10-25 12:21 ` Sakari Ailus
2023-10-25 20:01 ` Andy Shevchenko
2023-10-24 11:29 ` [PATCH v2 13/15] MAINTAINERS: add maintainers for Intel IPU6 input system driver bingbu.cao
2023-10-24 11:29 ` [PATCH v2 14/15] Documentation: add Intel IPU6 ISYS driver admin-guide doc bingbu.cao
2023-10-25 12:15 ` Sakari Ailus
2024-01-08 3:51 ` Bingbu Cao
2024-01-08 9:14 ` Sakari Ailus
2024-01-09 6:34 ` Bingbu Cao
2024-01-09 8:55 ` Sakari Ailus
2024-01-09 11:00 ` Bingbu Cao
2023-10-24 11:29 ` [PATCH v2 15/15] Documentation: add documentation of Intel IPU6 driver and hardware overview bingbu.cao
2023-10-25 12:09 ` Sakari Ailus
2023-10-26 3:38 ` Bingbu Cao
2023-10-26 5:27 ` Sakari Ailus
2023-11-08 11:59 ` [PATCH v2 00/15] Intel IPU6 and IPU6 input system drivers Hans de Goede
2023-11-08 14:31 ` Cao, Bingbu
2023-11-08 15:15 ` Hans de Goede
2023-11-10 12:04 ` Hans de Goede
2023-11-13 10:37 ` Bingbu Cao
2023-12-04 16:35 ` Hans de Goede
2023-12-04 16:49 ` Andy Shevchenko
2024-01-08 4:07 ` Bingbu Cao
2024-01-08 14:23 ` Hans de Goede
2024-01-09 3:51 ` Bingbu Cao
2024-01-15 13:13 ` Hans de Goede
2024-02-07 7:00 ` Sakari Ailus
2024-02-14 9:28 ` Sakari Ailus
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