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Sun, 20 Sep 2026 22:41:03 -0700 (PDT) X-Received: by 2002:a17:90b:17cb:b0:38e:57a3:f218 with SMTP id 98e67ed59e1d1-39e54d13343mr16318581a91.13.1789969262785; Sun, 20 Sep 2026 22:41:02 -0700 (PDT) Received: from [10.206.101.140] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144e14dd04dsm6579012c88.7.2026.09.20.22.40.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 20 Sep 2026 22:41:02 -0700 (PDT) Message-ID: <43e757dd-17f7-5b03-33e4-5c567e164be2@oss.qualcomm.com> Date: Mon, 21 Sep 2026 11:10:54 +0530 Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH 2/4] arm64: dts: qcom: nord: Add iris video node Content-Language: en-US To: Shawn Guo Cc: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , Abel Vesa , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260919-nord-iris-v1-0-94428761ec06@oss.qualcomm.com> <20260919-nord-iris-v1-2-94428761ec06@oss.qualcomm.com> From: Vishnu Reddy In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=PaRqFShd c=1 sm=1 tr=0 ts=6ab0c370 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=vTOospmqq8J8sbT3TakA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIxMDA3OSBTYWx0ZWRfX5TDPK9CuJ2KU bmqqrCTc4fdy2mJMuUFEkOK0IEZAkR8egFjvlFuTLVZxXyn3p1J+g6/MG31yDrHTcxNJNi5gUDf w/F+6ERYrB1ziZb/P7DDdEKUuSzWCAA= X-Proofpoint-GUID: ElkcELdrOkk0ERCq1_eq0V6toySxv7ww X-Proofpoint-ORIG-GUID: ElkcELdrOkk0ERCq1_eq0V6toySxv7ww X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIxMDA3OSBTYWx0ZWRfX0kUZBbAPQSrQ zxFzcXKHVmN+puUhF/XXykW9n/9sR7AUpc4f8JwK6RdKhryrYSFDbIcJfoUl8U6ecUt2xY2rZp+ s470k8WSt7lHqUXHguRXv5/HWvlP9PE6BTTKp4402KdeiWWcF6PyLYoqIZW1LgEu3MyT2HETHVH VHnPyW5WscrYj7IvmZEdAdWd9dPCt9NQYkC8+cd47tsH4uFpnbS/atled6Qq2x5Fd6Ng9hFPxEg 36wCqWEkXcrohbU6L42pg6dKSH5g7XMQ07OMD7VFJebZ5M3e/SoIYbLIDSE9NowEKGolK8VvHXX hacKu6idSJQJtd0muM+lgU2f9zs8+uGEYmp3dDovpgWqeai0ifAidXwrordErS9B4Kfd7B+heLX MNJ3I6pLqhwL3pqUcKeq8ktGhexgFmzSRvalDRdSvlvq77aYxT1CXTgXttInmP30Q9gwCXuhCyS srX4UFN++gMUOBzf45A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_02,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 clxscore=1015 spamscore=0 bulkscore=0 malwarescore=0 adultscore=0 priorityscore=1501 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609210079 On 9/20/2026 6:46 PM, Shawn Guo wrote: > On Sat, Sep 19, 2026 at 10:14:56AM +0530, Vishnu Reddy wrote: >> Add iris video codec to nord SoC, which comes with significantly different >> powering up sequence than previous platforms, thus different clocks and >> resets. >> >> Signed-off-by: Vishnu Reddy >> --- >> arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 114 ++++++++++++++++++++++++++++ >> 1 file changed, 114 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi >> index 74f4e6be8652..03f827f3e5fc 100644 >> --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi >> +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi >> @@ -1428,6 +1428,120 @@ camcc: clock-controller@9ce0000 { >> #power-domain-cells = <1>; >> }; >> >> + iris: video-codec@aa00000 { >> + compatible = "qcom,nord-iris", "qcom,glymur-iris"; >> + reg = <0x0 0x0aa00000 0x0 0xf0000>; > nord-embedded.dtsi is a place to accommodate Nord Embedded variant > specific resource descriptions, like clock, regulator, pinctrl, > interconnect, power domain, PHY, etc. The rest of descriptions should > go to nord.dtsi, like reg, interrupts, iommu, dma, etc. Will check and move it to nord.dtsi if no issues are found. > Shawn > >> + >> + clocks = <&nwgcc NW_GCC_VIDEO_AXI0_CLK>, >> + <&videocc VIDEO_CC_MVS0C_CLK>, >> + <&videocc VIDEO_CC_MVS0_CLK>, >> + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK>, >> + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>, >> + <&videocc VIDEO_CC_MVS0_FREERUN_CLK>, >> + <&nwgcc NW_GCC_VIDEO_AXI1_CLK>, >> + <&videocc VIDEO_CC_MVS1_CLK>, >> + <&videocc VIDEO_CC_MVS1_FREERUN_CLK>; >> + clock-names = "core_iface", >> + "core", >> + "vcodec0_core", >> + "vcodec0_iface", >> + "core_freerun", >> + "vcodec0_core_freerun", >> + "vcodec1_iface", >> + "vcodec1_core", >> + "vcodec1_core_freerun"; >> + >> + dma-coherent; >> + >> + interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, >> + <&mmss_noc MASTER_VIDEO_MVP0 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "cpu-cfg", >> + "video-mem"; >> + >> + interrupts = ; >> + >> + memory-region = <&video_mem>; >> + >> + operating-points-v2 = <&iris_opp_table>; >> + >> + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, >> + <&videocc VIDEO_CC_MVS0_GDSC>, >> + <&rpmhpd RPMHPD_MXC>, >> + <&rpmhpd RPMHPD_MMCX>, >> + <&videocc VIDEO_CC_MVS1_GDSC>; >> + power-domain-names = "venus", >> + "vcodec0", >> + "mxc", >> + "mmcx", >> + "vcodec1"; >> + >> + resets = <&nwgcc NW_GCC_VIDEO_AXI0_CLK_ARES>, >> + <&nwgcc NW_GCC_VIDEO_AXI0C_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>, >> + <&nwgcc NW_GCC_VIDEO_AXI1_CLK_ARES>, >> + <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>; >> + reset-names = "core_bus", >> + "vcodec0_bus", >> + "core", >> + "vcodec0_core", >> + "vcodec1_bus", >> + "vcodec1_core"; >> + >> + #address-cells = <1>; >> + #size-cells = <1>; >> + dma-ranges = <0x0 0x0 0x0 0xffe00000>; >> + >> + status = "disabled"; >> + >> + non-pixel { >> + iommus = <&apps_smmu_1 0x0940 0x20>, >> + <&apps_smmu_1 0x0944 0x0>, >> + <&apps_smmu_1 0x0960 0x20>; >> + iommu-ranges = <0x25800000 0xda600000>; >> + }; >> + >> + pixel { >> + iommus = <&apps_smmu_1 0x0943 0x0>; >> + }; >> + >> + iris_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-240000000 { >> + opp-hz = /bits/ 64 <240000000 240000000 360000000>; >> + required-opps = <&rpmhpd_opp_svs>, >> + <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-435000000 { >> + opp-hz = /bits/ 64 <435000000 435000000 652500000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-480000000 { >> + opp-hz = /bits/ 64 <480000000 480000000 720000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_nom>; >> + }; >> + >> + opp-533333333 { >> + opp-hz = /bits/ 64 <533333333 533333333 800000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>, >> + <&rpmhpd_opp_turbo>; >> + }; >> + >> + opp-560000000 { >> + opp-hz = /bits/ 64 <560000000 560000000 840000000>; >> + required-opps = <&rpmhpd_opp_nom>, >> + <&rpmhpd_opp_turbo_l1>; >> + }; >> + }; >> + }; >> + >> videocc: clock-controller@aaf0000 { >> compatible = "qcom,nord-videocc"; >> reg = <0x0 0x0aaf0000 0x0 0x10000>; >> >> -- >> 2.34.1 >> >>